coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Arthur Heymans (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58517/comment/93cb33e8_a00c23ab PS5, Line 48: the hardware of FSP > I think it's not FSP's fault. To me, it looks like _PRT just lacks the entry for PEG INT D. Well this should have FSP configure PIN A,B,C for the 3 PEG functions. It ends up using pin D. -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 14:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation/RFC: Generalize PCI support in coreboot
by Nico Huber (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Shelley Chen, Felix Singer, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Kyösti Mälkki, Yu-Ping Wu, Jianjun Wang. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57861 ) Change subject: Documentation/RFC: Generalize PCI support in coreboot ...................................................................... Patch Set 12: (1 comment) File Documentation/RFC/pci_config_access.md: https://review.coreboot.org/c/coreboot/+/57861/comment/31a2dc25_9aa347e2 PS12, Line 125: ### Specifying MMIO support for PCI devices that don't support ECAM : : We’ll need to be able to distinguish between a platform using the ECAM access : method and any other MMIO access mechanism. For devices that support ECAM, they : would have to select the `ECAM_MMONCF_SUPPORT` config. For devices that don't : support ECAM and would still need MMIO support, they would need to explictly : select the `NO_ECAM_MMCONF_SUPPORT` config and include the `pci_mmio_cfg.h' : header file in their platform-specific source. > Hi Shelley, […] The "example" linked below around get_pci_mmio_cfgbase() looks broken. I wouldn't worry about it too much right now. If you want to implement method 1. only, that seems fine. All you need in coreboot is pci_map_bus(). libpayload should get a similar mechanism eventually. NB. If you can, it would be helpful to provide links to public documentation of the hardware involved. -- To view, visit https://review.coreboot.org/c/coreboot/+/57861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a56d932f6e047087c38a7687564065cc1562363 Gerrit-Change-Number: 57861 Gerrit-PatchSet: 12 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 14:27:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Angel Pons (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58517/comment/2a172640_e211c883 PS5, Line 48: the hardware of FSP > > Whaaaaat??? FSP has hardware? Or is `of` a typo and should be `or` instead? […] I think it's not FSP's fault. To me, it looks like _PRT just lacks the entry for PEG INT D. -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 14:23:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/graphics/Kconfig: Guard options
by Nico Huber (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59471 ) Change subject: soc/intel/graphics/Kconfig: Guard options ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/common/block/graphics/Kconfig: https://review.coreboot.org/c/coreboot/+/59471/comment/de242334_59c20749 PS1, Line 13: config SOC_INTEL_DISABLE_IGD This one is actually implemented per soc. Doesn't seem to matter, but technically it doesn't depend on SOC_INTEL_COMMON_BLOCK_GRAPHICS. -- To view, visit https://review.coreboot.org/c/coreboot/+/59471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c252e31867e4560fb5aaf12273288f4ff18ae3d Gerrit-Change-Number: 59471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 14:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Angel Pons (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: I don't know why FIXED_INT_PIRQ is associated to PCIe functions. The entries in _PRT ignore the PCI function. -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 14:18:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Arthur Heymans (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58517/comment/9c9752d1_320d4508 PS5, Line 48: the hardware of FSP > Whaaaaat??? FSP has hardware? Or is `of` a typo and should be `or` instead? No idea what I even meant by that phrase xD. -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 13:54:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Arthur Heymans (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58517 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... soc/intel/cannonlake: Fix PEG1 _PRT generation Some weird things happen inside FSP and the routing is not correctly applied, with PIN D being used but lacking a proper routing in ACPI. To work around this issue generate _PRT for all 4 INT pins. Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58517/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Arthur Heymans (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... Patch Set 19: Code-Review+1 (1 comment) Patchset: PS19: Except that config file, things look good -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 19 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 13:53:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Set up LAPIC in pre MP init to fix SeaBIOS hang
by Arthur Heymans (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Arthur Heymans, Дмитрий Понаморев, Michał Żygowski, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57668 ) Change subject: soc/intel/denverton_ns: Set up LAPIC in pre MP init to fix SeaBIOS hang ...................................................................... Patch Set 9: (1 comment) Patchset: PS3: > Unfortunately adding setup_i8259(); i8259_configure_irq_trigger(9, 1); and isa_dma_init() to the lpc_init() in src/soc/intel/denverton_ns/lpc.c - doesn't fix the SeaBIOS hangs issue. My comment is not resolved. It's still only done on the BSP and not on APs when adding it to pre_mp_init(). -- To view, visit https://review.coreboot.org/c/coreboot/+/57668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Gerrit-Change-Number: 57668 Gerrit-PatchSet: 9 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 13:44:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Дмитрий Понаморев <dponamorev(a)gmail.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50
by David Wu (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Tim Wawrzynczak. David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59473 ) Change subject: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50 ...................................................................... [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50 Exchange i2c port for touchscreen and cr50. BUG=b:19583169 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I5c900568adb119871d6374294a27195d75699ea6 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/kano/overridetree.cb 3 files changed, 130 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59473/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 136bde6..0fb904d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -71,7 +71,15 @@ config DRIVER_TPM_I2C_BUS hex - default 0x3 + default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x3 if BOARD_GOOGLE_BRASK + default 0x3 if BOARD_GOOGLE_PRIMUS + default 0x3 if BOARD_GOOGLE_GIMBLE + default 0x3 if BOARD_GOOGLE_REDRIX + default 0x1 if BOARD_GOOGLE_KANO + default 0x3 if BOARD_GOOGLE_TAEKO + default 0x3 if BOARD_GOOGLE_FELWINTER + default 0x3 if BOARD_GOOGLE_ANAHERA config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 818ddd0..c7601e6 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h> @@ -161,6 +162,65 @@ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; +/* Early pad configuration in bootblock for board id 1 */ +static const struct pad_config early_gpio_table_id1[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), +}; + static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), @@ -174,8 +234,14 @@ const struct pad_config *variant_early_gpio_table(size_t *num) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + const uint32_t id = board_id(); + if (id == BOARD_ID_UNKNOWN || id < 1) { + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; + } + + *num = ARRAY_SIZE(early_gpio_table_id1); + return early_gpio_table_id1; } const struct pad_config *variant_romstage_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da..4287f41 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -11,6 +11,10 @@ option UFC_USB 0 option UFC_MIPI_OVTI2740 1 end + field TPM_I2C_BUS 38 38 + option I2C_BUS_3 0 + option I2C_BUS_1 1 + end end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" @@ -246,7 +250,16 @@ register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" register "key.label" = ""pen_eject"" - device generic 0 on end + device generic 0 on + probe TPM_I2C_BUS I2C_BUS_3 + end + end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on + probe TPM_I2C_BUS I2C_BUS_1 + end end end device ref i2c2 on @@ -408,7 +421,45 @@ chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + device i2c 50 on + probe TPM_I2C_BUS I2C_BUS_3 + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on + probe TPM_I2C_BUS I2C_BUS_1 + end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_D6 is the IRQ source, and GPP_D17 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" + register "key.wake_gpe" = "GPE0_DW1_17" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe TPM_I2C_BUS I2C_BUS_1 + end end end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c900568adb119871d6374294a27195d75699ea6 Gerrit-Change-Number: 59473 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021