coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Bora Guvendik, Maulik V Vaghela, Selma Bensaid, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57325 ) Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21753f2e5e9867f22c05e087cbf1f1e097d28bca Gerrit-Change-Number: 57325 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:22:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/chronicler: set DdrMemoryDown enable
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Sheng-Liang Pan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59373 ) Change subject: mb/google/volteer/var/chronicler: set DdrMemoryDown enable ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: just want to double check that we have the correct MRC version -- To view, visit https://review.coreboot.org/c/coreboot/+/59373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Gerrit-Change-Number: 59373 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 3: (4 comments) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/75fbaf22_ab79474b PS2, Line 11: void mutex_unlock(struct mutex *mutex); > So I wanted to make it so the lock/unlock asserts were checked regardless of threading or SMP. […] I don't think we should add all these calls to builds where they really do nothing at all, just to support assertions. They may get called pretty often in some contexts. The assertions will still get noticed on the SMP systems. I think these should become nothing (not even a call instruction to an empty function) on those platforms, so the checks should be in static inlines, or preprocessor guards. File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/38b699ab_173de68d PS2, Line 24: #if ENV_X86 > I haven't specifically looked at the ARM assembly generated by this. […] Hmmm... well, how sure are we that this is correct for RISC-V? I'm not familiar with that architecture but I'd be surprised if they don't have some sort of PAUSE instruction equivalent. We can do it this way for now if you want but I doubt it would really hold up for a lot of architectures. File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/b537d39a_a8e90d0b PS3, Line 27: continue; If we're keeping this code I find the continue here pretty weird -- the effect is the same as not having it. I'd just leave out the #else here. https://review.coreboot.org/c/coreboot/+/59320/comment/898cf794_68f789ba PS3, Line 31: } while (__atomic_load_1(&mutex->locked, __ATOMIC_RELAXED)); Are we sure this is guaranteed to make forward progress eventually, even with the relaxed model (i.e. does the memory model guarantee that a store by another CPU will eventually become visible to a relaxed load by this CPU within a finite amount of time even if there is no formal dependency declared)? -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 18:55:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Subrata Banik (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... Patch Set 2: -Code-Review (1 comment) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59392/comment/0c284b43_5b63e8d4 PS2, Line 51: # Enable CPU PCIE RP 2 using CLK 3 : register "cpu_pcie_rp[CPU_RP(2)]" = "{ : .clk_req = 3, : .clk_src = 3, : }" : move this to line 91 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 18:46:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 52: (1 comment) File src/ec/starlabs/merlin/Makefile.inc: https://review.coreboot.org/c/coreboot/+/58343/comment/6ef2b6bb_44405f80 PS51, Line 14: ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y) : ifeq ($(CONFIG_EC_STARLABS_ADD_ITE_BIN),y) : ifeq ($(CONFIG_EC_STARLABS_IT_BIN_PATH),) : files_added:: warn_no_ite_fw : : PHONY+=warn_no_ite_fw : warn_no_ite_fw: : printf "\n\t** WARNING **\n" : printf "coreboot has been built without the ITE EC Firmware.\n" : printf "Do not flash this image. Your laptop's power button\n" : printf "may not respond when you press it.\n\n" : : else : add_ite_fw: $(obj)/coreboot.pre : $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_IT_BIN_PATH) -u : : endif : endif : endif > ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 52 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Nov 2021 18:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add PLD to EC conn in ACPI table
by Prashant Malani (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Lance Zhao, Won Chung, Nick Vaccaro, Benson Leung, Prashant Malani. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59401 ) Change subject: ec/google/chromeec: Add PLD to EC conn in ACPI table ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59401/comment/fe40fd37_3c4647c7 PS1, Line 8: Add a commit message providing a bit more detail about what's being done in this CL. File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/59401/comment/b081cd54_b738bec9 PS1, Line 152: struct acpi_pld pld; Probably should be 0-initialized. -- To view, visit https://review.coreboot.org/c/coreboot/+/59401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f Gerrit-Change-Number: 59401 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 17:54:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add PLD to EC conn in ACPI table
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Lance Zhao, Won Chung, Nick Vaccaro, Benson Leung, Prashant Malani. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59401 ) Change subject: ec/google/chromeec: Add PLD to EC conn in ACPI table ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59401/comment/a44d257c_b99234cb PS1, Line 10: TEST=emerge-brya coreboot I believe you also tested this on a brya by dumping the SSDT and verifying the PLD object is written out under the EC CON* devices. File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/59401/comment/d1eee97a_09e3042a PS1, Line 125: struct drivers_usb_acpi_config *config; : : config = NULL; nit: `struct drivers_usb_acpi_config *config = NULL;` -- To view, visit https://review.coreboot.org/c/coreboot/+/59401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f Gerrit-Change-Number: 59401 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Benson Leung <bleung(a)chromium.org> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 17:52:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add ALC5682I-VS codec support
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59412 ) Change subject: mb/google/brya/var/felwinter: Add ALC5682I-VS codec support ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Since it's just the HID change, other ODMs have been doing this instead: https://review.coreboot.org/c/coreboot/+/59367/4/src/mainboard/google/brya/… -- To view, visit https://review.coreboot.org/c/coreboot/+/59412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c Gerrit-Change-Number: 59412 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 17:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/brya: Enable dev screen in bios-stage for Brask
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Adam Liu, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59414 ) Change subject: mainboard/google/brya: Enable dev screen in bios-stage for Brask ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59414/comment/0c074e3f_0b77fd0b PS3, Line 10: INTEL_GMA_HAVE_VBT For now, the VBTs are in the private repositories (NB I am working to change this but not done yet), so this change should go in config.brask with a cq-depend on the CL that adds the VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/59414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Gerrit-Change-Number: 59414 Gerrit-PatchSet: 3 Gerrit-Owner: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 17:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Joey Peng, Nick Vaccaro, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59411 ) Change subject: mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Gerrit-Change-Number: 59411 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 17:37:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021