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Change subject: drivers/tpm: Add always-shutdown-on-suspend DSD property
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/i2c/tpm/chip.c:
https://review.coreboot.org/c/coreboot/+/59479/comment/2d331c70_d27268d0
PS2, Line 53: suspend
Should we name this s0ix so it's not confused with S3?
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Change subject: amdfwtool: clean up psp fw parsing
......................................................................
Patch Set 2:
(3 comments)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/59449/comment/086a2c2b_58c72587
PS2, Line 109: };
> Nit: Please add a blank line.
Done
https://review.coreboot.org/c/coreboot/+/59449/comment/2b041ee1_7997509f
PS2, Line 110: psp_dir_valid_entries
> Why not merge this table with amd_fw_ps_table? Similar thing can be done for amd_bios_table, if requ […]
Yes that would be even better, definitely something should be planned. But it'd be a giant CL with changes in logic (I intentionally minimized it here). If you think it'd be better to have several cleanups within a CL let me know, I'll work on that.
https://review.coreboot.org/c/coreboot/+/59449/comment/b39a2328_1f1a4927
PS2, Line 178: if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) {
: if (!cb_config->have_whitelist)
: fw_type = AMD_FW_SKIP;
: }
> Now that you have fw_type, you can avoid strcmp and check against fw_type.
Yes that is on my mind for next cleanup, but again I didn't want it to be in this CL for keep this CL easy to review.
Also note that PSPBTLDR_AB_FILE and PSPBTLDR_WL_FILE have same fw_type but opposite condition for inclusion, so we can't abandon strmcmp completely for this logic.
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Hello build bot (Jenkins), Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59449
to look at the new patch set (#3).
Change subject: amdfwtool: clean up psp fw parsing
......................................................................
amdfwtool: clean up psp fw parsing
find_register_fw_filename_psp_dir parses first token from the fw.cfg and
find fw_type and subprog for it. However every entries are hard-coded,
which makes code to be hard to read and maintain.
Make a new lookup table so things are more organized than before.
TEST=build guybrush and confirm amdfw and coreboot.rom are identical
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c
---
M util/amdfwtool/data_parse.c
1 file changed, 81 insertions(+), 176 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59449/3
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Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/redrix/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59260/comment/b9714dca_c9baae5f
PS3, Line 351: register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
nit: this one is not required, D0 is the default if it is not set.
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Change subject: driver/intel/mipi_camera: Add support for _DSC field
......................................................................
Patch Set 11:
(1 comment)
File src/drivers/intel/mipi_camera/chip.h:
https://review.coreboot.org/c/coreboot/+/58767/comment/7f8a8d83_6ac043fe
PS10, Line 260: uint8_t max_dstate_for_probe;
> might be worth a thought to change the ACPI_DEVICE_SLEEP_D* defines in include/acpi/acpi. […]
Agreed, that's a good thought.
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Change subject: ChromeOS: Add legacy mainboard_ec_running_ro()
......................................................................
Patch Set 7:
(3 comments)
File src/include/bootmode.h:
https://review.coreboot.org/c/coreboot/+/58896/comment/4f496264_326bc929
PS7, Line 17: bool mainboard_ec_running_ro(void);
> (see https://review.coreboot.org/c/coreboot/+/58896/7/src/vendorcode/google/chro…. […]
ah right ec_is_trusted() has the latched behavior.
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/58896/comment/f961b7fc_f6c62ff7
PS5, Line 42: chromeos_acpi = cbmem_add(CBMEM_ID_ACPI_CNVS, sizeof(struct chromeos_acpi));
> What should we do on S3 resume path? Never modify CNVS?
That would be my thinking, I can't see a good reason that any of this should be modified during resume.
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/58896/comment/6fb1b1a5_3945e4d9
PS7, Line 67: }
> ... Can't we just get rid of this and related callbacks?
That's a good point Julius, I guess is a fallback ? b/c of EC sync, it does make sense to just leave this to depthcharge.
> What does the existing code do?
ACPI tables are not re-written during S3 suspend, the boot state machine resumes OS execution before BS_WRITE_TABLES anyway, so they are just left alone in the memory from the original boot. I don't think going in and tinkering with any existing tables seems like a good idea.
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Change subject: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value()
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59390/comment/79c2da4f_32a5a138
PS3, Line 7: /../
Why are these dots there?
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Change subject: src/security/vboot: Setup secure counter space in TPM NVRAM
......................................................................
Patch Set 1:
(4 comments)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/59476/comment/4b43b225_fbee9878
PS1, Line 159: .TPMA_NV_PPWRITE = 1,
> Similar to the discussion in https://review.coreboot.org/c/coreboot/+/59097/3.. […]
good point. yes, NO_DA makes sense
https://review.coreboot.org/c/coreboot/+/59476/comment/715ccfe3_83de2741
PS1, Line 368: rv = tlcl_read(index, &value, SECURE_COUNTER_SIZE);
> What's the point of this check? When we're going through factory init, this counter should never exi […]
actually, it may exist. if factory init was interrupted after creating this index, but before creating the f/w index, it will be there.
https://review.coreboot.org/c/coreboot/+/59476/comment/997f5f7e_f5a290bf
PS1, Line 369: !=
> Should we check for TPM_SUCCESS instead? I'm concerned this will let other errors through.
!= TPM_E_BADINDEX also makes sure that the index is created and written. but I agree shall be careful with error handling not to block factory init if the counter was created but not written (sudden reset between).
https://review.coreboot.org/c/coreboot/+/59476/comment/27ef8056_6fd1046a
PS1, Line 416: RETURN_ON_FAILURE(setup_secure_counter_spaces());
> The firmware space should always be the last one that is created, since this code uses that to confi […]
yes, the firmware space shall always be the last since its presence is the "factory init complete" check.
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Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59479 )
Change subject: drivers/tpm: Add always-shutdown-on-suspend DSD property
......................................................................
drivers/tpm: Add always-shutdown-on-suspend DSD property
Introduce always-shutdown-on-suspend DSD ACPI property for TPM devices.
This flag can be used by the kernel TPM driver to override the checks
used to determine when a TPM shutdown should be sent. A shutdown will
normally only be sent for S3 or S5 suspend (determined by
pm_suspend_via_firmware). Some platforms also reset the TPM in S0i3,
so a shutdown is always needed on suspend.
BUG=b:200578885
BRANCH=None
TEST=Shutdown is triggered on s0ix suspend on guybrush with patched
kernel
Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/drivers/i2c/tpm/chip.c
M src/drivers/i2c/tpm/chip.h
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59479/1
diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c
index 07791c3..3f7186e 100644
--- a/src/drivers/i2c/tpm/chip.c
+++ b/src/drivers/i2c/tpm/chip.c
@@ -11,6 +11,7 @@
static void i2c_tpm_fill_ssdt(const struct device *dev)
{
+ struct acpi_dp *dsd;
struct drivers_i2c_tpm_config *config = dev->chip_info;
const char *scope = acpi_device_scope(dev);
struct acpi_i2c i2c = {
@@ -47,6 +48,12 @@
acpigen_write_resourcetemplate_footer();
+ /* _DSD, Device-Specific Data */
+ dsd = acpi_dp_new_table("_DSD");
+ acpi_dp_add_integer(dsd, "always-shutdown-on-suspend",
+ config->always_shutdown_on_suspend);
+ acpi_dp_write(dsd);
+
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h
index 0ab10d7..c688b1c 100644
--- a/src/drivers/i2c/tpm/chip.h
+++ b/src/drivers/i2c/tpm/chip.h
@@ -10,4 +10,5 @@
enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */
struct acpi_irq irq; /* Interrupt */
struct acpi_gpio irq_gpio; /* GPIO interrupt */
+ bool always_shutdown_on_suspend; /* Always shutdown TPM on suspend */
};
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