coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/guybrush: Add variant_tpm_gpio_table
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59083 ) Change subject: mb/google/guybrush: Add variant_tpm_gpio_table ...................................................................... mb/google/guybrush: Add variant_tpm_gpio_table Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/verstage.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 8 files changed, 92 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 1154444..2791a8f 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -53,6 +53,9 @@ gpios = variant_espi_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + gpios = variant_early_gpio_table(&num_gpios); override_gpios = variant_early_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 0720bc2..c9b533e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -199,16 +199,6 @@ /* WWAN_RST_L */ PAD_GPO(GPIO_24, LOW), -/* Enable ESPI, GSC Interrupt & I2C Communication */ - /* Unused */ - PAD_NC(GPIO_3), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), @@ -237,6 +227,15 @@ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -353,3 +352,9 @@ *size = ARRAY_SIZE(espi_gpio_table); return espi_gpio_table; } + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 0dc6c7b..b50a590 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -43,6 +43,9 @@ /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void); void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index e90f4a3..fe2dcd1 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -44,10 +44,6 @@ static const struct soc_amd_gpio override_early_gpio_table[] = { /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ - PAD_NC(GPIO_85), }; /* This table is used by guybrush variant with board version < 2. */ @@ -56,6 +52,15 @@ PAD_GPO(GPIO_70, HIGH), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -92,3 +97,9 @@ return NULL; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index a2a0e93..00fd964 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -39,8 +39,6 @@ }; static const struct soc_amd_gpio override_early_gpio_table[] = { - /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), }; @@ -48,6 +46,27 @@ PAD_NC(GPIO_18), }; + +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -72,3 +91,16 @@ *size = ARRAY_SIZE(override_pcie_gpio_table); return override_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_tpm_gpio_table); + return bid1_tpm_gpio_table; + } + + *size = ARRAY_SIZE(bid2_tpm_gpio_table); + return bid2_tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index 17481d2..35bfa0a 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -46,3 +46,15 @@ dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; pm_io_write32(PM_ACPI_CONF, dword); } + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index dbdf2f2..ef8a9da 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -49,6 +49,7 @@ uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); void verstage_mainboard_espi_init(void); +void verstage_mainboard_tpm_init(void); void verstage_soc_aoac_init(void); void verstage_soc_espi_init(void); void verstage_soc_i2c_init(void); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 8fc2732..71f07c0 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -25,7 +25,9 @@ void __weak verstage_mainboard_early_init(void) {} void __weak verstage_mainboard_espi_init(void) {} +void __weak verstage_mainboard_tpm_init(void) {} void __weak verstage_mainboard_init(void) {} + uint32_t __weak get_max_workbuf_size(uint32_t *size) { /* This svc only exists in picasso and deprecated for later platforms. @@ -238,15 +240,19 @@ printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); verstage_mainboard_espi_init(); + printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); + verstage_soc_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_mainboard_tpm_init\n"); + /* mainboard_tpm_init may check board_id, so make sure espi is ready first */ + verstage_mainboard_tpm_init(); + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); verstage_mainboard_early_init(); svc_write_postcode(POSTCODE_LATE_INIT); fch_io_enable_legacy_io(); - printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); - verstage_soc_espi_init(); - printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); verstage_soc_aoac_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/59083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Gerrit-Change-Number: 59083 Gerrit-PatchSet: 9 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct USB3 TCSS setting
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59385 ) Change subject: mb/google/brya/var/felwinter: Correct USB3 TCSS setting ...................................................................... mb/google/brya/var/felwinter: Correct USB3 TCSS setting Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c 2 files changed, 10 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 5b90b9a..b1980f6 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -38,6 +38,12 @@ device domain 0 on device ref dtt on end device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_KB8001 + end + device ref tbt_pcie_rp2 on + probe DB_USB USB4_KB8001 + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -45,6 +51,7 @@ end end device ref tcss_dma0 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port2 as dfp[0].typec_port @@ -52,12 +59,11 @@ end end device ref tcss_dma1 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on - probe DB_USB USB4_KB8001 - end + device generic 0 on end end end device ref pcie_rp6 off end diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index 9234019..ee39ef0 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -9,5 +9,6 @@ if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) { config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19; config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20; + config->TcssAuxOri = 0x10; } } 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Gerrit-Change-Number: 59385 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/gimble: Include 2 new SPDs
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59299 ) Change subject: mb/google/brya/var/gimble: Include 2 new SPDs ...................................................................... mb/google/brya/var/gimble: Include 2 new SPDs Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B and MT53E512M32D1NP-046 WT:B. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/gimble/memory/Makefile.inc M src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Mark Hsieh: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc index 187d4c9..9db9484 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt index 02c1019..c3a1347 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt @@ -10,3 +10,5 @@ MT53E1G32D2NP-046 WT:A 2 (0010) K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt index 7cb0e23..568e724 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt @@ -4,3 +4,5 @@ MT53E1G32D2NP-046 WT:A K4U6E3S4AA-MGCR K4UBE3D4AA-MGCR +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/59299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Gerrit-Change-Number: 59299 Gerrit-PatchSet: 7 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: De-assert SSD PERST# in romstage
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59269 ) Change subject: mb/google/brya/var/redrix: De-assert SSD PERST# in romstage ...................................................................... mb/google/brya/var/redrix: De-assert SSD PERST# in romstage After CB:57539 applied, it can support romstage GPIO table override. We can move SSD PERST# de-assertion to romstage. The reason for this is to give enough time after PERST# deassertion so that the SSD has enough time to initialize before the FSP scans the RPs for downstream devices. BUG=b:199714453 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 20d6b48..afcb7e9 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -116,7 +116,7 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and - * then deassert PERST# in ramstage + * then deassert PERST# in romstage */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), @@ -125,6 +125,8 @@ }; static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Gerrit-Change-Number: 59269 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Correct WWAN power sequence
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59267 ) Change subject: mb/google/brya/var/redrix: Correct WWAN power sequence ...................................................................... mb/google/brya/var/redrix: Correct WWAN power sequence Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/redrix/Makefile.inc M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix/include/variant/gpio.h 4 files changed, 34 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4afee74..11f9b69 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -42,6 +42,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_KANO bool "-> Kano" diff --git a/src/mainboard/google/brya/variants/redrix/Makefile.inc b/src/mainboard/google/brya/variants/redrix/Makefile.inc index acf9bad..446d113 100644 --- a/src/mainboard/google/brya/variants/redrix/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index f35e0fd..20d6b48 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -37,13 +37,14 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC(GPP_E20, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), - /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), @@ -67,11 +68,17 @@ PAD_NC(GPP_S6, NONE), /* S7 : SNDW3_DATA ==> NC */ PAD_NC(GPP_S7, NONE), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -91,16 +98,18 @@ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> NC */ - PAD_NC(GPP_E0, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -115,6 +124,11 @@ PAD_CFG_GPO(GPP_B4, 0, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -126,3 +140,9 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h index c4fe342..99d09b2 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Gerrit-Change-Number: 59267 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure Acoustic noise mitigation
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58947 ) Change subject: mb/google/brya/var/redrix: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/redrix: Configure Acoustic noise mitigation Enable Acoustic noise mitigation for redrix and set slew rate to 1/8 BUG=b:204009588 TEST=build and verified by power team Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 777ac11..dc1a424 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -37,6 +37,11 @@ # FIVR RFI Spread Spectrum 6% register "FivrSpreadSpectrum" = "FIVR_SS_6" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/58947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Gerrit-Change-Number: 58947 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... soc/intel/alderlake: Add Acoustic noise mitigation UPDs This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:204009588 TEST=build Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58944 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index d259442..78f639c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -151,6 +151,21 @@ FIVR_SS_6 = 44, }; +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16 +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -528,6 +543,15 @@ * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. */ uint8_t FivrSpreadSpectrum; + /* Enable or Disable Acoustic Noise Mitigation feature */ + uint8_t AcousticNoiseMitigation; + /* Disable Fast Slew Rate for Deep Package C States for VR domains */ + uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS]; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values + */ + uint8_t SlowSlewRate[NUM_VR_DOMAINS]; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 17edada..e43335e 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -739,6 +739,19 @@ s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; } +static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + + if (s_cfg->AcousticNoiseMitigation) { + for (int i = 0; i < NUM_VR_DOMAINS; i++) { + s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; + s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i]; + } + } +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -770,6 +783,7 @@ fill_fsps_irq_params, fill_fsps_fivr_params, fill_fsps_fivr_rfi_params, + fill_fsps_acoustic_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 6 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... amdfwtool: Call the set_efs_table for Stoneyridge Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 5 files changed, 34 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 0febf29..46b6707 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -34,4 +34,12 @@ bool default y +if !EM100 +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz +endif + endif # BOARD_AMD_GARDENIA diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 96f8696..3c64497 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -58,4 +58,12 @@ If changed, make sure fan_init.c IO window setting. The HWM (Hardware Monitor) is used for fan control within padmelon. +if !EM100 +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz +endif + endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 5940d1a..29edb30 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -123,6 +123,14 @@ depends on USE_OEM_BIN default "" +if !EM100 +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz +endif + # Don't use AMD's Secure OS config USE_PSPSECUREOS def_bool n diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d265651..7d0b86d 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -132,6 +132,9 @@ OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -147,6 +150,8 @@ $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ $(OPT_COMBOCAPABLE)\ $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ $(OPT_SOCNAME) \ --flashsize $(CONFIG_ROM_SIZE) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 2c0b3e2..98e3189 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1586,13 +1586,11 @@ amd_romsig->xhci_entry = 0; if (soc_id != PLATFORM_UNKNOWN) { - if (soc_id != PLATFORM_STONEYRIDGE) { - retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, - efs_spi_speed, efs_spi_micron_flag); - if (retval) { - fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); - return retval; - } + retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, + efs_spi_speed, efs_spi_micron_flag); + if (retval) { + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); + return retval; } } else { fprintf(stderr, "WARNING: No SOC name specified.\n"); 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Set flag comboable as bool type
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59093 ) Change subject: amdfwtool: Set flag comboable as bool type ...................................................................... amdfwtool: Set flag comboable as bool type Fix the CL: https://review.coreboot.org/c/coreboot/+/58942 The type comboable was int but set as true. Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 38f0e62..2c0b3e2 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1274,7 +1274,7 @@ char *rom = NULL; embedded_firmware *amd_romsig; psp_directory_table *pspdir; - int comboable = 0; + bool comboable = false; int fuse_defined = 0; int targetfd; char *output = NULL, *config = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/59093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de Gerrit-Change-Number: 59093 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Add a union for combo and psp directory
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58557 ) Change subject: amdfwtool: Add a union for combo and psp directory ...................................................................... amdfwtool: Add a union for combo and psp directory For combo layout, this is for combo header. For non-combo layout, this is for PSP directory. Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ee360f0..38f0e62 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1618,7 +1618,7 @@ } if (comboable) - amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, pspdir); + amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); else amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index a7ac7c1..3136bf6 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -88,7 +88,10 @@ uint32_t gec_entry; uint32_t xhci_entry; uint32_t psp_directory; - uint32_t combo_psp_directory; + union { + uint32_t new_psp_directory; + uint32_t combo_psp_directory; + }; uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; -- To view, visit https://review.coreboot.org/c/coreboot/+/58557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9 Gerrit-Change-Number: 58557 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021