coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 682 power configurations
by Curtis Chen (Code Review) 19 Nov '21

19 Nov '21

Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59483 ) Change subject: soc/intel/alderlake: Add ADLP 682 power configurations ...................................................................... soc/intel/alderlake: Add ADLP 682 power configurations Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 682 sku power related settings. BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59483/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 78f639c..da23ee0 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -52,6 +52,7 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_682_45W_CORE, TDP_45W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e43335e..0ceaeb0 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -302,6 +302,7 @@ } switch (mch_id) { + case PCI_DEVICE_ID_INTEL_ADL_P_ID_1: case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: return ICC_MAX_ID_ADL_P_3_MA; case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 99caacb..c6cf66d 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -48,6 +48,7 @@ } static const struct vr_lookup vr_config_ll[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -55,6 +56,7 @@ }; static const struct vr_lookup vr_config_icc[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, @@ -62,6 +64,7 @@ }; static const struct vr_lookup vr_config_tdc_timewindow[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -69,6 +72,7 @@ }; static const struct vr_lookup vr_config_tdc_currentlimit[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 05:00:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value()
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59390 ) Change subject: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value() ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59390/comment/8499faf0_aa7715da PS3, Line 7: /../ > Why are these dots there? soc/intel/common/block/thermal: Replaced "common/block" => ".." to met 72 char guideline. Any suggestion on this ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 04:59:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Meera Ravindranath (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Angel Pons. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59392/comment/01dfb8a4_d38ef4c3 PS2, Line 51: # Enable CPU PCIE RP 2 using CLK 3 : register "cpu_pcie_rp[CPU_RP(2)]" = "{ : .clk_req = 3, : .clk_src = 3, : }" : > move this to line 91 ? Missed that, Thanks :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 04:56:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Meera Ravindranath (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Meera Ravindranath. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59392 to look at the new patch set (#3). Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... mb/intel/adlrvp: Enable CPU PCIe RP 2 Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression) causes regression in NVMe boot on ADL-P RVP boards. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59392/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/var/brask: set power limits for thermal
by David Wu (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak. David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59482 ) Change subject: mb/google/brask/var/brask: set power limits for thermal ...................................................................... mb/google/brask/var/brask: set power limits for thermal Set power limits for brask based on CPU SKUs. BUG=b:197475210 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ia2b6f229ce9b9574c79f89c790716c7069876b7f --- M src/mainboard/google/brya/variants/brask/Makefile.inc A src/mainboard/google/brya/variants/brask/ramstage.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59482/1 diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c new file mode 100644 index 0000000..06040e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2b6f229ce9b9574c79f89c790716c7069876b7f Gerrit-Change-Number: 59482 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brask: create dynamic power limits mechanism for thermal
by David Wu (Code Review) 19 Nov '21

19 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59481 ) Change subject: mb/google/brask: create dynamic power limits mechanism for thermal ...................................................................... mb/google/brask: create dynamic power limits mechanism for thermal Add dynamic power limits selection mechanism for brask board based on CPU SKUs which is detectable at runtime. BUG=b:197475210 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Iabbf04c2e87d255398b5a29149befe1f78f064aa --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59481/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 1693d2e..8a4b2ac 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c new file mode 100644 index 0000000..9c2d4aa --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +WEAK_DEV_PTR(dptf_policy); + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabbf04c2e87d255398b5a29149befe1f78f064aa Gerrit-Change-Number: 59481 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs
by shkim (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59480 to review the following change. Change subject: mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs ...................................................................... mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 --- M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/59480/1 diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index e1318a8..de1e46d 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,6 +2,12 @@ # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + # Disable PCIe Root Port 8 (index 7) register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) -- To view, visit https://review.coreboot.org/c/coreboot/+/59480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Gerrit-Change-Number: 59480 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Use command line option use-combo to decide if use combo
by Bao Zheng (Code Review) 19 Nov '21

19 Nov '21

Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55455 ) Change subject: amdfwtool: Use command line option use-combo to decide if use combo ...................................................................... Patch Set 21: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/55455/comment/0c5f5230_1a6422e2 PS20, Line 1567: if (comboable) : amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); : else : amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); : : if (cb_config.use_combo) { : psp_combo_directory *combo_dir = new_combo_dir(&ctx); : amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); : /* 0 -Compare PSP ID, 1 -Compare chip family ID */ : combo_dir->entries[0].id_sel = 0; : combo_dir->entries[0].id = get_psp_id(cb_config.soc_id); : combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); : : combo_dir->header.lookup = 1; : fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); : } > create a new function to set psp_directory. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Gerrit-Change-Number: 55455 Gerrit-PatchSet: 21 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 04:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 43: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133753): https://review.coreboot.org/c/coreboot/+/57131/comment/41e020f8_b8a57049 PS43, Line 1890: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 43 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 19 Nov 2021 03:32:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021