coreboot-gerrit November 2021

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... mb/intel/adlrvp: Enable CPU PCIe RP 2 Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression) causes regression in NVMe boot on ADL-P RVP boards. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8926887..2c45e85 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,6 +83,12 @@ .clk_src = 0, }" + # Enable CPU PCIE RP 2 using CLK 3 + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + }" + # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Merging this CL that fixes boot regression. -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 06:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS
by build bot (Jenkins) (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59367 ) Change subject: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/primus/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133772): https://review.coreboot.org/c/coreboot/+/59367/comment/92cd203f_9e07601d PS5, Line 26: if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/59367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Gerrit-Change-Number: 59367 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 06:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS
by Malik Hsu (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak. Malik Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59367 ) Change subject: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/brya/variants/primus/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59367/comment/58ce5f89_d59d4786 PS4, Line 188: end > should there be another probe statement here too? […] Done File src/mainboard/google/brya/variants/primus/variant.c: https://review.coreboot.org/c/coreboot/+/59367/comment/6182f96c_4e89adf0 PS4, Line 28: audio_codec->enabled = 1; > if you add the probe statement to the devicetree, you don't need this here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Gerrit-Change-Number: 59367 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 06:16:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamp: Add new helper functions
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Tim Wawrzynczak, Julius Werner, Angel Pons, Aaron Durbin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add new helper functions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/4b2e9120_197c82cf PS3, Line 7: Add helper fucntions > Hi Bora, > > Not sure if you've heard yet, but Furquan isn't working on coreboot anymore. I believe +Tim is taking over some of his former work, although I'm not sure if he has context on this effort. I can also try to help although I'm not familiar with your platform in particular. > > You are right, of course, that the formula should be `base_delta * ts->tick_freq_mhz / base_freq_mhz`, not `base_delta * base_freq_mhz / ts->tick_freq_mhz`. > > However, looking at this again with a few months distance, I'm actually not so sure anymore why we even need all this rewind() stuff. Fundamentally, your reason for doing that was just that some of the new timestamps you were trying to add are chronologically *before* the base_time, right? I guess we have other options as well to create 2 cbmem tables 1. with Pre-CPU reset timestamp (that we are implementing newly from ADL onwards) 2. with Post-CPU reset timestamp (regular cbmem -t on IA platform) Now we would like to create things organically where #2 above can rebase based on #1. Additionally, unlike some other SoC platform, where #1 can be collected as early after CPU reset, is not likely the case with IA platform. Rather when we are able to collect #1 (typically, at early romstage state or late might be), we already have #2 available. It makes things more complicated as we would like to make the timestamp appear as if we have collected #1 prior to #2, which is not the case unfortunately. It poses the requirement of rewinding the #2 table based on #1 timestamp. I had thought of simple merging #1 and #2 together without rebasing but Furquan has suggested it might not portrait the exact situation nicely. > But why is that such a problem? Alternatively, we could just redefine (struct timestamp_entry).entry_stamp from uint64_t to int64_t, and declare that it should be allowed to be negative. Then I don't think you need any API changes here and just need to modify utils/cbmem to be aware of that case, and "rebase" all of those timestamps to the lowest one in the list when displaying them. I kind of get what your are suggesting but I would let Bora to share a sample timestamp for #1 and #2 above to illustrate the scenario. Want to make sure we have exact timestamp value appearing at base rather delta which may not be the exact while doing (Tn - T(n-1)) = negative number. > I think that would require the minimum amount of extra logic in firmware code because you can basically just use timestamp_add() and pass a (potentially) negative number. (You may still need to do frequency conversions, that's where my other suggestion would come in of just rewrite x86's timestamp_get() to immediately convert to microseconds -- all other architecture ports already do it that way anyway, and then we'll never have any of this frequency confusion anymore.) This is good suggestion, if all other arch does the same, its easy to implement and land the CL in that way. Thanks for suggestion. > > What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 06:14:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 442 power configurations
by Curtis Chen (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59483 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add ADLP 442 power configurations ...................................................................... soc/intel/alderlake: Add ADLP 442 power configurations Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 442 sku power related settings. BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59483/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/google/brya: Enable dev screen in bios-stage for Brask
by Adam Liu (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Alan Huang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59414 to look at the new patch set (#7). Change subject: mainboard/google/brya: Enable dev screen in bios-stage for Brask ...................................................................... mainboard/google/brya: Enable dev screen in bios-stage for Brask Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION. TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage. BUG=b:199490251, b:206014054 Signed-off-by: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59414/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Gerrit-Change-Number: 59414 Gerrit-PatchSet: 7 Gerrit-Owner: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 53: (1 comment) Patchset: PS46: > Sure understood. I will upload a separate patch to disable PSE first before this patch. Hi Michael, done! :) https://review.coreboot.org/c/coreboot/+/59484 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 53 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 19 Nov 2021 05:11:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Disable Intel PSE by default
by Lean Sheng Tan (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Patrick Rudolph. Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59484 ) Change subject: soc/intel/elkhartlake: Disable Intel PSE by default ...................................................................... soc/intel/elkhartlake: Disable Intel PSE by default Disable PSE loading by default. If left enabled (current default), the EHL coreboot will end up in endless restart loop, due to FSP unable to locate PSE FW image and trigger global reset. However disabling this flag (PchPseEnable) will cause the coreboot to trigger a single reset due to CSE signal (HECI: CSE does not meet required prerequisites). The reason behind this is that FSP need to perform static disabling (power gate) to fully shut down PSE HW, and to do this will need to global reset entire system including CSE. Then PMC will power gate PSE from the start. To avoid this behavior, the best way to disable PSE is to disable via IFWI FIT softstrap (For specific detail can refer to Intel PSE documentation). With this, PMC will power gate PSE from the first cold boot and system will boot happily without sigle reset behavior. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f --- M src/soc/intel/elkhartlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59484/1 diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index a15b030..ecb6304 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,8 @@ config->ibecc.region_mask); } } + /* PSE (Intel Programmable Services Engine) switch */ + m_cfg->PchPseEnable = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/59484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Gerrit-Change-Number: 59484 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55367 to look at the new patch set (#53). Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enables the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 172 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 53 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021