coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/ppc64/boot.c: handle non-OPD entry point
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57083 ) Change subject: arch/ppc64/boot.c: handle non-OPD entry point ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309be370d66a808b355241fcee880883631f38ce Gerrit-Change-Number: 57083 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:30:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu/power9: add file structure for power9, implement SCOM access
by Krystian Hebel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Felix Singer, Arthur Heymans, Sergii Dmytruk, Timothy Pearson, Ron Minnich. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57078 ) Change subject: src/cpu/power9: add file structure for power9, implement SCOM access ...................................................................... Patch Set 11: (1 comment) File src/include/cpu/power/scom.h: https://review.coreboot.org/c/coreboot/+/57078/comment/4799aeb8_e78f23f1 PS11, Line 91: static uint64_t read_scom_direct(uint64_t reg_address) : { : uint64_t val; : uint64_t hmer = 0; : do { : /* : * Clearing HMER on every SCOM access seems to slow down CCS up : * to a point where it starts hitting timeout on "less ideal" : * DIMMs for write centering. Clear it only if this do...while : * executes more than once. : */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "ldcix %0, %1, %2" : : "=r"(val) : : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) { : reset_scom_engine(); : /* : * All F's are returned in case of error, but code polls for a set bit : * after changes that can make such error appear (e.g. clock settings). : * Return 0 so caller won't have to test for all F's in that case. : */ : return 0; : } : return val; : } : : static void write_scom_direct(uint64_t reg_address, uint64_t data) : { : uint64_t hmer = 0; : do { : /* See comment in read_scom_direct() */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "stdcix %0, %1, %2":: : "r"(data), : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) : reset_scom_engine(); : } > What is the rationale to not put this in a compilation unit? None at this moment I guess. It started as just inlined `asm volatile(...); eieio();` but got way more complicated since. This should be moved to scom.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/57078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Gerrit-Change-Number: 57078 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:30:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Paul Menzel, Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57082 ) Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... Patch Set 12: (7 comments) Patchset: PS12: I'm pretty confused about all these symbols in ramstage. Most of these are in cbmem by that time. File src/mainboard/emulation/qemu-power9/memlayout.ld: https://review.coreboot.org/c/coreboot/+/57082/comment/5ed7d971_6a94e737 PS12, Line 24: STACK(0xa000000, 32K) I might be wrong but I haven't seen the stage entry move the stack pointer to this so this ends up not being consumed. https://review.coreboot.org/c/coreboot/+/57082/comment/a4174048_23b33368 PS12, Line 27: FMAP_CACHE(0xa108000, 4K) gets migrated to cbmem. https://review.coreboot.org/c/coreboot/+/57082/comment/34f0ef3a_25baca75 PS12, Line 28: CBFS_MCACHE(0xa109000, 8K) This gets migrated to cbmem. https://review.coreboot.org/c/coreboot/+/57082/comment/bf647b00_62f3c274 PS12, Line 29: TIMESTAMP(0xa10b000, 4K) Is that not in cbmem in ramstage? https://review.coreboot.org/c/coreboot/+/57082/comment/ea7751f8_0f9f9a45 PS12, Line 30: CBFS_CACHE(0xa10c000, 512K) Not sure if needed in ramstage. https://review.coreboot.org/c/coreboot/+/57082/comment/92e69e32_5a0ecd97 PS12, Line 31: PRERAM_CBMEM_CONSOLE(0xf918c000, 128K) not needed in ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:28:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu/power9: add file structure for power9, implement SCOM access
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Felix Singer, Krystian Hebel, Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57078 ) Change subject: src/cpu/power9: add file structure for power9, implement SCOM access ...................................................................... Patch Set 11: (1 comment) File src/include/cpu/power/scom.h: https://review.coreboot.org/c/coreboot/+/57078/comment/3a61bb81_54109ee0 PS11, Line 91: static uint64_t read_scom_direct(uint64_t reg_address) : { : uint64_t val; : uint64_t hmer = 0; : do { : /* : * Clearing HMER on every SCOM access seems to slow down CCS up : * to a point where it starts hitting timeout on "less ideal" : * DIMMs for write centering. Clear it only if this do...while : * executes more than once. : */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "ldcix %0, %1, %2" : : "=r"(val) : : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) { : reset_scom_engine(); : /* : * All F's are returned in case of error, but code polls for a set bit : * after changes that can make such error appear (e.g. clock settings). : * Return 0 so caller won't have to test for all F's in that case. : */ : return 0; : } : return val; : } : : static void write_scom_direct(uint64_t reg_address, uint64_t data) : { : uint64_t hmer = 0; : do { : /* See comment in read_scom_direct() */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "stdcix %0, %1, %2":: : "r"(data), : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) : reset_scom_engine(); : } What is the rationale to not put this in a compilation unit? -- To view, visit https://review.coreboot.org/c/coreboot/+/57078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Gerrit-Change-Number: 57078 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/ppc64/arch_timer.c: implement timer functions
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57077 ) Change subject: src/arch/ppc64/arch_timer.c: implement timer functions ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a244df01f6d15cbefb3b01079f6eec943136983 Gerrit-Change-Number: 57077 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ppc64/bootblock_crt0.S: minimal implementation for bootblock C enviro...
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57076 ) Change subject: ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0 Gerrit-Change-Number: 57076 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:15:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add ADLP 442 power configurations
by Curtis Chen (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59483 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Add ADLP 442 power configurations ...................................................................... soc/intel/alderlake: Add ADLP 442 power configurations Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 442 sku power related settings. BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59483/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Gerrit-Change-Number: 59483 Gerrit-PatchSet: 3 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/ppc64/include/arch/io.h: implement IO functions
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57075 ) Change subject: arch/ppc64/include/arch/io.h: implement IO functions ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib65c99888ba2e616893a55dff47d2b445052fa7c Gerrit-Change-Number: 57075 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:12:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Nico Huber, Paul Menzel, Julius Werner, Sergii Dmytruk, Ron Minnich, Timothy Pearson. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57074 ) Change subject: drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64 ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d Gerrit-Change-Number: 57074 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:10:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Sergii Dmytruk, Ron Minnich, Timothy Pearson. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57079 ) Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard ...................................................................... Patch Set 11: Code-Review+1 (2 comments) File src/mainboard/emulation/qemu-power9/board.fmd: https://review.coreboot.org/c/coreboot/+/57079/comment/907413e8_8cf63a7b PS11, Line 12: FLASH@0 CONFIG_ROM_SIZE { : BIOS@0 CONFIG_ROM_SIZE { : BOOTBLOCK 128K : FMAP 0x200 : COREBOOT(CBFS) : } : } This looks identical to util/cbfstool/default.fmd. Use that? File src/mainboard/emulation/qemu-power9/cbmem.c: https://review.coreboot.org/c/coreboot/+/57079/comment/7769b1a8_d9973e7c PS11, Line 9: (1ULL << 32) - 1048576 4ULL * GiB - 1 * MiB -- To view, visit https://review.coreboot.org/c/coreboot/+/57079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Gerrit-Change-Number: 57079 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 10:10:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021