coreboot-gerrit November 2021

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Change in blobs[master]: mb/teleplatforms/D4E4S168: Add blobs
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Дмитрий Понаморев, Paul Menzel, Arthur Heymans, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/57196 ) Change subject: mb/teleplatforms/D4E4S168: Add blobs ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Are those binaries redistributable? No idea because there's no license for them, see comment in https://review.coreboot.org/c/blobs/+/57196/4..5//COMMIT_MSG#11 -- To view, visit https://review.coreboot.org/c/blobs/+/57196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I71de576aa283fe6738138ad023d70c282045f5cc Gerrit-Change-Number: 57196 Gerrit-PatchSet: 5 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:42:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in blobs[master]: mb/teleplatforms/D4E4S168: Add blobs
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Дмитрий Понаморев, Paul Menzel, Arthur Heymans, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/57196 ) Change subject: mb/teleplatforms/D4E4S168: Add blobs ...................................................................... Patch Set 5: (2 comments) File mainboard/teleplatforms/D4E4S16P8/README.md: https://review.coreboot.org/c/blobs/+/57196/comment/184fdb3f_76d82cdd PS5, Line 1: contens typo: conten*t*s File mainboard/teleplatforms/D4E4S16P8/bootorder: https://review.coreboot.org/c/blobs/+/57196/comment/5bfbce2a_e89ea1fd PS5, Line 1: /pci@i0cf8/usb@15/usb-*@1 : /pci@i0cf8/usb@15/usb-*@2 : /pci@i0cf8/usb@15/usb-*@3 : /pci@i0cf8/usb@15/usb-*@4 : /pci@i0cf8/*@13/drive@1/disk@0 : /pci@i0cf8/*@13/drive@3/disk@0 > Not really a blob but a text file. […] +1, I agree this can be in the mainboard directory -- To view, visit https://review.coreboot.org/c/blobs/+/57196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I71de576aa283fe6738138ad023d70c282045f5cc Gerrit-Change-Number: 57196 Gerrit-PatchSet: 5 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Expose apic devices
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/59313/comment/553b628e_80d970dc PS1, Line 394: __apic_0000_0 > > This doesn't look like a config aka chip_info […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Expose apic devices
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/59313/comment/2f73649a_0ae88d52 PS2, Line 391: config_of_lapic Just to be explicit, I'd use `config_of_lapic_0` -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:36:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/hardwaremain: Run timers more frequently
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58955 ) Change subject: lib/hardwaremain: Run timers more frequently ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58955/comment/571e0ddf_fc6e579e PS2, Line 14: see SPI transactions progress faster > Because we poll the SPI DMA controller more often to see if it's completed the transaction. […] Basically, `bs_run_timers(0)` calls `timers_run()` once, which checks if the timer queue's first element (the one with the earliest deadline) has expired. If so, its callback is executed. This change calls `bs_run_timers(0)` in more places, so that expired elements in the timer queue can be processed sooner and more often. This would only speed up the boot process if the delays before expired timer queue elements get processed are part of the critical path (the longest sequence of dependent tasks that need to be completed). -- To view, visit https://review.coreboot.org/c/coreboot/+/58955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Gerrit-Change-Number: 58955 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:35:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59489 to review the following change. Change subject: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree ...................................................................... soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree This removes the need to expose a FSP upd to the devicetree directly. Change-Id: If11266e93d1d11695edf21b6cd60e5d8add1fde8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 16 files changed, 12 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59489/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 1d7dca6..0f3e53d 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -72,9 +72,7 @@ .backlight_off_delay_ms = 1, }" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 105eddb..32bb1b7 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -46,7 +46,6 @@ .tdp_pl2_override = 51, .psys_pmax = 140, }" - register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" register "SlowSlewRateForGt" = "2" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a84eabd..0256525 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -35,7 +35,6 @@ .tdp_pl1_override = 15, .tdp_pl2_override = 64, }" - register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C @@ -202,7 +201,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 04.0 on end # SA Thermal device device pci 05.0 off end # SA IPU device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0bbc25f..95e60eb 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -35,7 +35,6 @@ .tdp_pl2_override = 51, .psys_pmax = 140, }" - register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" register "SlowSlewRateForGt" = "2" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index a447240..c04755b 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -43,7 +43,6 @@ .tdp_pl2_override = 51, .psys_pmax = 136, }" - register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb index c8d6816..cb06235 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb @@ -78,9 +78,7 @@ .backlight_off_delay_ms = 1, }" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on # USB xHCI diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 08d152c..3d136e1 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -58,9 +58,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on # USB xHCI diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 4f16bbd..07d2e72 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -60,9 +60,7 @@ register "PcieClkSrcClkReq[8]" = "8" end device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index da86024..14ba13e 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -63,9 +63,7 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index c02a6ec..9fbd7e3 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -61,9 +61,7 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 00d3708..c2b82af 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -62,9 +62,7 @@ subsystemid 0x1558 0x1401 inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index bb75616..cbe91a3 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -69,9 +69,7 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 85b5d26..c9071a1 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -66,9 +66,7 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 3e28a16..3704454 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -63,9 +63,7 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_STATIC_DISPLAYS(0)" end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 774b526..e36e273 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -220,8 +220,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - uint8_t Device4Enable; - /* CPU PL2/4 Config * Performance: Maximum PLs for maximum performance. * Baseline: Baseline PLs for balanced performance at lower power. diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f22e39d..631b64a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -583,7 +583,7 @@ #if !CONFIG(HECI_DISABLE_USING_SMM) params->Heci1Disabled = !is_devfn_enabled(PCH_DEVFN_CSE); #endif - params->Device4Enable = config->Device4Enable; + params->Device4Enable = is_devfn_enabled(SA_DEVFN_DSP); /* Teton Glacier hybrid storage support */ params->TetonGlacierMode = config->TetonGlacierMode; -- To view, visit https://review.coreboot.org/c/coreboot/+/59489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11266e93d1d11695edf21b6cd60e5d8add1fde8 Gerrit-Change-Number: 59489 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in blobs[master]: mb/teleplatforms/D4E4S168: Add blobs
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Дмитрий Понаморев, Paul Menzel, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/57196 ) Change subject: mb/teleplatforms/D4E4S168: Add blobs ...................................................................... Patch Set 5: (1 comment) File mainboard/teleplatforms/D4E4S16P8/bootorder: https://review.coreboot.org/c/blobs/+/57196/comment/e2bddb32_e8ea899b PS5, Line 1: /pci@i0cf8/usb@15/usb-*@1 : /pci@i0cf8/usb@15/usb-*@2 : /pci@i0cf8/usb@15/usb-*@3 : /pci@i0cf8/usb@15/usb-*@4 : /pci@i0cf8/*@13/drive@1/disk@0 : /pci@i0cf8/*@13/drive@3/disk@0 Not really a blob but a text file. You might want to just put that in the mainboard dir? -- To view, visit https://review.coreboot.org/c/blobs/+/57196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I71de576aa283fe6738138ad023d70c282045f5cc Gerrit-Change-Number: 57196 Gerrit-PatchSet: 5 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:16:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in blobs[master]: mb/teleplatforms/D4E4S168: Add blobs
by Arthur Heymans (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Дмитрий Понаморев, Paul Menzel, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/57196 ) Change subject: mb/teleplatforms/D4E4S168: Add blobs ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Are those binaries redistributable? -- To view, visit https://review.coreboot.org/c/blobs/+/57196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I71de576aa283fe6738138ad023d70c282045f5cc Gerrit-Change-Number: 57196 Gerrit-PatchSet: 5 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:14:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Add PSE TSN support
by Lean Sheng Tan (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56633 ) Change subject: soc/intel/elkhartlake: Add PSE TSN support ...................................................................... Patch Set 25: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56633/comment/4146d61f_b53ca8bc PS1, Line 8: > IIRC, TSN = Time Sensitive Networking. […] Yes, i just removed WIP. Updated. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56633/comment/689dfbf6_e5409f18 PS19, Line 143: params->PchPseGbeEnable[0] = is_devfn_enabled(PCH_DEVFN_GBE) ? : Host_Owned : config->PseGbeOwn; > This statement is identical to the statement above. […] Yeah it was WIP. Updated now, please take a look :) -- To view, visit https://review.coreboot.org/c/coreboot/+/56633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Gerrit-Change-Number: 56633 Gerrit-PatchSet: 25 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 11:14:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Add PSE TSN support
by Lean Sheng Tan (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56633 to look at the new patch set (#25). Change subject: soc/intel/elkhartlake: Add PSE TSN support ...................................................................... soc/intel/elkhartlake: Add PSE TSN support Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a --- M src/soc/intel/elkhartlake/acpi/tsn_glan.asl M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 116 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/56633/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/56633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Gerrit-Change-Number: 56633 Gerrit-PatchSet: 25 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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