coreboot-gerrit November 2021

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Change in coreboot[master]: src/security/tpm: Add TPM2_NV_Increment command
by Andrey Pronin (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Christian Walter, Julius Werner, Karthik Ramasubramanian. Andrey Pronin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59475 ) Change subject: src/security/tpm: Add TPM2_NV_Increment command ...................................................................... Patch Set 1: (2 comments) File src/security/tpm/tss/tcg-2.0/tss.c: https://review.coreboot.org/c/coreboot/+/59475/comment/ce7f7ab8_beb29162 PS1, Line 360: TPM_E_INC_FAILURE nit: can we just reuse TPM_E_WRITE_FAILURE instead of adding a new code? also, we may want to do different error handling based on what's wrong (index doesn't exist vs wrong auth, for example). if that's the case it makes sense to switch on the actual response code as tlcl_read does. and if (!response) return TPM_E_IOERROR. but of we don't care about the return code and treat it as a success flag in all callers, reusing TPM_E_WRITE_FAILURE should be enough. File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/c/coreboot/+/59475/comment/e2cabf9f_394536f9 PS1, Line 203: TPM_RH_PLATFORM nit: why not use command_body->nvIndex and rely on AUTHWRITE(authValue = NULL) here? -- To view, visit https://review.coreboot.org/c/coreboot/+/59475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86f8db5ad0926e9d1fd34a9ca5d55d884f76423 Gerrit-Change-Number: 59475 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 20:16:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Setup secure counter space in TPM NVRAM
by build bot (Jenkins) (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Setup secure counter space in TPM NVRAM ...................................................................... Patch Set 1: (1 comment) File src/security/vboot/secdata_tpm.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133722): https://review.coreboot.org/c/coreboot/+/59476/comment/1b13ed88_e65e724b PS1, Line 157: .TPMA_NV_WRITE_STCLEAR =1, spaces required around that '=' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:57:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable secure counters
by Karthik Ramasubramanian (Code Review) 18 Nov '21

18 Nov '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59477 ) Change subject: mb/google/guybrush: Enable secure counters ...................................................................... mb/google/guybrush: Enable secure counters Guybrush uses secure counters to protect against High Definition (HD) protected content rollback. These secure counters are hosted in TPM NVRAM. Enable secure counters so that they are defined in PSP verstage. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM. Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/59477/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c97c06d..c05b913 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -54,6 +54,9 @@ bool "Enable PSP_verstage" default y if VBOOT +config VBOOT_STARTS_BEFORE_BOOTBLOCK + select VBOOT_DEFINE_SECURE_COUNTERS + config VBOOT_STARTS_IN_BOOTBLOCK bool default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/59477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Gerrit-Change-Number: 59477 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security/vboot: Setup secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Setup secure counter space in TPM NVRAM ...................................................................... src/security/vboot: Setup secure counter space in TPM NVRAM High Definition (HD) protected content playback requires secure counters that are updated at regular interval while the protected content is playing. To support similar use-cases, define space for secure counters in TPM NVRAM and initialize them. These counters are defined once during the factory initialization stage. Also add a config item to enable these secure counters only on the mainboard where they are required/used. BUG=b:205261728 TEST=Build and boot to OS in guybrush. Ensure that the secure counters are defined and initialized successfully in TPM NVRAM space. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100f return code 28b tlcl_define_space: response is 0 tlcl_nv_increment: response is 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1010 return code 28b tlcl_define_space: response is 0 tlcl_nv_increment: response is 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1011 return code 28b tlcl_define_space: response is 0 tlcl_nv_increment: response is 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1012 return code 28b tlcl_define_space: response is 0 tlcl_nv_increment: response is 0 On subsequent boot cycles, the read ensure that the space already exists and the secure counter is not re-defined. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100f return code 0 setup_secure_counter_spaces():373: Secure counter 0000100f value 72057594037927936 rv 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1010 return code 0 setup_secure_counter_spaces():373: Secure counter 00001010 value 72057594037927936 rv 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1011 return code 0 setup_secure_counter_spaces():373: Secure counter 00001011 value 72057594037927936 rv 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1012 return code 0 setup_secure_counter_spaces():373: Secure counter 00001012 value 72057594037927936 rv 0 Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c A src/security/vboot/secure_counter.h 3 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 7cbeea3..d5e7554 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -282,6 +282,14 @@ Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate SHA hash calculation in vboot. +config VBOOT_DEFINE_SECURE_COUNTERS + bool "Define Secure Counters in Verstage" + default n + depends on TPM2 + help + Setup Secure Counters in TPM NVRAM including defining space and + initializing them. + menu "GBB configuration" config GBB_HWID diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0bc4f839..ecc3f05 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -6,6 +6,7 @@ */ #include <security/vboot/antirollback.h> +#include <security/vboot/secure_counter.h> #include <security/vboot/tpm_common.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> @@ -147,6 +148,17 @@ .TPMA_NV_POLICY_DELETE = 1, }; +static const TPMA_NV secure_counter_attr = { + .TPMA_NV_COUNTER = 1, + .TPMA_NV_ORDERLY = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_AUTHWRITE = 1, + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_WRITE_STCLEAR =1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PPWRITE = 1, +}; + /* * This policy digest was obtained using TPM2_PolicyOR on 3 digests * corresponding to a sequence of @@ -330,6 +342,42 @@ return rv; } +static uint32_t setup_secure_counter(uint32_t index, const TPMA_NV nv_attributes) +{ + uint32_t rv; + + rv = define_space(SECURE_COUNTER_NAME, index, SECURE_COUNTER_SIZE, nv_attributes, + NULL, 0); + if (rv != TPM_SUCCESS) + return rv; + + /* Increment the secure counter so that it has a valid initial value on read. */ + return tlcl_nv_increment(index); +} + +static uint32_t setup_secure_counter_spaces(void) +{ + uint32_t index; + uint32_t rv; + uint64_t value; + + if (!CONFIG(VBOOT_DEFINE_SECURE_COUNTERS)) + return TPM_SUCCESS; + + for (index = SECURE_COUNTER1_NV_INDEX; index < SECURE_COUNTER_END_NV_INDEX; index++) { + rv = tlcl_read(index, &value, SECURE_COUNTER_SIZE); + if (rv != TPM_E_BADINDEX) { + VBDEBUG("Secure counter %08x value %llu rv %d\n", index, value, rv); + continue; + } + + rv = setup_secure_counter(index, secure_counter_attr); + if (rv != TPM_SUCCESS) + return rv; + } + return TPM_SUCCESS; +} + static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { RETURN_ON_FAILURE(tlcl_force_clear()); @@ -365,6 +413,8 @@ RETURN_ON_FAILURE(setup_firmware_space(ctx)); + RETURN_ON_FAILURE(setup_secure_counter_spaces()); + return TPM_SUCCESS; } diff --git a/src/security/vboot/secure_counter.h b/src/security/vboot/secure_counter.h new file mode 100644 index 0000000..d676ed3 --- /dev/null +++ b/src/security/vboot/secure_counter.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SECURE_COUNTER_H__ +#define __SECURE_COUNTER_H__ + +#define SECURE_COUNTER_NAME "Secure Counter" +#define SECURE_COUNTER_SIZE 8 + +/* TPM NVRAM location indices. */ +enum secure_counter_nv_index { + SECURE_COUNTER1_NV_INDEX = 0x100f, + SECURE_COUNTER2_NV_INDEX, /* 0x1010 */ + SECURE_COUNTER3_NV_INDEX, /* 0x1011 */ + SECURE_COUNTER4_NV_INDEX, /* 0x1012 */ + SECURE_COUNTER_END_NV_INDEX, +}; + +#endif /* __SECURE_COUNTER_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security/tpm: Add TPM2_NV_Increment command
by Karthik Ramasubramanian (Code Review) 18 Nov '21

18 Nov '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59475 ) Change subject: src/security/tpm: Add TPM2_NV_Increment command ...................................................................... src/security/tpm: Add TPM2_NV_Increment command This command is used to increment the value in an NV Index that has the TPM_NT_COUNTER attribute. The data value of the NV Index is incremented by one. Introduce the command code, structure and marshaling function. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that when the command is applied on an appropriate NV Index, it is incremented successfully. Change-Id: Ic86f8db5ad0926e9d1fd34a9ca5d55d884f76423 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss_errors.h 5 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/59475/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index f68e1f4..be1db1b 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -200,4 +200,9 @@ */ uint32_t tlcl_get_permissions(uint32_t index, uint32_t *permissions); +/** + * Increment the NVRAM Secure Counter at index. + */ +uint32_t tlcl_nv_increment(uint32_t index); + #endif /* TSS_H_ */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 8c9d12f..1415805 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -343,6 +343,25 @@ return TPM_SUCCESS; } +uint32_t tlcl_nv_increment(uint32_t index) +{ + struct tpm2_response *response; + /* TPM Will reject attempts to increment at non-defined index. */ + struct tpm2_nv_increment_cmd nv_inc = { + .nvIndex = HR_NV_INDEX + index, + }; + + response = tpm_process_command(TPM2_NV_Increment, &nv_inc); + + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response || response->hdr.tpm_code) + return TPM_E_INC_FAILURE; + + return TPM_SUCCESS; +} + uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, const TPMA_NV nv_attributes, const uint8_t *nv_policy, size_t nv_policy_size) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 83fff5f..9145e75 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -197,6 +197,14 @@ return rc; } +static int marshal_nv_increment(struct obuf *ob, + const struct tpm2_nv_increment_cmd *command_body) +{ + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + + return marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); +} + static int marshal_nv_setbits(struct obuf *ob, const struct tpm2_nv_setbits_cmd *command_body) { @@ -398,6 +406,10 @@ rc |= marshal_nv_define_space(ob, tpm_command_body); break; + case TPM2_NV_Increment: + rc |= marshal_nv_increment(ob, tpm_command_body); + break; + case TPM2_NV_SetBits: rc |= marshal_nv_setbits(ob, tpm_command_body); break; @@ -634,6 +646,7 @@ case TPM2_Clear: case TPM2_ClearControl: case TPM2_NV_DefineSpace: + case TPM2_NV_Increment: case TPM2_NV_SetBits: case TPM2_NV_Write: case TPM2_NV_WriteLock: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index c0e354d..53bd793 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -81,6 +81,7 @@ #define TPM2_Clear ((TPM_CC)0x00000126) #define TPM2_ClearControl ((TPM_CC)0x00000127) #define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) +#define TPM2_NV_Increment ((TPM_CC)0x00000134) #define TPM2_NV_SetBits ((TPM_CC)0x00000135) #define TPM2_NV_Write ((TPM_CC)0x00000137) #define TPM2_NV_WriteLock ((TPM_CC)0x00000138) @@ -430,4 +431,8 @@ TPMI_YES_NO state; }; +struct tpm2_nv_increment_cmd { + TPMI_RH_NV_INDEX nvIndex; +}; + #endif // TCG2_TSS_STRUCTURES_H_ diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index 49a7405..82fc099 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -42,5 +42,6 @@ #define TPM_E_HASH_ERROR ((uint32_t)0x0000500d) #define TPM_E_NO_SUCH_COMMAND ((uint32_t)0x0000500e) #define TPM_E_RANGE ((uint32_t)0x0000500f) +#define TPM_E_INC_FAILURE ((uint32_t)0x00005010) #endif /* TSS_ERRORS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86f8db5ad0926e9d1fd34a9ca5d55d884f76423 Gerrit-Change-Number: 59475 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Nick Vaccaro, Julius Werner, Kyösti Mälkki, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > I haven't fully root-caused it yet, but this is breaking crossystem, the userspace tool we use to re […] just assumptions about the paths involved, snippets from dmesg: ``` [ 0.197888] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW], AE_NOT_FOUND (20200925/dswload2-163) [ 0.197895] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20200925/psobject-220) [ 0.197928] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.CNVS], AE_NOT_FOUND (20200925/dsfield-501) [ 0.204896] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 0.204900] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.204905] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 0.814701] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 0.814705] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.814710] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 0.839973] ACPI Error: No object attached to node [VBT3] 0000000023f4c77c (20200925/exresnte-93) [ 0.839973] chromeos_acpi: ignoring type 20 (CHSW) [ 0.839973] ACPI Error: No object attached to node [VBT5] 000000006f7b1d76 (20200925/exresnte-93) [ 0.839975] ACPI Error: Aborting method \CRHW.FWID due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.839980] chromeos_acpi: failed to retrieve FWID (12322) [ 0.839984] ACPI Error: No object attached to node [VBT4] 0000000023f2c7ec (20200925/exresnte-93) [ 0.839986] ACPI Error: Aborting method \CRHW.HWID due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.839990] chromeos_acpi: failed to retrieve HWID (12322) [ 0.839993] ACPI Error: No object attached to node [VBT6] 000000003e5858e1 (20200925/exresnte-93) [ 0.839995] ACPI Error: Aborting method \CRHW.FRID due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.839998] chromeos_acpi: failed to retrieve FRID (12322) [ 0.840003] ACPI Error: No object attached to node [VBT0] 00000000b7047eab (20200925/exresnte-93) [ 0.840005] ACPI Error: No object attached to node [VBT1] 00000000a81b3c2f (20200925/exresnte-93) [ 0.840007] ACPI Error: No object attached to node [VBT2] 000000009407f2cb (20200925/exresnte-93) [ 0.840009] ACPI Error: No object attached to node [VBT7] 0000000033c19e4f (20200925/exresnte-93) [ 0.840011] ACPI Error: No object attached to node [VBT8] 0000000050322925 (20200925/exresnte-93) [ 0.840019] chromeos_acpi: ignoring type 20 (BINF) [ 0.840020] chromeos_acpi: ignoring type 20 (BINF) [ 0.840021] chromeos_acpi: ignoring type 20 (BINF) [ 0.840021] chromeos_acpi: ignoring type 20 (BINF) [ 0.840022] chromeos_acpi: ignoring type 20 (BINF) [ 0.840054] ACPI Error: No object attached to node [CHVD] 00000000ab2442d7 (20200925/exresnte-93) [ 0.840056] ACPI Error: Aborting method \CRHW.VDAT due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 0.840060] chromeos_acpi: failed to retrieve VDAT (12322) [ 0.840063] ACPI Error: No object attached to node [VBT9] 0000000070871628 (20200925/exresnte-93) [ 0.840068] chromeos_acpi: ignoring type 20 (FMAP) [ 0.840072] ACPI Error: No object attached to node [MEHH] 0000000069c0ea6b (20200925/exresnte-93) [ 0.840076] chromeos_acpi: ignoring type 20 (MECK) [ 2.344636] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.344641] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.344647] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 2.347684] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.347687] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.347692] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 2.350267] i2c i2c-14: failed to add I2C device GDIX0000:00 from ACPI [ 2.350452] i2c i2c-14: failed to add I2C device SIS9815:00 from ACPI [ 2.350862] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.350865] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.350870] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 2.353381] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.353384] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.353388] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 2.467374] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.467380] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.467386] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) [ 2.470709] ACPI Error: No object attached to node [RMOB] 0000000081e5914b (20200925/exresnte-93) [ 2.470713] ACPI Error: Aborting method \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/psparse-531) [ 2.470718] ACPI Error: Method execution failed \_SB.RMOP._CRS due to previous error (AE_AML_UNINITIALIZED_NODE) (20200925/uteval-69) ``` looks like it breaks chromeos-ramoops as well -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:51:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
by Subrata Banik (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59271 ) Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Bray can boot and reboot without issues. Thanks Eric for checking -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:41:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Tim Wawrzynczak (Code Review) 18 Nov '21

18 Nov '21

1 0

Change in coreboot[master]: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value()
by Subrata Banik (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59390 ) Change subject: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value() ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59390/comment/96b756b8_d693d0b7 PS1, Line 7: variable > parameter Ack https://review.coreboot.org/c/coreboot/+/59390/comment/87b4b1cd_095e9075 PS1, Line 9: being > nit: move to next line Ack https://review.coreboot.org/c/coreboot/+/59390/comment/7c18c6c2_bcbcee2e PS1, Line 10: replaced > present tense (no final `d`): `replace` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 19:40:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value()
by Subrata Banik (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59390 to look at the new patch set (#2). Change subject: soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value() ...................................................................... soc/intel/../thermal: Drop unused `dev` parameter in pch_get_ltt_value() `struct device *dev` as part of the pch_get_ltt_value() argument is being used hence, replace with `void`. BUG=b:193774296 Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59390/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021