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Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 )
Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59392/comment/4820c3ea_4fdb1849
PS2, Line 9: commit:3fd39467b Fix S0ix regression
> what fixes the S0ix regression now? just the FIVR change?
Clksrc 3 disable is needed for S0ix regression. But since we can't push it upstream, the alternative is to disable it via FIT.
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Hello build bot (Jenkins), Jeremy Soller,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/system76/*: Enable dGPU temp/fan reporting
......................................................................
mb/system76/*: Enable dGPU temp/fan reporting
Select the EC option on boards with dGPUs to report GPU temperature and
fan data.
Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.
system76_acpi-acpi-0
Adapter: ACPI interface
CPU fan: 1985 RPM
GPU fan: 2348 RPM
CPU temp: +68.0°C
GPU temp: +0.0°C
Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/addw1/Kconfig
M src/mainboard/system76/bonw14/Kconfig
M src/mainboard/system76/galp5/Kconfig
M src/mainboard/system76/gaze15/Kconfig
M src/mainboard/system76/gaze16/Kconfig
M src/mainboard/system76/oryp5/Kconfig
M src/mainboard/system76/oryp6/Kconfig
M src/mainboard/system76/oryp8/Kconfig
8 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/59123/3
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Change subject: mb/system76/*: Enable dGPU temp reporting
......................................................................
Set Ready For Review
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57881 )
Change subject: ec/system76/ec: acpi: Add dGPU thermal reporting
......................................................................
Set Ready For Review
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Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57861 )
Change subject: Documentation/RFC: Generalize PCI support in coreboot
......................................................................
Patch Set 12:
(1 comment)
File Documentation/RFC/pci_config_access.md:
https://review.coreboot.org/c/coreboot/+/57861/comment/5c809bd3_59dc916b
PS12, Line 125: ### Specifying MMIO support for PCI devices that don't support ECAM
:
: We’ll need to be able to distinguish between a platform using the ECAM access
: method and any other MMIO access mechanism. For devices that support ECAM, they
: would have to select the `ECAM_MMONCF_SUPPORT` config. For devices that don't
: support ECAM and would still need MMIO support, they would need to explictly
: select the `NO_ECAM_MMCONF_SUPPORT` config and include the `pci_mmio_cfg.h'
: header file in their platform-specific source.
Hi Shelley,
This will be a little confused in Mediatek platform, we can support ECAM access method, but it need to rely on the MMIO space to do so.
We will have two scenarios to access the config space:
1. No ECAM support, we will use pci_map_bus() to map the internal register to access the config space of devices, and the MMIO space is only used to access the BARs;
2. ECAM support, we need to remain some MMIO space for ECAM access method(1MB for each bus for 32 devices with 8 functions in maximum), and the other spaces will be used to access the BARs.
The reality problem is that we don't have large MMIO space like x86 does, so we will prefer to use the method with no ECAM support, but the function of get_pci_mmio_cfgbase() seems a little confused in this scenario.
Thanks.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Andrey Pronin, Marshall Dawson, Kangheui Won, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#18).
Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c
needs to be ready before attempting to restore tpm.
BUG=b:200578885,b:197965075
TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay.
BRANCH=None
Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/soc/amd/common/psp_verstage/Kconfig
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
3 files changed, 62 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/18
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Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59411 )
Change subject: mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
......................................................................
mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.
BUG=b:206867635
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301
---
M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59411/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h
index b346530..3c7fde5 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h
+++ b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h
@@ -43,10 +43,10 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
(MAINBOARD_EC_S3_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
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