coreboot-gerrit October 2021

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Change in coreboot[master]: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36710 ) Change subject: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant ...................................................................... mb/*/*{haswell}: Link gpio.c and add a const global for lp variant This is similar to how sb/common/intel handles it. The advantage is that the gpio configuration does not need to be passed on that much. Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/beltino/romstage.c R src/mainboard/google/beltino/variants/mccloud/gpio.c R src/mainboard/google/beltino/variants/monroe/gpio.c R src/mainboard/google/beltino/variants/panther/gpio.c R src/mainboard/google/beltino/variants/tricky/gpio.c R src/mainboard/google/beltino/variants/zako/gpio.c M src/mainboard/google/slippy/Makefile.inc R src/mainboard/google/slippy/variants/falco/gpio.c M src/mainboard/google/slippy/variants/falco/romstage.c R src/mainboard/google/slippy/variants/leon/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c R src/mainboard/google/slippy/variants/peppy/gpio.c M src/mainboard/google/slippy/variants/peppy/romstage.c R src/mainboard/google/slippy/variants/wolf/gpio.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/pch.h 26 files changed, 25 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36710/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..7459011 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -134,7 +134,6 @@ struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *); }; diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 34fd7b0..e28ebf4 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,7 +33,7 @@ enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->rcba_config); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3deae75..dd4043e 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -92,7 +92,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e1bebc1..7535350 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f206664..5c91bec 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -24,7 +24,6 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include <variant/gpio.h> #include "onboard.h" const struct rcba_config_instruction rcba_config[] = { @@ -128,7 +127,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/mccloud/gpio.c index 116eeeb..47979d2b 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MCCLOUD_GPIO_H -#define MCCLOUD_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/monroe/gpio.c index 8423e1e..22ef848 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MONROE_GPIO_H -#define MONROE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/panther/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/panther/gpio.c index e48f0b4..08142a8 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef PANTHER_GPIO_H -#define PANTHER_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/tricky/gpio.c index 6980ebb..df5d333 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef TRICKY_GPIO_H -#define TRICKY_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/zako/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/zako/gpio.c index dffefd6..e533bf0 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef ZAKO_GPIO_H -#define ZAKO_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 921f9e7..f80dcab 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/romstage.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/falco/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/falco/gpio.c index c35b81e..3fdc032 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 1903588..656bf70 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -165,7 +164,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/leon/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/leon/gpio.c index 7527ff2..5ea78f9 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef LEON_GPIO_H -#define LEON_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 3ef8eec..2eeb86d 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -160,7 +159,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/peppy/gpio.c index 8eb3da9..00e6a54 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef PEPPY_GPIO_H -#define PEPPY_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 71eafc2..048a154 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" @@ -177,7 +176,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/wolf/gpio.c index 5c72f73..1dbd5ff 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef WOLF_GPIO_H -#define WOLF_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7fcf085..cc67c93 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -164,7 +163,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index e34704d..91a7963 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,4 +17,6 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +romstage-y += gpio.c + smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index f2be9e3..3a33f09 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1a10931..3d03ab3 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -134,7 +134,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = NULL, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 552ebd2..46ec7b2 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -90,7 +90,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 25ffdc4..b49d3cf 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -99,17 +99,16 @@ { } -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const struct rcba_config_instruction *rcba_config) { int wake_from_s3; pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(mainboard_gpio_map); #endif pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 8436243..0464226 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -160,6 +160,8 @@ u8 pirq; } __packed; +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; + /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d83dd17..8802be1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -181,8 +181,7 @@ #endif void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Gerrit-Change-Number: 36710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: adding new mainboard (no official website as it is a noname board but...
by Skoll RC (Code Review) 07 Aug '23

07 Aug '23

Skoll RC has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40813 ) Change subject: adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details ...................................................................... adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details Signed-off-by: Robin CASSET <amisbievre(a)posteo.net> Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c --- A src/mainboard/ongy/Kconfig A src/mainboard/ongy/Kconfig.name A src/mainboard/ongy/h61m-s1/Kconfig A src/mainboard/ongy/h61m-s1/Kconfig.name A src/mainboard/ongy/h61m-s1/Makefile.inc A src/mainboard/ongy/h61m-s1/acpi/ec.asl A src/mainboard/ongy/h61m-s1/acpi/platform.asl A src/mainboard/ongy/h61m-s1/acpi/superio.asl A src/mainboard/ongy/h61m-s1/acpi_tables.c A src/mainboard/ongy/h61m-s1/board_info.txt A src/mainboard/ongy/h61m-s1/devicetree.cb A src/mainboard/ongy/h61m-s1/dsdt.asl A src/mainboard/ongy/h61m-s1/early_init.c A src/mainboard/ongy/h61m-s1/gma-mainboard.ads A src/mainboard/ongy/h61m-s1/gpio.c A src/mainboard/ongy/h61m-s1/hda_verb.c A src/mainboard/ongy/h61m-s1/mainboard.c 17 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/40813/1 diff --git a/src/mainboard/ongy/Kconfig b/src/mainboard/ongy/Kconfig new file mode 100644 index 0000000..30ea9f3 --- /dev/null +++ b/src/mainboard/ongy/Kconfig @@ -0,0 +1,14 @@ +if VENDOR_ONGY +choice + prompt "Mainboard model" + +source "src/mainboard/ongy/*/Kconfig.name" + +endchoice + +source "src/mainboard/ongy/*/Kconfig" + +config MAINBOARD_VENDOR + default "H61M-S1" + +endif # VENDOR_ONGY diff --git a/src/mainboard/ongy/Kconfig.name b/src/mainboard/ongy/Kconfig.name new file mode 100644 index 0000000..d0e84b5 --- /dev/null +++ b/src/mainboard/ongy/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ONGY + bool "ongy" diff --git a/src/mainboard/ongy/h61m-s1/Kconfig b/src/mainboard/ongy/h61m-s1/Kconfig new file mode 100644 index 0000000..65bda16 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_H61M_S1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default ongy/h61m-s1 + +config MAINBOARD_PART_NUMBER + string + default "h61m-s1" + +config VGA_BIOS_FILE + string + default "pci8086,0112.rom" + +config VGA_BIOS_ID + string + default "8086,0112" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/ongy/h61m-s1/Kconfig.name b/src/mainboard/ongy/h61m-s1/Kconfig.name new file mode 100644 index 0000000..36eed8c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_H61M_S1 + bool "h61m-s1" diff --git a/src/mainboard/ongy/h61m-s1/Makefile.inc b/src/mainboard/ongy/h61m-s1/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/ongy/h61m-s1/acpi/ec.asl b/src/mainboard/ongy/h61m-s1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/ec.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi/platform.asl b/src/mainboard/ongy/h61m-s1/acpi/platform.asl new file mode 100644 index 0000000..ac9ff88 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* The _PTS method (Prepare To Sleep) is called before the OS is +* entering a sleep state. The sleep state number is passed in Arg0 +*/ + +Method(_PTS,1) +{ +} + +/*The _WAK method is called on system wakeup*/ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ongy/h61m-s1/acpi/superio.asl b/src/mainboard/ongy/h61m-s1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/superio.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi_tables.c b/src/mainboard/ongy/h61m-s1/acpi_tables.c new file mode 100644 index 0000000..3319c25 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi_tables.c @@ -0,0 +1,22 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/ongy/h61m-s1/board_info.txt b/src/mainboard/ongy/h61m-s1/board_info.txt new file mode 100644 index 0000000..0fc073c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: none +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/ongy/h61m-s1/devicetree.cb b/src/mainboard/ongy/h61m-s1/devicetree.cb new file mode 100644 index 0000000..38b740f --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/devicetree.cb @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x8086 0x1c1a + end + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c5c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 off end # SATA Controller 2 + + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x8086 0x0100 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/ongy/h61m-s1/dsdt.asl b/src/mainboard/ongy/h61m-s1/dsdt.asl new file mode 100644 index 0000000..8c67659 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/dsdt.asl @@ -0,0 +1,43 @@ +/* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/ongy/h61m-s1/early_init.c b/src/mainboard/ongy/h61m-s1/early_init.c new file mode 100644 index 0000000..6cb36f1 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/ongy/h61m-s1/gma-mainboard.ads b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads new file mode 100644 index 0000000..e2c84c6 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-only +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/ongy/h61m-s1/gpio.c b/src/mainboard/ongy/h61m-s1/gpio.c new file mode 100644 index 0000000..22f4838 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/ongy/h61m-s1/hda_verb.c b/src/mainboard/ongy/h61m-s1/hda_verb.c new file mode 100644 index 0000000..09748c0 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/hda_verb.c @@ -0,0 +1,43 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek*/ + 0x10ec0000, /* Subsystem ID*/ + 12, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_PIN_CFG(2, 0x12, 0x40130000), + AZALIA_PIN_CFG(2, 0x14, 0x01014010), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19040), + AZALIA_PIN_CFG(2, 0x19, 0x02a19050), + AZALIA_PIN_CFG(2, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4044c601), + AZALIA_PIN_CFG(2, 0x1e, 0x01441130), + + 0x80862805, /* Codec Vendor / Device ID: Intel*/ + 0x80860101, /* Subsystem ID*/ + 4, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/ongy/h61m-s1/mainboard.c b/src/mainboard/ongy/h61m-s1/mainboard.c new file mode 100644 index 0000000..3f9c24e --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c Gerrit-Change-Number: 40813 Gerrit-PatchSet: 1 Gerrit-Owner: Skoll RC Gerrit-MessageType: newchange

8 115

Change in coreboot[master]: Documentation: Add cache as ram documentation
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36126 ) Change subject: Documentation: Add cache as ram documentation ...................................................................... Documentation: Add cache as ram documentation This add documentation around coreboot's history of CAR usage. The history is reconstructed from articles and git/svn history, but should provide a good overview of the challenges and solutions coreboot came up with to deal with early code execution on X86 platforms. The technical details about CAr will come in follow-up patch and are marked as TODO for now. Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/cpu/index.md A Documentation/cpu/x86/car.md M Documentation/index.md 3 files changed, 171 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36126/1 diff --git a/Documentation/cpu/index.md b/Documentation/cpu/index.md new file mode 100644 index 0000000..d9f063f --- /dev/null +++ b/Documentation/cpu/index.md @@ -0,0 +1,5 @@ +# CPU-specific documentation + +This section contains documentation about coreboot on specific CPU. + +* [A gentle introduction to Cache-as-Ram on X86](x86/car.md) diff --git a/Documentation/cpu/x86/car.md b/Documentation/cpu/x86/car.md new file mode 100644 index 0000000..3d2983e --- /dev/null +++ b/Documentation/cpu/x86/car.md @@ -0,0 +1,165 @@ +# A gentle introduction to Cache-as-Ram on X86 + +This explains a bit of history on CAR in coreboot, how it works +and then finally give a more in depth overview at the steps of +how it is set up on Intel CPUs. + +## Glossary + +- Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution + environment. +- XIP: Execute in place on a memory mapped medium +- SRAM: Static Random Access Memory, here: memory mapped memory + that needs no initialization. +- ROMCC: A C compiler using only the CPU registers. + +## Cache-as-Ram, the basics + +When an X86 platforms boot, it starts in a pretty bare environment. +The first instruction is fetched from the top of the boot medium, +which on most x86 platforms is memory mapped below 4G (in 32bit +protected mode). Not only do they start in 16bit 'real' mode, +most of the hardware starts uninitialized. This includes the dram +controller. Another thing about X86 platforms is that they generally +don't feature SRAM, static RAM. SRAM for this purpose of this text is +a small region of ram that is available without any initialization. +Without RAM this leaves the system with just CPU registers and a +memory mapped boot medium of which code can be executed in place (XIP) +to initialize the hardware. + +For simple dram controllers that environment is just fine and +initializing the dram controller in assembly code without using a +stack is very doable. Modern systems however require complex +initialization procedures and writing that in assembly would be either +too hard or simply impossible. To overcome this limitation a technique +called Cache-as-Ram exists. It allows to use the CPU's Cache-as-Ram. +This in turn makes it possible to write the early initialization code +in a higher level programming language compiled by a regular compiler, +e.g. GCC. Typically only the stack is placed in Cache-as-Ram and the +code is still executed in place, but copying code in the cache as ram +and executing from there is also possible. + +For coreboot this means that with only a very small amount of assembly +code to set up CAR, all the other code can written in C, which +compared to writing assembly tremendously increases development speed +and is much less error prone. + +## A bit of history on Cache-as-Ram in coreboot + +### Linux as a BIOS? The invention of romstage + +When LinuxBIOS, later coreboot, started out, the first naive attempt +to run the Linux kernel instead of the legacy BIOS interface, was to +jump straight to loading the kernel. This did not work at all, since +dram was not working at that point. LinuxBIOS v1 therefore +initialized the memory in assembly before it was able to load the +kernel. This executed in place and would later become romstage. It +turned that Linux needed other devices, like enumerated and have it's +resources allocated, so yet another stage, ramstage, was called into +life, but that's another story. + +### coreboot v2: romcc + +In 2003 AMD's K8 CPU's came out. Those CPU's featured an on die memory +controller and also a new point to point BUS for CPU <-> CPU and +CPU <-> IO controller (northbridge) devices. Writing support for +these in assembly became difficult and a better solution was needed. +This is where ROMCC came to the rescue in 2002. ROMCC is a 25K lines +of code C compiler, written by Eric Biederman, that does not use a +stack but uses CPU registers instead. Besides the 8 general purpose +registers on x86 the MMX and SSE registers, respectively _%mm0_-_%mm7_ +and _%xmm0_-_%xmm7_, can be used to store data. ROMCC also converts +all function calls to static inline functions. This has the +disadvantage that a ROMCC compiled stage must be compiled in one go, +linking is not possible. In practice you will see a lot of '#include +_some_file.c_' which is quite unusual in C, because it makes the +inclusion of files fragile. Given that limited amount +'register-stack', it also imposes restrictions on how many levels of +nested function can be achieved. One last issue with ROMCC is that +no-one really dared touching that code, due to its size and complexity +besides its original author. + +Coreboot used ROMCC in the following way: a bootblock written in both +assembly to enter 32bit protected mode would use ROMCC compiled code +to either jump to 'normal/romstage' or 'fallback/romstage' which in +turn was also compiled with romstage. + +### Cache-as-Ram + +While ROMCC was eventually used for early initialization, prior to +that development attempts were made to use the CPU's cache as RAM. +This would allow to use regular GCC compiled and linked code to +be used. The idea is to set up the CPU's cache to Write Back to a +region, while disable cacheline filling or simply hope that no cache +eviction or invalidation happens. Eric Biederman initially got CAR +working, but with the advent of Intel Hyperthreading on the Pentium 4, +on which CAR setup proved to be a little more difficult and he +developed ROMCC instead. + +Around 2006 a lot was learned from coreboot v2 with its ROMCC usage +and development on coreboot v3 was started. The decision was mode to +not use ROMCC anymore and use Cache Memory for early stages. The +results were good as init object code size is reduced by factor of +four. So the code was smaller and faster at the same time. + +coreboot v4 sort of merged v2 and v3, so it was a mix of ROMCC compiled +romstage and romstage with CAR. + +In 2014 Support for ROMCC compiled romstage was dropped. + +### Intel Apollolake, a new era: POSTCAR_STAGE and C_ENVIRONMENT_BOOTBLOCK + +In 2016 Intel released the ApolloLake architecture. This architecture +is a weird duck in the X86 pool. It is the first Intel CPU to feature +MMC as a boot medium and does not memory map it. It also features to +the main CPU read only SRAM that is mapped right below 4G. The +bootblock is copied to SRAM and executed. Given that the boot medium +is not always memory mapped XIP is not an option. The solution is to +set up CAR in the bootblock and copy the romstage in CAR. We call this +C_ENVIRONMENT_BOOTBLOCK, because it runs GCC compiled code. Granted +XIP is still possible on ApolloLake, but coreboot has to use Intel's +blob, FSP-M, and it is linked to run in CAR, so a blob actually forced +a nice feature in coreboot! + +Another issue arises with this setup. With romstage running from the +read only boot medium, you can continue executing code (albeit without +stack) to tear down the CAR and start executing code from 'real' RAM. +On ApolloLake with romstage executing from CAR, tearing down CAR in +there, would shooting in ones own foot, as our code would be gone +in doing so. The solution was to tear down CAR in a separate stage, +named 'postcar' stage. This provides a clean separation of programs +and results in needing less linker scripts hacks in romstage. This +solution was therefore adopted by many other platforms that still did +XIP. + +### AMD Zen, 2019 + +On AMD Zen the first CPU to come out of reset is the PSP and it +initializes the dram before pulling out the main CPU out of reset. +CAR won't be needed, nor used on this platform. + +### The future? + +For coreboot release 4.11, scheduled for october 2019, support for +ROMCC in the bootblock will be dropped as will support for the messy +tearing down of CAR in romstage as opposed to doing that in a separate +stage. + +## In depth analysis + +### CAR setup + +TODO: MTRR, IPI/hyperthreaded, ROM Caching, Non-evict + +### Linker symbols + +TODO: sharing things over multiple CAR stages: car.ld + +### CAR teardown + +TODO: postcarstage, NO_CAR_GLOBAL_MIGRATION + +## References +[2007, The Open Source BIOS is Ten An interview with the coreboot developers](http://www.h-online.com/open/features/The-Open-Source-BIOS-is-T… +[A Framework for Using Processor Cache-as-Ram (CAR)](https://www.coreboot.org/images/6/6c/LBCar.pdf) +[CAR: Using Cache-as-Ram in LinuxBIOS](https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf) diff --git a/Documentation/index.md b/Documentation/index.md index 1c04ad3..85666cb 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -177,6 +177,7 @@ * [Display panel-specific documentation](gfx/display-panel.md) * [Architecture-specific documentation](arch/index.md) * [Platform independend drivers documentation](drivers/index.md) +* [CPU-specific documentation](cpu/index.md) * [Northbridge-specific documentation](northbridge/index.md) * [System on Chip-specific documentation](soc/index.md) * [Mainboard-specific documentation](mainboard/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Gerrit-Change-Number: 36126 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/skylake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42213 ) Change subject: soc/intel/skylake: Add romstage common stage file ...................................................................... soc/intel/skylake: Add romstage common stage file Change-Id: I31dc5baca23c3d339fbe5fb06b8049789d9ba415 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc D src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c 6 files changed, 13 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42213/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 27c1084..c7b61bd 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -81,6 +81,8 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_ROMSTAGE config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 75121ab..ee81567 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -106,6 +106,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index b9eea98..cb11f50 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 1b069b6..dff89ce 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-y += pch.c diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index c85bdd6..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <intelblocks/tco.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444a..c709cf8 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,6 +21,7 @@ #include <soc/systemagent.h> #include <string.h> #include <security/vboot/vboot_common.h> +#include <intelbasecode/romstage.h> #include "../chip.h" @@ -37,6 +38,8 @@ CHANNEL_PRESENT }; +void romstage_cpu_init(void) {/*Stub function*/} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -126,20 +129,10 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void mainboard_romstage_entry(void) +void romstage_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps; - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); - ps = pmc_get_power_state(); - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!romstage_is_s3wake()) save_dimm_info(); } @@ -269,7 +262,7 @@ m_cfg->PrimaryDisplay = config->PrimaryDisplay; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +void romstage_soc_mem_init_params(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_skylake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -303,6 +296,10 @@ soc_primary_gfx_config_params(m_cfg, config); m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; +} + +void romstage_mb_mem_init_params(FSPM_UPD *mupd) +{ mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31dc5baca23c3d339fbe5fb06b8049789d9ba415 Gerrit-Change-Number: 42213 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/cannonlake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37883 ) Change subject: soc/intel/cannonlake: Add romstage common stage file ...................................................................... soc/intel/cannonlake: Add romstage common stage file Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/romstage.c 3 files changed, 124 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37883/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e99..16bcad6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -113,6 +113,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a..9adae3d 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -27,109 +27,6 @@ #include "../chip.h" -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) -{ - unsigned int i; - uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); - - /* Set IGD stolen size to 64MB. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) - m_cfg->UserBd = BOARD_TYPE_DESKTOP; - else - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; -#if CONFIG(SOC_INTEL_COMETLAKE) - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -#else - m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; -#endif - /* - * PcdDebugInterfaceFlags - * This config will allow coreboot to pass information to the FSP - * regarding which debug interface is being used. - * Debug Interfaces: - * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub - * BIT2 - Not used. - */ - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - -#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; -#endif - - if (config->cpu_ratio_override) { - m_cfg->CpuRatio = config->cpu_ratio_override; - } else { - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; - } - - /* If ISH is enabled, enable ISH elements */ - if (!dev) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = dev->enabled; - - /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; - - /* Enable IPU only if the device is enabled */ - m_cfg->SaIpuEnable = 0; - dev = pcidev_path_on_root(SA_DEVFN_IPU); - if (dev) - m_cfg->SaIpuEnable = dev->enabled; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); - assert(dev != NULL); - const config_t *config = config_of(dev); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - - soc_memory_init_params(m_cfg, config); - - /* Enable SMBus controller based on config */ - if (!smbus) - m_cfg->SmbusEnable = 0; - else - m_cfg->SmbusEnable = smbus->enabled; - - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = - CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; - - /* Configure VT-d */ - tconfig->VtdDisable = 0; - - mainboard_memory_init_params(mupd); -} - __weak void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..668ca50 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -27,6 +27,11 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> +#include <intelbasecode/romstage.h> +#include <assert.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <cpu/x86/msr.h> #include "../chip.h" @@ -41,6 +46,121 @@ /* Default weak implementation, no need to override part number. */ } +void cnlk_soc_post_mem_init(void); + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd); + +static struct romstage_ops cnlk_rs_ops = { + &romstage_cmn_soc_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_soc_mem_init_param, + &mainboard_memory_init_params, + &cnlk_soc_post_mem_init, + &cnlk_soc_post_mem_init +}; + +struct romstage_ops *soc_get_ops(void) +{ + return &cnlk_rs_ops; +} + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd) +{ + unsigned int i; + uint32_t mask = 0; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const config_t *config = config_of(dev); + + assert(dev != NULL); + config = config_of(dev); + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + /* Set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + m_cfg->UserBd = BOARD_TYPE_DESKTOP; + else + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else + m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif + /* + * PcdDebugInterfaceFlags + * This config will allow coreboot to pass information to the FSP + * regarding which debug interface is being used. + * Debug Interfaces: + * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub + * BIT2 - Not used. + */ + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; +#endif + + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + + /* If ISH is enabled, enable ISH elements */ + if (!dev) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = dev->enabled; + + /* If HDA is enabled, enable HDA elements */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + /* Enable IPU only if the device is enabled */ + m_cfg->SaIpuEnable = 0; + dev = pcidev_path_on_root(SA_DEVFN_IPU); + if (dev) + m_cfg->SaIpuEnable = dev->enabled; + + /* Enable SMBus controller based on config */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + if (!dev) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = dev->enabled; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = + CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + + /* Configure VT-d */ + mupd->FspmTestConfig.VtdDisable = 0; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -125,19 +245,10 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void mainboard_romstage_entry(void) +void cnlk_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps = pmc_get_power_state(); - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!cnlk_rs_ops.is_s3wake()) save_dimm_info(); } + -- To view, visit https://review.coreboot.org/c/coreboot/+/37883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc Gerrit-Change-Number: 37883 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: Apple Mac Mini (mid 2011)
by Mac Mini (Code Review) 07 Aug '23

07 Aug '23

Mac Mini has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49074 ) Change subject: Apple Mac Mini (mid 2011) ...................................................................... Apple Mac Mini (mid 2011) Autoported and tested on real device Signed-off-by: Mac Mini <mac-mini-2011(a)outlook.com> Change-Id: Ied578e8a9c7ff2c041b5495491acb256019f1c6d --- A src/mainboard/apple/macmini5_1/Kconfig A src/mainboard/apple/macmini5_1/Kconfig.name A src/mainboard/apple/macmini5_1/Makefile.inc A src/mainboard/apple/macmini5_1/acpi/ec.asl A src/mainboard/apple/macmini5_1/acpi/platform.asl A src/mainboard/apple/macmini5_1/acpi/superio.asl A src/mainboard/apple/macmini5_1/acpi_tables.c A src/mainboard/apple/macmini5_1/board_info.txt A src/mainboard/apple/macmini5_1/devicetree.cb A src/mainboard/apple/macmini5_1/dsdt.asl A src/mainboard/apple/macmini5_1/early_init.c A src/mainboard/apple/macmini5_1/gma-mainboard.ads A src/mainboard/apple/macmini5_1/gpio.c A src/mainboard/apple/macmini5_1/hda_verb.c A src/mainboard/apple/macmini5_1/mainboard.c 15 files changed, 494 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49074/1 diff --git a/src/mainboard/apple/macmini5_1/Kconfig b/src/mainboard/apple/macmini5_1/Kconfig new file mode 100644 index 0000000..edc994e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig @@ -0,0 +1,36 @@ +if BOARD_APPLE_MACMINI5_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select MAINBOARD_HAS_LIBGFXINIT + # select HAVE_CMOS_DEFAULT + # select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default "apple/macmini5_1" + +config MAINBOARD_PART_NUMBER + string + default "Macmini5,1" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO + int + default 30 +endif diff --git a/src/mainboard/apple/macmini5_1/Kconfig.name b/src/mainboard/apple/macmini5_1/Kconfig.name new file mode 100644 index 0000000..bca6a27 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACMINI5_1 + bool "Macmini5,1" diff --git a/src/mainboard/apple/macmini5_1/Makefile.inc b/src/mainboard/apple/macmini5_1/Makefile.inc new file mode 100644 index 0000000..e402ffa --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macmini5_1/acpi/ec.asl b/src/mainboard/apple/macmini5_1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/ec.asl diff --git a/src/mainboard/apple/macmini5_1/acpi/platform.asl b/src/mainboard/apple/macmini5_1/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macmini5_1/acpi/superio.asl b/src/mainboard/apple/macmini5_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/superio.asl diff --git a/src/mainboard/apple/macmini5_1/acpi_tables.c b/src/mainboard/apple/macmini5_1/acpi_tables.c new file mode 100644 index 0000000..161689d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macmini5_1/board_info.txt b/src/mainboard/apple/macmini5_1/board_info.txt new file mode 100644 index 0000000..85a3d5d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macmini5_1/devicetree.cb b/src/mainboard/apple/macmini5_1/devicetree.cb new file mode 100644 index 0000000..820bba9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/devicetree.cb @@ -0,0 +1,77 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00e6 + end + device pci 01.0 on # PCI Express Graphics + subsystemid 0x106b 0x00e6 + end + device pci 01.1 on # Thunderbolt + subsystemid 0x106b 0x00e6 + end + device pci 02.0 on # iGPU + subsystemid 0x106b 0x00e6 + end + device pci 04.0 off end # Signal Processing Controller ?? + + chip southbridge/intel/bd82x6x # Intel Series 6 Chipset + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1a.7 on end + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # Ethernet Controller + device pci 1c.1 on end # Broadcom WiFi + device pci 1c.2 on end # FireWire + + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.7 on end + + device pci 1e.0 off end # PCI bridge + + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macmini5_1/dsdt.asl b/src/mainboard/apple/macmini5_1/dsdt.asl new file mode 100644 index 0000000..27d14ae --- /dev/null +++ b/src/mainboard/apple/macmini5_1/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/apple/macmini5_1/early_init.c b/src/mainboard/apple/macmini5_1/early_init.c new file mode 100644 index 0000000..c02d482 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/early_init.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/apple/macmini5_1/gma-mainboard.ads b/src/mainboard/apple/macmini5_1/gma-mainboard.ads new file mode 100644 index 0000000..e07e1e9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, HDMI1, DP3, HDMI3, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macmini5_1/gpio.c b/src/mainboard/apple/macmini5_1/gpio.c new file mode 100644 index 0000000..e69fd26 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macmini5_1/hda_verb.c b/src/mainboard/apple/macmini5_1/hda_verb.c new file mode 100644 index 0000000..e622098 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2100, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x106b2100), + AZALIA_PIN_CFG(0, 0x09, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0a, 0x002b4040), + AZALIA_PIN_CFG(0, 0x0b, 0x90100130), + AZALIA_PIN_CFG(0, 0x0c, 0x008b3010), + AZALIA_PIN_CFG(0, 0x0d, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x00cbe020), + AZALIA_PIN_CFG(0, 0x10, 0x004be050), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560010), + AZALIA_PIN_CFG(3, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macmini5_1/mainboard.c b/src/mainboard/apple/macmini5_1/mainboard.c new file mode 100644 index 0000000..e90d85e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/49074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied578e8a9c7ff2c041b5495491acb256019f1c6d Gerrit-Change-Number: 49074 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Mini <mac-mini-2011(a)outlook.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/...
by Matt Parnell (Code Review) 07 Aug '23

07 Aug '23

Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34946 ) Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ...................................................................... WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/ec/hp/it8987e/Kconfig A src/ec/hp/it8987e/Makefile.inc A src/ec/hp/it8987e/acpi/ac.asl A src/ec/hp/it8987e/acpi/battery.asl A src/ec/hp/it8987e/acpi/ec.asl A src/ec/hp/it8987e/acpi/kb.asl A src/ec/hp/it8987e/acpi/superio.asl A src/ec/hp/it8987e/acpi/tpm.asl A src/ec/hp/it8987e/chip.h A src/ec/hp/it8987e/ec.c A src/ec/hp/it8987e/ec.h A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 31 files changed, 5,065 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/1 diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig new file mode 100644 index 0000000..54f7896 --- /dev/null +++ b/src/ec/hp/it8987e/Kconfig @@ -0,0 +1,4 @@ +config EC_HP_IT8987E + bool + help + Interface to QUANTA/HP IT8987E Embedded Controller. diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc new file mode 100644 index 0000000..db11205 --- /dev/null +++ b/src/ec/hp/it8987e/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_EC_HP_IT8987E),y) + +romstage-y += ec.c +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl new file mode 100644 index 0000000..bb4b4fe --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ac.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + Local0 = ^^PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = One + } + + Return (Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl new file mode 100644 index 0000000..75efd92 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, One) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, Zero) + Name (B1ST, 0x0F) + Name (B1WT, Zero) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = ^^PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [One] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += One + If ((^^PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == One)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = ^^PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = ^^PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [Zero] = One + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == One)) + { + Local0 = ^^PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [One] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [One] = Local3 + } + } + Else + { + PBST [One] = Local0 + } + } + Else + { + PBST [One] = 0xFFFFFFFF + } + + Local5 = ^^PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl new file mode 100644 index 0000000..0692ced --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ec.asl @@ -0,0 +1,1201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (PHOT, One) + Name (ECAV, Zero) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (BFFR, ResourceTemplate () + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + Return (BFFR) /* \_SB_.PCI0.LPCB.EC0_._CRS.BFFR */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + ^^^GFX0.CLID = 0x03 + Return (0x0F) + } + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, Zero) + Name (BATO, Zero) + Name (BATN, Zero) + Name (BATF, 0xC0) + Name (TMEE, Zero) + Name (TMDE, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = One + GBAS () + ECMI () + } + } + + Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events + { + Local0 = GGPE (0x02020017) + Return (Local0) + } + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = One + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = Zero + EBPL = Zero + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == One)) + { + BATF = Zero + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= One + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = Zero + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + ^^^GFX0.GHDS (Zero) + Sleep (0xC8) + } + + Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "!!! Wireless Button pressed !!!" + If ((OSYS >= 0x07DC)) + { + Notify (WLBT, 0x80) // Status Change + } + Else + { + If (BNLS) + { + BNLS = Zero + Local0 = One + } + Else + { + BNLS = One + Local0 = Zero + } + + If ((^^^^WMID.WMIF == One)) + { + If (((WWLS == One) & (WLDS == One))) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If (((WBTS == One) & (BTDS == One))) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + Else + { + If ((WLDS == One)) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If ((BTDS == One)) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + } + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + If (SW2S) + { + ^^^^WMID.GWEV (0x03, Zero) + } + } + + PNOT () + } + } + + Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((BCTF || BMNF)) + { + ^^^^WMID.GWEV (0x12, One) + } + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + BACR = Zero + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == One)) + { + PSIN = 0xFF + Sleep (One) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (One) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((ENWD == One)) + { + TMPR = One + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((CVTS == One)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == Zero)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((PVSS == One)) + { + If ((PVSE == One)) + { + ^^^^WMID.GWEV (0x14, 0xFE) + } + Else + { + ^^^^WMID.GWEV (0x14, 0xFF) + } + } + } + } + + Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x00020001, Zero) + } + + Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x04, Zero) + } + + Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, Zero) + } + + Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, One) + } + + Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q82 : Temperature reachs for Turbo Mode OFF" + TMDE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q83 : Temperature reachs for Turbo Mode ON" + TMEE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = Zero + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + + Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + If (Local0) + { + Local0-- + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local1 = Zero + Local0 = PKPS /* \PKPS */ + If ((Local0 > 0x80)) + { + Local0 -= 0x80 + While ((Local0 > 0x06)) + { + Local0 -= 0x10 + Local1 += 0x06 + } + + Local1 += Local0 + If (((Local1 >= 0x07) & (Local1 <= 0x0C))) + { + Local1 += 0x12 + } + ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12))) + { + Local1 += 0x06 + } + ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18))) + { + Local1 -= 0x0C + } + ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E))) + { + Local1 -= 0x0C + } + + Stall (0x05) + Local0 = Zero + Local3 = OFDA /* \OFDA */ + While ((Local1 > One)) + { + Local2 = DerefOf (Local3 [Local0]) + Local0 += Local2 + Local1 -= One + } + + Stall (0x0F) + Local1 = DerefOf (Local3 [Local0]) + Local2 = Zero + Stall (0x0F) + Name (KPFT, Buffer (0xA0){}) + While ((Local2 < 0xA0)) + { + If ((Local1 > Zero)) + { + KPFT [Local2] = DerefOf (Local3 [Local0]) + Local0++ + Local1 -= One + } + Else + { + KPFT [Local2] = Zero + } + + Local2++ + Stall (0x05) + } + + PKMC = KPFT /* \_SB_.PCI0.LPCB.EC0_._QE4.KPFT */ + PKWD = One + } + } + + Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x12, PKPS) + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMW0, 16 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMB0, 8 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD0, 64 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD1, 128 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD2, 192 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD3, 256 + } + + Mutex (MUT0, 0x00) + Mutex (MUT1, 0x00) + Mutex (MUT2, 0x00) + Method (SMRD, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x07)) + { + If ((Arg0 != 0x09)) + { + If ((Arg0 != 0x0B)) + { + If ((Arg0 != 0x47)) + { + If ((Arg0 != 0xC7)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + Else + { + If ((Arg0 == 0x07)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x47)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0xC7)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x09)) + { + Arg3 = SMW0 /* \_SB_.PCI0.LPCB.EC0_.SMW0 */ + } + + If ((Arg0 == 0x0B)) + { + Local3 = BCNT /* \_SB_.PCI0.LPCB.EC0_.BCNT */ + Local2 = 0x20 + If ((Local3 > Local2)) + { + Local3 = Local2 + } + + If ((Local3 < 0x11)) + { + Local2 = FLD1 /* \_SB_.PCI0.LPCB.EC0_.FLD1 */ + } + ElseIf ((Local3 < 0x19)) + { + Local2 = FLD2 /* \_SB_.PCI0.LPCB.EC0_.FLD2 */ + } + Else + { + Local2 = FLD3 /* \_SB_.PCI0.LPCB.EC0_.FLD3 */ + } + + Local3++ + Local4 = Buffer (Local3){} + Local3-- + Local5 = Zero + Name (OEMS, Buffer (0x46){}) + ToBuffer (Local2, OEMS) /* \_SB_.PCI0.LPCB.EC0_.SMRD.OEMS */ + While ((Local3 > Local5)) + { + GBFE (OEMS, Local5, RefOf (Local6)) + PBFE (Local4, Local5, Local6) + Local5++ + } + + PBFE (Local4, Local5, Zero) + Arg3 = Local4 + } + } + + Release (MUT0) + Return (Local0) + } + + Method (SMWR, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x06)) + { + If ((Arg0 != 0x08)) + { + If ((Arg0 != 0x0A)) + { + If ((Arg0 != 0x46)) + { + If ((Arg0 != 0xC6)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + If ((Arg0 == 0x06)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x46)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0xC6)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x08)) + { + SMW0 = Arg3 + } + + If ((Arg0 == 0x0A)) + { + SMD0 = Arg3 + } + + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + + Release (MUT0) + Return (Local0) + } + + Method (GSHK, 0, Serialized) + { + If ((ECOK == One)) + { + Local0 = SFHK /* \_SB_.PCI0.LPCB.EC0_.SFHK */ + } + + Return (Local0) + } + + Method (SSHK, 1, Serialized) + { + If ((ECOK == One)) + { + SFHK = Arg0 + } + } + + Method (CPUS, 1, NotSerialized) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + \_PR.CPPC = Arg0 + } + + If ((TCNT == 0x08)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + Notify (\_PR.PR04, 0x80) // Performance Capability Change + Notify (\_PR.PR05, 0x80) // Performance Capability Change + Notify (\_PR.PR06, 0x80) // Performance Capability Change + Notify (\_PR.PR07, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x04)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x02)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + } + Else + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + } + } + + Method (ECMI, 0, NotSerialized) + { + If ((ECOK == One)) + { + OSTD () + CLOW = Zero + CMAX = (MPPP - One) + ACKY = FNKY /* \FNKY */ + SASU () + If ((SMA4 == One)) + { + SMSZ = Zero + } + Else + { + SMSZ = One + } + + ULID (Zero) + } + } + + Method (SASU, 0, NotSerialized) + { + If ((ECOK == One)) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If (((SW2S == Zero) || ((SADP >= One) & ( + SADP <= 0x02)))) + { + Local0 = Zero + CPUS (Local0) + CLOW = Local0 + } + + If ((SADP == 0x03)) + { + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + CLOW = Local0 + } + } + } + } + + Method (RPIO, 2, NotSerialized) + { + Local0 = Zero + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + Local0 = EI03 /* \EI03 */ + } + + Return (Local0) + } + + Method (WPIO, 3, NotSerialized) + { + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + EI03 = Arg2 + } + } + + Method (ECMD, 3, NotSerialized) + { + If ((ECOK == One)) + { + WPIO (Arg0, Arg1, Arg2) + While (EI03) + { + Stall (0xFF) + } + + Local0 = RPIO (0xFB, Zero) + Return (Local0) + } + } + + Method (CBCD, 0, NotSerialized) + { + If ((ECOK == One)) + { + Local0 = MBDC /* \_SB_.PCI0.LPCB.EC0_.MBDC */ + Local0 &= 0xE4 + MBDC = Local0 + } + } + + Method (ULID, 1, NotSerialized) + { + If ((ECOK == One)) + { + If ((ECLS == One)) + { + Local0 = Zero + } + Else + { + Local0 = One + } + + If (IGDS) + { + If ((Arg0 == One)) + { + If ((Local0 != LIDS)) + { + If (^^^GFX0.GLID (Local0)) + { + If ((LIDS == Zero)) + { + ^^^GFX0.CLID |= 0x80000000 /* External reference */ + } + + If ((LIDS == One)) + { + ^^^GFX0.CLID |= 0x80000001 /* External reference */ + } + } + } + } + } + + LIDS = Local0 + } + } + + Method (OSTD, 0, NotSerialized) + { + If ((ECOK == One)) + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + If ((OSYS >= 0x07D0)) + { + If ((OSYS >= 0x07D9)) + { + W7OS = One + If ((OSKU == Zero)) + { + W7OS = Zero + } + } + } + Else + { + If ((OSYS == 0x03E8)) + { + RFLG = One + } + + If ((OSYS == 0x03E9)) + { + SUSE = One + } + } + } + Else + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + } + } + + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "tpm.asl" +} diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl new file mode 100644 index 0000000..bc42897 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/kb.asl @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((CHID == 0x25)) + { + Return ("*SYN326A") + } + Else + { + Return ("*SYN326A") + } + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/ec/hp/it8987e/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h new file mode 100644 index 0000000..1bc9949 --- /dev/null +++ b/src/ec/hp/it8987e/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _EC_HP_IT8987E_CHIP_H +#define _EC_HP_IT8987E_CHIP_H + +#include <device/device.h> + +struct chip_operations; +extern struct chip_operations ec_quanta_it8987e_ops; + +struct ec_quanta_it8987e_config { +}; + +#endif /* _EC_HP_IT8987E_CHIP_H */ diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c new file mode 100644 index 0000000..db6fe3c --- /dev/null +++ b/src/ec/hp/it8987e/ec.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> + +#include "ec.h" +#include "chip.h" + +/* helper functions from drivers/pc80/keyboard.c */ +static int input_buffer_empty(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); + timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n"); + printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + +static int output_buffer_full(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) + & KBD_OBF) == 0); timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n"); + printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + + +/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or may not respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!output_buffer_full(KBD_STATUS)) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the IT8987E device RAM space via 0x66/0x68 + */ + +u8 ec_read_ob(void) +{ + if (!output_buffer_full(EC_SC)) return 0; + return inb(EC_DATA); +} + +void ec_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(cmd, EC_SC); +} + +void ec_write_ib(u8 data) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(data, EC_DATA); +} + +u8 ec_read(u16 addr) +{ + ec_write_cmd(RD_EC); + ec_write_ib(addr); + return ec_read_ob(); +} + +void ec_write(u16 addr, u8 data) +{ + ec_write_cmd(WR_EC); + ec_write_ib(addr); + ec_write_ib(data); +} + +#ifndef __PRE_RAM__ + +u8 ec_it8987e_get_event(void) +{ + u8 cmd = 0; + u8 status = inb(EC_SC); + if (status & SCI_EVT) { + ec_write_cmd(QR_EC); + cmd = ec_read_ob(); + } else if (status & SMI_EVT) { + ec_kbc_write_cmd(EC_KBD_SMI_EVENT); + cmd = ec_kbc_read_ob(); + } + return cmd; +} + +void ec_it8987e_enable_wake_events(void) +{ + /* + * Set the bit in ECRAM that will enable the Lid switch as a wake source + */ + u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE); + ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); +} + +#ifndef __SMM__ +static void it8987e_init(struct device *dev) +{ + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static struct device_operations ops = { + .init = it8987e_init, + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_quanta_it8987e_ops = { + CHIP_NAME("QUANTA IT8987E EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h new file mode 100644 index 0000000..f87b2c0 --- /dev/null +++ b/src/ec/hp/it8987e/ec.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Modified by Matt Parnell <mparnell(a)gmail.com> to support ITL 8987E + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * EC communication interface for QUANTA IT8987E Embedded Controller. + */ + +#ifndef _EC_HP_IT8987E_EC_H +#define _EC_HP_IT8987E_EC_H + +#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* Wait 400ms for keyboard controller ansswers */ +#define KBC_TIMEOUT_IN_MS 400 + +// 60h/64h Command Interface +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + +#define EC_KBD_SMI_EVENT 0xCD +#define EC_KBD_CMD_UNMUTE 0xE8 +#define EC_KBD_CMD_MUTE 0xE9 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); + +// 62h/66h Command Interface +#define EC_DATA 0x62 +#define EC_SC 0x66 // Status & Control Register +#define SMI_EVT (1 << 6) // 1: SMI event was triggered +#define SCI_EVT (1 << 5) // 1: SCI event was triggered + +// EC Commands (defined in ec_function_spec v3.12) +#define RD_EC 0x80 +#define WR_EC 0x81 +#define QR_EC 0x84 + +#define EC_CMD_EXIT_BOOT_BLOCK 0x85 +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 +#define EC_CMD_WARM_RESET 0x8C + +// ECRAM Offsets +#define EC_PERIPH_CNTL_3 0x0D +#define EC_USB_S3_EN 0x26 +#define EC_PERIPH_STAT_3 0x35 +#define EC_THERM_0 0x78 +#define EC_WAKE_SRC_ENABLE 0xBF +#define EC_FW_VER 0xE8 // 2 Bytes +#define EC_IF_MIN_VER 0xEB +#define EC_STATUS_REG 0xEC +#define EC_IF_MAJ_VER 0xEF +#define EC_MBAT_STATUS 0x0138 + + +// EC 0.83b added status bits: +// BIT0=EC in RO mode +// BIT1=Recovery Key Sequence Detected +#define EC_IN_RO_MODE 0x1 +#define EC_IN_RECOVERY_MODE 0x3 + +// EC 0.86a added enable bit: +#define EC_LID_WAKE_ENABLE 0x4 + +u8 ec_read_ob(void); +void ec_write_cmd(u8 cmd); +void ec_write_ib(u8 data); + +u8 ec_read(u16 addr); +void ec_write(u16 addr, u8 data); +u8 ec_it8987e_get_event(void); +void ec_it8987e_enable_wake_events(void); + +#endif /* _EC_HP_IT8987E_EC_H */ diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig new file mode 100644 index 0000000..00542d7 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig @@ -0,0 +1,59 @@ +config BOARD_HP_SPECTRE_AE000 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform does not have any way to see POST codes + +if BOARD_HP_SPECTRE_AE000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "HP" + +config MAINBOARD_FAMILY + string + default "HP Spectre x360" + +config MAINBOARD_PART_NUMBER + string + default "13t-ae000" + +config MAINBOARD_DIR + string + default "hp/hp_spectre_x360_13_convertible" + +config DEVICETREE + string + default "devicetree.cb" + +config FMDFILE + string + default "" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name new file mode 100644 index 0000000..9f089a5 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_SPECTRE_AE000 + bool "Spectre x360 13t-ae000" diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl new file mode 100644 index 0000000..489bdcd --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (ADP1) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = 1 + } + + Return (Local0) + } + + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } +} + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID + Method (_LID, 0, NotSerialized) // _LID: Lid Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.ECLS == 1)) + { + Local0 = 0 + } + Else + { + Local0 = 1 + } + } + Else + { + Local0 = 1 + } + + /* \_SB_.PCI0.LPCB.EC0.ULID (1) */ + Return (Local0) + } +} + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl new file mode 100644 index 0000000..94ce92c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, 1) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + 1, + 0xFFFFFFFF, + 0xFFFFFFFF, + 1, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, 0) + Name (B1ST, 0x0F) + Name (B1WT, 0) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = \_SB_.PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [1] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += 1 + If ((\_SB_.PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == 1)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = \_SB_.PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = \_SB_.PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [0] = 1 + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [1] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [1] = Local3 + } + } + Else + { + PBST [1] = Local0 + } + } + Else + { + PBST [1] = 0xFFFFFFFF + } + + Local5 = \_SB_.PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!\_SB_.PCI0.LPCB.EC0.SW2S && (\_SB_.PCI0.LPCB.EC0.BACR == 1))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = \_SB_.PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [0] = \_SB_.PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl new file mode 100644 index 0000000..a417560 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl @@ -0,0 +1,393 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_GPE, 0x17) + Name (PHOT, 1) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, 0) + Name (BATO, 0) + Name (BATN, 0) + Name (BATF, 0xC0) + Name (TMEE, 0) + Name (TMDE, 0) + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = 1 + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = 0 + EBPL = 0 + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == 1)) + { + BATF = 0 + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= 1 + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = 0 + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + /*\_SB_.PCI0.GFX0.GHDS (0)*/ /*Todo: fixme? where is this guy defined? */ + Sleep (0xC8) + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + } + + PNOT () + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + BACR = 0 + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == 1)) + { + PSIN = 0xFF + Sleep (1) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (1) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((ENWD == 1)) + { + TMPR = 1 + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((CVTS == 1)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == 0)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + /* _Q80 _Q82 _Q83 thermal zone methods removed */ + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = 0 + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + +/* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "mainboard.asl" +/*#include "tpm.asl"*/ +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl new file mode 100644 index 0000000..296cdba --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((OSYS >= 0x07DC)) + { + Return ("HPQ8001") + } + Else + { + Return ("PNP0303") + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + Return ("*SYN326A") + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl new file mode 100644 index 0000000..3c7189b --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl @@ -0,0 +1,282 @@ + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (RTC) +{ + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Scope (\_SB.PCI0.LPCB.RTC) +{ + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Device (VBPA) +{ + Name (_HID, "INT33D6" /* Intel Virtual Buttons Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (0) + } + } + + Name (VBST, 0) + Method (VBDL, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + } + + Method (VGBS, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + + Return (VBST) /* \_SB_.VBPA.VBST */ + } +} + +Device (CIND) +{ + Name (_HID, "INT33D3" /* Intel GPIO Buttons */) // _HID: Hardware ID + Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0B) + } + Else + { + Return (0) + } + } +} + +Device (GFX0) +{ + Name (_ADR, 0x00020000) // _ADR: Address +} + +Device (B0D4) +{ +Method (PCIC, 1, Serialized) + { + If ((ECR1 == One)) + { + If ((Arg0 == PCIG)) + { + Return (One) + } + } + + Return (Zero) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If (PCIC (Arg0)) + { + Return (PCID (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (1) + { + 0x00 // . + }) + } + + Name (_ADR, 0x00040000) // _ADR: Address +} + +Device (ISP0) +{ + Name (_ADR, 0x00050000) // _ADR: Address +} + +Scope (\) +{ + Name (PCIG, ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */) + Name (KBWK, 0) + Name (TPWK, 0) + + Field (GNVS, AnyAcc, Lock, Preserve) + { + ECR1, 8 + } + + OperationRegion (EXBU, SystemMemory, 0x2F822018, 0x3008) + Field (EXBU, AnyAcc, Lock, Preserve) + { + AEAX, 32, + AEBX, 32, + AECX, 32, + AEDX, 32, + AREF, 32, + DAB0, 8, + DAB1, 8, + DAB2, 8, + DAB3, 8, + WBUF, 1024, + TJMX, 8, + FNKY, 8, + CAME, 8, + VTDT, 8, + DPMD, 8, + WLVD, 16, + WLDD, 16, + WLSV, 16, + WLSS, 16, + BTVD, 16, + BTDD, 16, + WWVD, 16, + WWDD, 16, + WMVD, 16, + WMDD, 16, + GPVD, 16, + GPDD, 16, + SMA4, 8, + PMEE, 8, + WSD0, 8, + WSD1, 8, + WSD2, 8, + WSD3, 8, + WAR7, 8, + DBCM, 8, + CPUP, 64, + GPUP, 32, + SYSP, 64, + FANP, 32, + BATP, 32, + HDDP, 32, + CPUT, 8, + GPUT, 8, + SYST, 8, + FANT, 8, + BATT, 8, + TTST, 8, + RTCF, 8, + BODD, 8, + BRTM, 8, + NOCD, 8, + PWVD, 16, + PWDD, 16, + PWSV, 16, + PWSS, 16, + Offset (0x400), + SBUF, 2048 + } + + Method (PCID, 4, Serialized) + { + If ((Arg0 == PCIG)) + { + If ((Arg1 >= 0x03)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0x01, 0x03 // .. + }) + } + + If ((Arg2 == 0x08)) + { + Return (One) + } + + If ((Arg2 == 0x09)) + { + Return (Package (0x05) + { + 0xC350, + Ones, + Ones, + 0xC350, + Ones + }) + } + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt new file mode 100644 index 0000000..62be952 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt @@ -0,0 +1,10 @@ +Vendor name: HP +Board name: Spectre 13t-ae000 +Board serial: DAOX33MBAFO +Board URL: https://support.hp.com/us-en/product/HP-Spectre-13-ae000-x360-Convertible-P… +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb new file mode 100644 index 0000000..2bf6b15 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + +# these are probably very wrong + # Enable EC Port 0x68/0x6C + register "gen1_dec" = "0x00040069" + + # EC range is 0x800-0x9ff + register "gen2_dec" = "0x00fc0901" + + # EC range is 0x1610-0x161F + register "gen3_dec" = "0x0001C1611" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" # do we actually need this with only nvme? + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + # Enable Root Ports 5 and 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + + # NVMe for port 9 settings + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port Left + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # UHD Graphics 620 + device pci 04.0 on end # Thermal Subsystem DSP + device pci 13.0 on end # Intel Sensor Hub + device pci 14.0 on end # USB 3 Controller + device pci 14.2 on end # Thermal Subsystem DSP + device pci 15.0 on end # I2C Controller + device pci 1c.0 on end # PCIe Root Port 1 + device pci 1c.1 on end # PCIe Root Port 2 + device pci 1c.4 on end # PCIe Root Port 5 + device pci 1d.0 on end # PCIe Root Port 9 + device pci 1e.0 off end # UART + device pci 1e.2 off end # SPI + device pci 1f.0 on end # ISA Bridge + device pci 1f.2 on end # Memory Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl new file mode 100644 index 0000000..d36c960 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x01072009 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h new file mode 100644 index 0000000..42a6287 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* ------- GPIO group GPP_A ------- */ +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x18), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c19), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c1a), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c1b), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c1c), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x1d), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x82080102, 0x1f), +/* CLKRUN# */_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x20), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1021), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1022), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000300, 0x23), +/* ISH_GP6 */_PAD_CFG_STRUCT(GPP_A12, 0x44000b02, 0x24), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x25), +/* GPIO */_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x26), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3027), +/* GPIO */_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x28), +/* GPIO */_PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x29), +/* ISH_GP0 */_PAD_CFG_STRUCT(GPP_A18, 0x44000700, 0x2a), +/* ISH_GP1 */_PAD_CFG_STRUCT(GPP_A19, 0x44000700, 0x2b), +/* ISH_GP2 */_PAD_CFG_STRUCT(GPP_A20, 0x44000700, 0x2c), +/* ISH_GP3 */_PAD_CFG_STRUCT(GPP_A21, 0x44000700, 0x2d), +/* ISH_GP4 */_PAD_CFG_STRUCT(GPP_A22, 0x44000700, 0x2e), +/* ISH_GP5 */_PAD_CFG_STRUCT(GPP_A23, 0x44000502, 0x3f), +/* ------- GPIO Group GPP_B -------*/ +/* GPIO */_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x34), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x36), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x38), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x39), +/* SRCCLKREQ5# */_PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x3a), +/* GPIO */_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x3c), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x3d), +/* SPKR */_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x103e), +/* GSPI0_CS# */_PAD_CFG_STRUCT(GPP_B15, 0x44000700, 0x3f), +/* GSPI0_CLK */_PAD_CFG_STRUCT(GPP_B16, 0x84000700, 0x40), +/* GSPI0_MISO */_PAD_CFG_STRUCT(GPP_B17, 0x44000700, 0x41), +/* GSPI0_MOSI */_PAD_CFG_STRUCT(GPP_B18, 0x84000700, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1044), +/* GPIO */_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1045), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1046), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_C ------- */ +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x48), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1049), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x104a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x4d), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x50), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x51), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x52), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x53), +/* GPIO */_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x54), +/* GPIO */_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x55), +/* GPIO */_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x57), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x58), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x59), +/* GPIO */_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x5b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x5c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x5d), +/* GPIO */_PAD_CFG_STRUCT(GPP_C22, 0x82880102, 0x105e), +/* GPIO */_PAD_CFG_STRUCT(GPP_C23, 0x80880102, 0x5f), +/* ------- GPIO Group GPP_D ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x60), +/* GPIO */_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x61), +/* GPIO */_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x62), +/* GPIO */_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x63), +/* GPIO */_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x64), +/* ISH_I2C0_SDA */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x65), +/* ISH_I2C0_SCL */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x66), +/* ISH_I2C1_SDA */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x67), +/* ISH_I2C1_SCL */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x68), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x82000102, 0x69), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x6a), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x6b), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x6c), +/* GPIO */_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x6d), +/* GPIO */_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x6e), +/* GPIO */_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x6f), +/* GPIO */_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x70), +/* GPIO */_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x71), +/* GPIO */_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x72), +/* GPIO */_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x73), +/* GPIO */_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x74), +/* GPIO */_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x75), +/* GPIO */_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x76), +/* GPIO */_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x77), +/* ------- GPIO Group GPP_E ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x84000102, 0x18), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x84000102, 0x19), +/* SATAXPCIE2 */_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x1a), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1b), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x84000200, 0x101c), +/* GPIO */_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E6, 0x44000300, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1f), +/* GPIO */_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x20), +/* GPIO */_PAD_CFG_STRUCT(GPP_E9, 0x44000300, 0x21), +/* GPIO */_PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x22), +/* GPIO */_PAD_CFG_STRUCT(GPP_E11, 0x80100102, 0x23), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x84000201, 0x24), +/* DDPB_HPD0 */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x25), +/* DDPC_HPD1 */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x26), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880300, 0x27), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000300, 0x28), +/* EDP_HPD */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x29), +/* DDPB_CTRLCLK */_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x2a), +/* DDPB_CTRLDATA */_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x102b), +/* DDPC_CTRLCLK */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x2c), +/* DDPC_CTRLDATA */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x102d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x2e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x102f), +/* ------- GPIO Group GPD ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x50), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x51), +/* GPIO */_PAD_CFG_STRUCT(GPD2, 0x4000200, 0x52), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3053), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x54), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x55), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x57), +/* GPIO */_PAD_CFG_STRUCT(GPD8, 0x44000300, 0x58), +/* GPIO */_PAD_CFG_STRUCT(GPD9, 0x44000300, 0x59), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x44000700, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPD11, 0x44000300, 0x5b), +/* ------- GPIO Group GPP_F ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x34), +/* GPIO */_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x36), +/* GPIO */_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_F8, 0x44000100, 0x38), +/* GPIO */_PAD_CFG_STRUCT(GPP_F9, 0x44000100, 0x39), +/* I2C5_SDA */_PAD_CFG_STRUCT(GPP_F10, 0x44000702, 0x3a), +/* I2C5_SCL */_PAD_CFG_STRUCT(GPP_F11, 0x44000702, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x3c), +/* GPIO */_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x3d), +/* GPIO */_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x3e), +/* GPIO */_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x3f), +/* GPIO */_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x40), +/* GPIO */_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x41), +/* GPIO */_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x44), +/* GPIO */_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x45), +/* GPIO */_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x46), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_G ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x48), +/* GPIO */_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x49), +/* GPIO */_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x4a), +/* GPIO */_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x4d), +/* GPIO */_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x4e), +/* GPIO */_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x4f), +}; + +#endif + +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c new file mode 100644 index 0000000..c0de990 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h new file mode 100644 index 0000000..510a9ce --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, /* Codec Vendor / Device ID: Realtek */ + 0x103c83b9, /* Subsystem ID */ + 0x0000000d, /* Number of NID entries */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x103c83b9 */ + AZALIA_SUBVENDOR(0x0, 0x103c83b9), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + + /* Pin Complex (NID 0x13) */ + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x16) */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11040), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40600001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x03211020), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c new file mode 100644 index 0000000..faf4090 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Gerrit-Change-Number: 34946 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Parnell <mparnell(a)gmail.com> Gerrit-MessageType: newchange

6 55

Change in coreboot[master]: Revert "src/Kconfig: enable USE_BLOBS by default"
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello Julius Werner, Angel Pons, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41848 to review the following change. Change subject: Revert "src/Kconfig: enable USE_BLOBS by default" ...................................................................... Revert "src/Kconfig: enable USE_BLOBS by default" This reverts commit a6b887e017f2310db79067b18b216036907b2d90. It was brought to my attention that the 3rdparty/blobs/ repository is full of licenses that don't adhere to our binary policy (that demands unlimited redistribution rights). IANAL, but if the license texts apply literally, it is not allowed to clone the blobs repository without reading and agreeing to them. Change-Id: I7079e23481eb96d1140f2fa5bc1abe7bd4b2bac8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/Kconfig M util/abuild/abuild 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41848/1 diff --git a/src/Kconfig b/src/Kconfig index 2a2a144..6a748db 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -214,7 +214,6 @@ config USE_BLOBS bool "Allow use of binary-only repository" - default y help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. diff --git a/util/abuild/abuild b/util/abuild/abuild index b6a6bfe..4d5ba35 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -715,7 +715,7 @@ shift;; -B|--blobs) shift customizing="${customizing}, blobs" - configoptions="${configoptions}CONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n" + configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n" ;; -A|--any-toolchain) shift customizing="${customizing}, any-toolchain" -- To view, visit https://review.coreboot.org/c/coreboot/+/41848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7079e23481eb96d1140f2fa5bc1abe7bd4b2bac8 Gerrit-Change-Number: 41848 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/yanling: Add Yanling YL-KBR6L mainboard + doc
by Thomas (Code Review) 07 Aug '23

07 Aug '23

Thomas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48769 ) Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ...................................................................... mb/yanling: Add Yanling YL-KBR6L mainboard + doc The Yanling YL-KBR6L (aka Yanling N18) is a Protecli FW6 with a newer CPUs (i5-8250U), different SuperIO chip (ITE IT8613F), slightly different (newer?) flash memory chip (MX25L6436F) and support for a mPCIe modem. Working: - USB 3.0 front ports (SeaBIOS, Linux and FreeBSD) - 6 Ethernet ports - HDMI port with libgfxinit and VGA Option ROM - flashrom - PCIe WiFi - SATA and mSATA - mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) - Super I/O serial port 0 (RS232 via front RJ45 connector) - SeaBIOS payload (version rel-1.14.0) - Booting Ubuntu 20.04, FreeBSD 12.2 - 64GB RAM (tested with Crucial CT2K32G4SFD8266) Untested (same as Protectli FW6): - Internal USB 2.0 headers - Boot with cleaned ME Misc: - Removed "ProbelessTrace" in devicetree as done for other boards by coreboot. Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a Signed-off-by: Thomas Kupper <thomas.kupper(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/yanling/yl-kbr6l.md A Documentation/mainboard/yanling/yl-kbr6l_front.jpg A src/mainboard/yanling/Kconfig A src/mainboard/yanling/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Kconfig A src/mainboard/yanling/yl_kbr6l/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Makefile.inc A src/mainboard/yanling/yl_kbr6l/acpi/ec.asl A src/mainboard/yanling/yl_kbr6l/acpi/superio.asl A src/mainboard/yanling/yl_kbr6l/board_info.txt A src/mainboard/yanling/yl_kbr6l/bootblock.c A src/mainboard/yanling/yl_kbr6l/data.vbt A src/mainboard/yanling/yl_kbr6l/devicetree.cb A src/mainboard/yanling/yl_kbr6l/dsdt.asl A src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads A src/mainboard/yanling/yl_kbr6l/gpio.h A src/mainboard/yanling/yl_kbr6l/ramstage.c A src/mainboard/yanling/yl_kbr6l/romstage.c 19 files changed, 820 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48769/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..2480069 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -179,3 +179,7 @@ ## UP - [Squared](up/squared/index.md) + +## Yanling + +- [YL-KBR6L](yanling/yl-kbr6l.md) \ No newline at end of file diff --git a/Documentation/mainboard/yanling/yl-kbr6l.md b/Documentation/mainboard/yanling/yl-kbr6l.md new file mode 100644 index 0000000..28d1d56 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l.md @@ -0,0 +1,133 @@ +# Yanling YL-KBR6L + +This board and therefore its documentation is very, very similar to the Protectli FW6. This document is based on theirs, all praise to 3mdeb/Protectli. + +This page describes how to run coreboot on the [Yanling YL-KBR6L], or [Yanling N18] as it seems to be called officially (and its three CPU variants). + +![](yl-kbr6l_front.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using libgfxinit). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.1. Firmware an be easily flashed +with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the bottom side of the case (the radiator side). One +has to remove all screws (in order): 4 top cover screws, 4 side cover screws +(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up +the mainboard and turn around it. The flash chip is near the SoC on the DIMM +slots side. Use a clip (or solder the wires) to program the chip. Specifically, +it's a Macronix MX25L6436F M2I-08Q (3V) - [datasheet][MX25L6436F]. + +## Known issues + +- assume the same as for Protectli FW6: + +- After flashing with external programmer it is always required to reset RTC + with jumper or disconnect coin cell temporarily. Only then the platform will + boot after flashing. +- FW6A does not always work reliably with all DIMMs. Linux happens to hang or + gives many panics. This issue was present also with vendor BIOS. +- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs + connected). A workaround is to power cycle the board (even a few times) or + temporarily disconnect DIMM when platform is powered off. +- When using libgfxinit and SeaBIOS bootsplash, the red color is dim + +## Untested + +- assume the same as for Protectli FW6: + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- Internal USB 2.0 headers +- Boot with cleaned ME + +## Working + +- USB 3.0 front ports (SeaBIOS and Linux) +- 6 Ethernet ports +- HDMI port with libgfxinit and VGA Option ROM +- flashrom +- PCIe WiFi +- SATA and mSATA +- mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) +- Super I/O serial port 0 (RS232 via front RJ45 connector) +- SeaBIOS payload (version rel-1.14) +- Booting Ubuntu 20.04, FreeBSD 12.2 +- 64GB RAM (tested with Crucial CT2K32G4SFD8266) + +## Technology + +```eval_rst ++---------------------+-----------------------------------------------+ +| CPU | [Intel Core i5-8250U] | ++---------------------+-----------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Premium | ++---------------------+-----------------------------------------------+ +| Super I/O, EC | ITE IT8613F | ++---------------------+-----------------------------------------------+ +| Coprocessor | Intel Management Engine | ++---------------------+-----------------------------------------------+ +| Ethernet Controller | 6x Intel I211AT | ++---------------------+-----------------------------------------------+ +``` +Information about the PCH can be found in [Intel 7th and 8th gen datasheet vol 1] and [Intel 7th and 8th gen datasheet vol 2]. + +## Ports + +```eval_rst ++---------------------+-----------------------------------------------+ +| Ethernet | 6x 1GbE | ++---------------------+-----------------------------------------------+ +| USB | 4x USB 3.0 | ++---------------------+-----------------------------------------------+ +| Serial/COM | 1x RJ-45 serial port | ++---------------------+-----------------------------------------------+ +| SATA | 1x mSATA (port 0) + 1x SATA 3.0 (port 1) | ++---------------------+-----------------------------------------------+ +| Cellular Modem | 1x mPCIe, shared with mSATA slot, nano-SIM | ++---------------------+-----------------------------------------------+ +| Wifi/Bluetooth | 1x mPCIe slot, under mSATA/Modem, | +| | supports half-size cards only | ++---------------------+-----------------------------------------------+ +``` + +[flashrom]: https://flashrom.org/Flashrom +[Intel 7th and 8th gen datasheet vol 1]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… +[Intel 7th and 8th gen datasheet vol 2]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… +[MX25L6436F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7405/MX25L6436F,%203V,%… +[Yanling YL-KBR6L]: https://www.aliexpress.com/item/1005001813291053.html +[Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewa… diff --git a/Documentation/mainboard/yanling/yl-kbr6l_front.jpg b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg diff --git a/src/mainboard/yanling/Kconfig b/src/mainboard/yanling/Kconfig new file mode 100644 index 0000000..2972a38 --- /dev/null +++ b/src/mainboard/yanling/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_YANLING + +choice + prompt "Mainboard model" + +source "src/mainboard/yanling/*/Kconfig.name" + +endchoice + +source "src/mainboard/yanling/*/Kconfig" + +config MAINBOARD_VENDOR + default "Yanling" + +endif # VENDOR_YANLING diff --git a/src/mainboard/yanling/Kconfig.name b/src/mainboard/yanling/Kconfig.name new file mode 100644 index 0000000..6cc7ef1 --- /dev/null +++ b/src/mainboard/yanling/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_YANLING + bool "Yanling" diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig b/src/mainboard/yanling/yl_kbr6l/Kconfig new file mode 100644 index 0000000..838bc44 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig @@ -0,0 +1,57 @@ +if BOARD_YANLING_YLKBR6L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select SOC_INTEL_KABYLAKE + select SPI_FLASH_MACRONIX + select SUPERIO_ITE_IT8613E + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "yanling/yl_kbr6l" + +config MAINBOARD_PART_NUMBER + string + default "YLKBR6L" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,5917" + +config PXE_ROM_ID + string + default "8086,1539" + +config CBFS_SIZE + hex + default 0x600000 + +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig.name b/src/mainboard/yanling/yl_kbr6l/Kconfig.name new file mode 100644 index 0000000..8b039de --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_YANLING_YLKBR6L + bool "YLKBR6L" diff --git a/src/mainboard/yanling/yl_kbr6l/Makefile.inc b/src/mainboard/yanling/yl_kbr6l/Makefile.inc new file mode 100644 index 0000000..4cd7aac --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl diff --git a/src/mainboard/yanling/yl_kbr6l/board_info.txt b/src/mainboard/yanling/yl_kbr6l/board_info.txt new file mode 100644 index 0000000..c12e388 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Yanling +Board name: YL-KBR6L +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/yanling/yl_kbr6l/bootblock.c b/src/mainboard/yanling/yl_kbr6l/bootblock.c new file mode 100644 index 0000000..e35a7cc --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/it8613e/it8613e.h> +#include <superio/ite/common/ite.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/yanling/yl_kbr6l/data.vbt b/src/mainboard/yanling/yl_kbr6l/data.vbt new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/data.vbt diff --git a/src/mainboard/yanling/yl_kbr6l/devicetree.cb b/src/mainboard/yanling/yl_kbr6l/devicetree.cb new file mode 100644 index 0000000..b57ab96 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/devicetree.cb @@ -0,0 +1,278 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "SsicPortEnable" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "SkipExtGfxScan" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # TODO: Check why protectli used them and WiFi won't work + # for me if I set them -> err: lost pci device + # Enable RP 9 CLKREQ# support + #register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + #register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_COREBOOT + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 5914 - Host Bridge + device pci 02.0 on end # 8086 5917 - Integrated Graphics Device + device pci 04.0 off end # 8086 ???? - SA thermal subsystem + device pci 05.0 off end # 8086 ???? - SA IMGU + device pci 08.0 off end # 8086 ???? - Gaussian Mixture Model + device pci 13.0 off end # 8086 9d35 - Integrated Sensor Hub + device pci 14.0 on end # 8086 9d2f - USB xHCI + device pci 14.1 off end # 8086 9d30 - USB xDCI (OTG) + device pci 14.2 off end # 8086 9d31 - Thermal Subsystem + device pci 14.3 off end # 8086 9d32 - Camera I/O Host Controller + device pci 15.0 off end # 8086 9d60 - I2C #0 + device pci 15.1 off end # 8086 9d61 - I2C #1 + device pci 15.2 off end # 8086 9d62 - I2C #2 + device pci 15.3 off end # 8086 9d63 - I2C #3 + device pci 16.0 on end # 8086 9d3a - Management Engine Interface 1 + device pci 16.1 off end # 8086 9d3b - Management Engine Interface 2 + device pci 16.2 off end # 8086 9d3c - Management Engine IDE-Redirection + device pci 16.3 off end # 8086 9d3d - Management Engine KT Redirection + device pci 16.4 off end # 8086 9d3e - Management Engine Interface 3 + device pci 17.0 on end # 8086 9d03 - SATA + device pci 19.0 off end # 8086 9d66 - UART #2 + device pci 19.1 off end # 8086 9d65 - I2C #5 + device pci 19.2 off end # 8086 9d64 - I2C #4 + device pci 1c.0 on end # 8086 9d10 - PCI Express Port 1 + device pci 1c.1 on end # 8086 9d11 - PCI Express Port 2 + device pci 1c.2 on end # 8086 9d12 - PCI Express Port 3 + device pci 1c.3 on end # 8086 9d13 - PCI Express Port 4 + device pci 1c.4 on end # 8086 9d14 - PCI Express Port 5 + device pci 1c.5 on end # 8086 9d15 - PCI Express Port 6 + device pci 1c.6 off end # 8086 9d16 - PCI Express Port 7 + device pci 1c.7 off end # 8086 9d17 - PCI Express Port 8 + device pci 1d.0 on # 8086 9d18 - PCI Express Port 9 - WiFi + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" + end + device pci 1d.1 off end # 8086 9d19 - PCI Express Port 10 + device pci 1d.2 off end # 8086 9d1a - PCI Express Port 11 + device pci 1d.3 off end # 8086 9d1b - PCI Express Port 12 + device pci 1e.0 off end # 8086 9d27 - UART #0 + device pci 1e.1 off end # 8086 9d28 - UART #1 + device pci 1e.2 off end # 8086 9d29 - GSPI #0 + device pci 1e.3 off end # 8086 9d2a - GSPI #1 + device pci 1e.4 off end # 8086 9d2b - eMMC + device pci 1e.5 off end # 8086 ???? - SDIO + device pci 1e.6 off end # 8086 9d2d = SDXC + device pci 1f.0 on # 8086 9d4e - LPC Controller + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end # LPC Interface + device pci 1f.1 on end # 8086 9d20 - P2SB + device pci 1f.2 on end # 8086 9d21 - Power Management Controller + device pci 1f.3 off end # 8086 9d71 - Intel HDA + device pci 1f.4 on end # 8086 9d23 - SMBus + device pci 1f.5 off end # 8086 9d24 - PCH SPI + device pci 1f.6 off end # 8086 9d25 - GbE + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/yanling/yl_kbr6l/dsdt.asl b/src/mainboard/yanling/yl_kbr6l/dsdt.asl new file mode 100644 index 0000000..3de4e26 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads new file mode 100644 index 0000000..0e0f4f8 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/yanling/yl_kbr6l/gpio.h b/src/mainboard/yanling/yl_kbr6l/gpio.h new file mode 100644 index 0000000..7ec5a8a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gpio.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/yanling/yl_kbr6l/ramstage.c b/src/mainboard/yanling/yl_kbr6l/ramstage.c new file mode 100644 index 0000000..9518b1d --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchPort61hEnable = 1; + params->CdClock = 3; +} diff --git a/src/mainboard/yanling/yl_kbr6l/romstage.c b/src/mainboard/yanling/yl_kbr6l/romstage.c new file mode 100644 index 0000000..2b68e1a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a Gerrit-Change-Number: 48769 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: util/amdfwtool: clean up Makefile, Makefile.inc
by Idwer Vollering (Code Review) 07 Aug '23

07 Aug '23

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49086 ) Change subject: util/amdfwtool: clean up Makefile, Makefile.inc ...................................................................... util/amdfwtool: clean up Makefile, Makefile.inc Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: Ia16af046acdc68c176b1c4ff434518a5f8f8bf9e --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/49086/1 diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 58606e3..00e6d59 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -9,7 +9,7 @@ $(TARGET): $(OBJ) - $(CC) $(OBJ) $(LDFLAGS) -o $@ + $(CC) $(OBJ) -o $@ %.o: %.c $(HEADER) $(CC) $(CFLAGS) -c -o $@ $< diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index e794ed9..06a17f3 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -2,10 +2,8 @@ amdfwtoolobj = amdfwtool.o data_parse.o -AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow - $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) - $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(HOSTCC) $(CFLAGS) -c -o $@ $< $(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) printf " AMDFWTOOL\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/49086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia16af046acdc68c176b1c4ff434518a5f8f8bf9e Gerrit-Change-Number: 49086 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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