coreboot-gerrit October 2021

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Change in coreboot[master]: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/ec.h: https://review.coreboot.org/c/coreboot/+/58060/comment/01de80db_23d88dc6 PS1, Line 36: /* Returns data role and type of device connected */ Please add the comment to the now static function. -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:59:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Update some APIs
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58058 ) Change subject: src/ec/google/chromeec: Update some APIs ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58058/comment/66314210_27fbd4dc PS1, Line 7: some some PD and DisplayPort https://review.coreboot.org/c/coreboot/+/58058/comment/61256cb8_a9aac022 PS1, Line 9: Update google_chromeec_pd_get_amode() to return bitmask. Update : google_chromeec_wait_for_displayport() to handle the updated return : value of google_chromeec_pd_get_amode(). Drop : google_chromeec_pd_get_amode() from ec.h and make it static because : it's not used outside of ec.c Please format this as a list. Even better, please make one commit per change. -- To view, visit https://review.coreboot.org/c/coreboot/+/58058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Gerrit-Change-Number: 58058 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:58:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Modify google_chromeec_usb_pd_control()
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58057 ) Change subject: src/ec/google/chromeec: Modify google_chromeec_usb_pd_control() ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58057/comment/ea9180e0_8d8d6f9d PS1, Line 8: Please introduce the topic, by saying what cable types there are, and why this information is necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/58057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Gerrit-Change-Number: 58057 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:54:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Add APIs for USB-C DP ALT mode
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang, Brandon Breitenstein, Curtis Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add APIs for USB-C DP ALT mode ...................................................................... Patch Set 13: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57138/comment/85974338_4854a057 PS13, Line 10: and API to wait for DP HPD event Please add a dot/period at the end. https://review.coreboot.org/c/coreboot/+/57138/comment/44ccc094_60df5f84 PS13, Line 11: Please elaborate, why 100 ms delay steps are used. Please add the output of the new messages from your test board. File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/57138/comment/5c15df6c_8d120740 PS13, Line 1674: mdelay(100); 100 ms sounds excessive for coreboot’s normal execution time. -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 13 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:53:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 28: (6 comments) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/c7282bd9_37b9b889 PS25, Line 171: } > }; Done File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/12654ebb_3f34749b PS24, Line 159: type_c_port_info_table_entry > `type_c_info` should work? Done https://review.coreboot.org/c/coreboot/+/57069/comment/a61bf12b_17acc48f PS24, Line 164: cb_type_c_info > Now that you have implemented the suggestion in https://review.coreboot.org/c/coreboot/+/57069/23.. […] Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/da39ecc0_6f5e1310 PS25, Line 439: u32 > uint32_t Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/6c0cea50_87a2e05b PS24, Line 424: > I think you can include coreboot_tables.h directly in chip.h and drop the enum definitions in chip. […] Done https://review.coreboot.org/c/coreboot/+/57069/comment/121e20f6_091a92cc PS24, Line 443: struct lb_type_c_info { : uint32_t tag; : uint32_t size; : struct type_c_port_info_table_entry type_c_info; : }; > This is what `conn_get_cbmem_buffer()` would look like: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 28 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: switch to common GNVS
by Frans Hendriks (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57946 ) Change subject: soc/intel/skylake: switch to common GNVS ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Gerrit-Change-Number: 57946 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:42:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Set GNVS DPTE via devicetree
by Frans Hendriks (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57988 ) Change subject: soc/intel/braswell: Set GNVS DPTE via devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Gerrit-Change-Number: 57988 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:41:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 12: (5 comments) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/f81304cd_28bc16ba PS5, Line 115: mux = pmc->link_list->children; > > I was seeing .final being called after each port was registered. […] Done File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/9400db5d_72077633 PS7, Line 99: { > Oh right sorry forgot about that one 😊 putting port_count there in the struct makes sense. Done https://review.coreboot.org/c/coreboot/+/57345/comment/fc7a4ab4_d18a9007 PS7, Line 104: > ``` […] Done File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/55ad2470_e246127f PS8, Line 28: lb_type_c_info > `type_c_info` should be fine. We don't need lb_type_c_info. Done https://review.coreboot.org/c/coreboot/+/57345/comment/c1293509_0cb850d6 PS8, Line 44: == > >=? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:30:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#12). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Cq-Depend: chromium:57069 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 --- M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c 2 files changed, 69 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Furquan Shaikh (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Nick Vaccaro. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 28: (4 comments) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/5b80b410_d068fc4d PS26, Line 173: struct cb_type_c_info { This is not needed as well. File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/57069/comment/bae16f03_16c3e5cb PS26, Line 153: typec_orientation type_c_orientation. However, the last line of the comment might not be necessary as this comment already is added to type_c_port_info. File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/57069/comment/4d6ad2da_b67b38e4 PS26, Line 251: get_cbmem_addr (void *) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/d0ebd165_adbe0a66 PS27, Line 431: enum type_c_orientation { You will have to pull in the change to src/drivers/intel/pmc_mux/conn/chip.h into this CL, else compilation would fail for volteer. -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 28 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 05:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021