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Change subject: soc/intel/baytrail: Set GNVS DPTE via devicetree
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57986/comment/f7f63e4f_db05ee55
PS1, Line 10: field, as newer Intel platforms do.
How did you test this ?
Patchset:
PS1:
How did you test this
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Change subject: soc/intel/braswell: Set GNVS DPTE via devicetree
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57988/comment/873de63d_9930cba4
PS1, Line 10: field, as newer Intel platforms do.
Please, share test results.
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Change subject: mb/google/brya/variants/kano: Correct MIPI camera info
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/58048/comment/29e9196e_52dbf8e1
PS1, Line 323: 0x15752A00
> `36 * MHz` […]
Done. Should be 360 * MHz, and it does the job.
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57345
to look at the new patch set (#10).
Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
......................................................................
driver/intel/pmc_mux/conn: Add type-c port info to cbmem
This change adds type-c port information for USB type-c ports to cbmem.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
---
M src/drivers/intel/pmc_mux/conn/chip.h
M src/drivers/intel/pmc_mux/conn/conn.c
2 files changed, 69 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/10
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57069
to look at the new patch set (#26).
Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully. Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
---
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
M src/commonlib/include/commonlib/cbmem_id.h
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
6 files changed, 79 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/26
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Change subject: sc7280: Add SHRM firmware support
......................................................................
Patch Set 76: -Code-Review
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Change subject: sc7280: Add SHRM firmware support
......................................................................
Patch Set 76:
(1 comment)
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49392/comment/ca26676a_a1c4c8cf
PS76, Line 110: none
> Why no compression?
Good point. Please add $(CBFS_PRERAM_COMPRESS_FLAG)
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Change subject: util/cbfstool: Add support for ARM64 UefiPayload
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58055/comment/9271df4c_59f860a9
PS2, Line 9: To support ARM SystemReady.
> Please use complete sentences.
Done
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