coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
by Rex-BC Chen (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Jg Daolongzhu, Hung-Te Lin. Hello Hung-Te Lin, Jg Daolongzhu, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58053 to look at the new patch set (#3). Change subject: soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed ...................................................................... soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed 1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/d… BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 --- M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/mainboard.c M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 7 files changed, 340 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58053/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Gerrit-Change-Number: 58053 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: add debug dump for ltiming and clock_div
by Rex-BC Chen (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58074 ) Change subject: soc/mediatek: add debug dump for ltiming and clock_div ...................................................................... soc/mediatek: add debug dump for ltiming and clock_div ltiming and clock_div are not support for MT8173, so we separate them to weak function: mtk_i2c_dump_more_info() Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7 --- M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8195/i2c.c 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58074/1 diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index ec9b797..94e5fcd 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -135,3 +135,9 @@ mtk_i2c_speed_init(bus); mtk_i2c_set_gpio_pinmux(bus); } + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { + printk(BIOS_ERR, "LTIMING %x\nCLK_DIV %x\n", + read32(&regs->ltiming), + read32(&regs->clock_div)); +} diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index 572c280..bd629ce 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -181,3 +181,9 @@ mtk_i2c_speed_init(bus); mtk_i2c_set_gpio_pinmux(bus); } + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { + printk(BIOS_ERR, "LTIMING %x\nCLK_DIV %x\n", + read32(&regs->ltiming), + read32(&regs->clock_div)); +} diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c index a0d36b3..2de3c4d 100644 --- a/src/soc/mediatek/mt8195/i2c.c +++ b/src/soc/mediatek/mt8195/i2c.c @@ -356,3 +356,9 @@ mtk_i2c_speed_init(bus, speed); mtk_i2c_set_gpio_pinmux(bus); } + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { + printk(BIOS_ERR, "LTIMING %x\nCLK_DIV %x\n", + read32(&regs->ltiming), + read32(&regs->clock_div)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7 Gerrit-Change-Number: 58074 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
by Rex-BC Chen (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, Jg Daolongzhu, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58053 to look at the new patch set (#2). Change subject: soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed ...................................................................... soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed 1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/d… BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 --- M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/mainboard.c M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 7 files changed, 341 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58053/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Gerrit-Change-Number: 58053 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/kano: Correct MIPI camera info
by Jim Lai (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sugnan Prabhu S, Andy Yeh, Karthik Ramasubramanian. Jim Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58048 ) Change subject: mb/google/brya/variants/kano: Correct MIPI camera info ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58048/comment/5e3cc844_2bcdb588 PS2, Line 7: mb/google/brya/variants/kano: Correct MIPI camera info > Not only the CIO port information needs correction, but also other fields, i.e. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Gerrit-Change-Number: 58048 Gerrit-PatchSet: 3 Gerrit-Owner: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:45:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jim Lai <jim.lai(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/kano: Correct MIPI camera info
by Jim Lai (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sugnan Prabhu S, Andy Yeh, Karthik Ramasubramanian. Jim Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58048 ) Change subject: mb/google/brya/variants/kano: Correct MIPI camera info ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58048/comment/58878564_598f321e PS2, Line 7: mb/google/brya/variants/kano: Correct MIPI camera info > Maybe: […] Not only the CIO port information needs correction, but also other fields, i.e. HID and Link Freq https://review.coreboot.org/c/coreboot/+/58048/comment/361415f2_756a3d8d PS2, Line 9: Correct OVTI2740 information for Kano > …, which is connected to port 1 instead of 2. Done https://review.coreboot.org/c/coreboot/+/58048/comment/593590c9_78a127f0 PS2, Line 12: TEST=Build and boot on Kano > What didn’t work before, and what does work now? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Gerrit-Change-Number: 58048 Gerrit-PatchSet: 3 Gerrit-Owner: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/kano: Correct MIPI camera info
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Sugnan Prabhu S, Andy Yeh, Jim Lai, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58048 ) Change subject: mb/google/brya/variants/kano: Correct MIPI camera info ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58048/comment/da3bae95_b302763c PS2, Line 7: mb/google/brya/variants/kano: Correct MIPI camera info Maybe: > Correct MIPI camera CIO port https://review.coreboot.org/c/coreboot/+/58048/comment/2929b903_4e7261c7 PS2, Line 9: Correct OVTI2740 information for Kano …, which is connected to port 1 instead of 2. https://review.coreboot.org/c/coreboot/+/58048/comment/5da5e457_5511a55c PS2, Line 12: TEST=Build and boot on Kano What didn’t work before, and what does work now? -- To view, visit https://review.coreboot.org/c/coreboot/+/58048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Gerrit-Change-Number: 58048 Gerrit-PatchSet: 2 Gerrit-Owner: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: Jim Lai <jim.lai(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Always enable SpeedStep
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57669 ) Change subject: soc/intel/denverton_ns: Always enable SpeedStep ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57669/comment/11607574_6871ed8b PS2, Line 12: > Оperating system cannot change the frequency. Clock is stuck at 800MHz. […] Please add that to the commit message. Also, can the OS lower the speed again to 800 MHz? Commit Message: https://review.coreboot.org/c/coreboot/+/57669/comment/461ddfff_fcf3f36a PS3, Line 9: When SpeedStep is disabled on an Atom C3538, the maximum CPU clock : speed is limited to 800 MHz. This is the symptom. Please elaborate, why `enable_turbo()` seems to fail, causing the if condition to fail. -- To view, visit https://review.coreboot.org/c/coreboot/+/57669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Gerrit-Change-Number: 57669 Gerrit-PatchSet: 3 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:06:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Дмитрий Понаморев <dponamorev(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add SHRM firmware support
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: Add SHRM firmware support ...................................................................... Patch Set 76: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49392/comment/885891a0_3df8ccec PS9, Line 7: sc7280: shrm.elf loading changes > Please improve the commit message. (Same for all other commits.) […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/49392/comment/59fa33d4_55945097 PS76, Line 9: SHRM is a system hardware resource manager. : It is used to manage run time DDRSS activities. Please do not break lines after each sentence, and use the full textwidth of 75 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 76 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/tcss: Optimize Type-C DP flow
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang, Curtis Chen, Brandon Breitenstein. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize Type-C DP flow ...................................................................... Patch Set 20: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57139/comment/306614a6_66734fd9 PS20, Line 8: Please describe the problem first. https://review.coreboot.org/c/coreboot/+/57139/comment/7544f0a0_4b49f1de PS20, Line 11: Please paste the new log messages, which should be shown now, and say, what exact device you tested this with. -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 20 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:02:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Paul Menzel (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58060/comment/66b19b7f_2c295082 PS1, Line 10: static and drop from ec.h Please add a dot/period to the end of sentences. (Also other change-sets.) -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 06:00:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021