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Change subject: src/ec/google/chromeec: Add APIs for USB-C DP ALT mode
......................................................................
src/ec/google/chromeec: Add APIs for USB-C DP ALT mode
Add API to allow AP to send the command to EC to enter DP ALT mode
and API to wait for DP HPD event.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
coreboot and update your system. Boot the system you will find below
message in the coreboot log with or without USB-C display connected:
'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
2 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/57138/14
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Change subject: src/ec/google/chromeec: Update some PD and DisplayPort APIs
......................................................................
src/ec/google/chromeec: Update some PD and DisplayPort APIs
1. Update google_chromeec_pd_get_amode() to return bitmask.
2. Update google_chromeec_wait_for_displayport() to handle the
updated return value of google_chromeec_pd_get_amode().
3. Drop google_chromeec_pd_get_amode() from ec.h and make it static
because it's not used outside of ec.c.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
2 files changed, 29 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/58058/2
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Change subject: src/ec/google/chromeec: Update google_chromeec_usb_pd_control()
......................................................................
src/ec/google/chromeec: Update google_chromeec_usb_pd_control()
Add parameter `active_cable` to obtain the cable type
(active or passive) which is needed for USB-C configuration for
some SoCs (at least Intel TGL and ADL), change the function name to
google_chromeec_usb_pd_get_info() for better understanding.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
2 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/58057/2
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Change subject: include/device: Generic interface for USB-C mux operations
......................................................................
include/device: Generic interface for USB-C mux operations
Create a generic interface to allow any of the EC or other drivers
to provide set of USB-C mux operations.
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d
---
A src/include/device/usbc_mux.h
1 file changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/58002/4
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Jakub Czapiga has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56305 )
Change subject: tests: Add lib/lzmadecode-test test case
......................................................................
Abandoned
Moved to CB:57555
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58064 )
Change subject: soc/intel/common/../cse: Helper function to check CSE device `devfn` status
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/58064/comment/8a1fbaf6_352e4d0d
PS3, Line 587: printk(BIOS_WARNING, "HECI: No CSE device\n");
need one suggestion:
we are seeing this msg for all HECI devices while calling heci_finalize https://review.coreboot.org/c/coreboot/+/58040/7/src/soc/intel/alderlake/fi….
Do you see any concern or confusion, if yes, then we might to add slot and function number to clarify which device is not there.
HECI: No CSE device
HECI: No CSE device
HECI: No CSE device
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58074 )
Change subject: soc/mediatek: add debug dump for ltiming and clock_div
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/mt8183/i2c.c:
https://review.coreboot.org/c/coreboot/+/58074/comment/079fb8d4_e4a949e4
PS3, Line 141: ERR
INFO or DEBUG. Same below.
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Perform `heci_finalize` prior booting to OS
......................................................................
soc/intel/alderlake: Perform `heci_finalize` prior booting to OS
`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.
Note: coreboot might skip calling `heci_finalize()` if
SOC_INTEL_CSE_SET_EOP Kconfig is not selected.
TEST=Verified D0i3 bit is set for all HECI devices prior booting to OS.
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
---
M src/soc/intel/alderlake/finalize.c
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58040/7
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