coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

1 participants
2457 discussions

Change in coreboot[master]: ec/google/chromeec: Add support for USB Type-C alternate mode control
by John Zhao (Code Review) 09 Jun '23

09 Jun '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40424 ) Change subject: ec/google/chromeec: Add support for USB Type-C alternate mode control ...................................................................... ec/google/chromeec: Add support for USB Type-C alternate mode control PMC mux control can be used for swapping the USB data role and for setting connector to act in alternate modes. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along with PMC mux control. Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40424/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 3e9b773..a8d859f 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -56,4 +56,117 @@ { Return (0xB) } + + Device (USBC) + { + Name (_HID, "GOOG0014") + Name (_DDN, "ChromeOS Embedded Controller USB Type-C Control") + + /* + * Each connector shall have its own ACPI device entry + * (node), under the actual interface device. + */ + Device (CON0) + { + Name (_ADR, 0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON0 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + } + }) + + /* + * Each supported alternate mode. Use _STA() to disable/enable + * them. + */ + + /* Thunderbolt 3 alternate mode */ + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0x8087 }, + Package () { "vdo", 1 }, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Display Port alternate mode */ + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb-role-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "mode-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "orientation-switch", + \_SB.PCI0.PMC.MUX.CON1 }, + Package () { "power-role", "dual" }, + Package () { "data-role", "dual" }, + }, + }) + + Device (TBT3) + { + Name (_ADR, 0) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () {"svid", 0x8087}, + Package () {"vdo", 1}, + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device (DP) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "svid", 0xff01 }, + Package () { "vdo", 0x1c46 }, + } + }) + } + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c872537d9c633f8eb4238fd9b023577c4570a5a Gerrit-Change-Number: 40424 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: sb/intel/common/smihandler.c: add mainboard intrusion detection handler
by Michał Żygowski (Code Review) 09 Jun '23

09 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40348 ) Change subject: sb/intel/common/smihandler.c: add mainboard intrusion detection handler ...................................................................... sb/intel/common/smihandler.c: add mainboard intrusion detection handler Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b --- M src/southbridge/intel/common/smihandler.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40348/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..b8ea9a2 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -424,6 +424,9 @@ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); + } else if (tco_sts & (1 << 16)) { /* INTRUDER */ + mainboard_smi_intruder(tco_sts); + printk(BIOS_DEBUG, "TCO Intruder.\n"); } else { dump_tco_status(tco_sts); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c30c9b8fbf7dbc0327155863cfe62c51bcbc1b Gerrit-Change-Number: 40348 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH
by Edward O'Callaghan (Code Review) 09 Jun '23

09 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40517 ) Change subject: mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH ...................................................................... mb/google/hatch: Toggle on EC_ENABLE_LID_SWITCH Unfortunately EC_ENABLE_LID_SWITCH needs to be toggled on to enable the 'PNP0C0D' ASL device on otherwise the wake pin will not be noticed by the kernel. This patch works around that issue for Puff and Puff variants. BUG=b:152913653 BRANCH=none TEST=builds Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/duffy/include/variant/ec.h M src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40517/1 diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 5e2043f..9f9b4a9 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -49,6 +49,8 @@ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ +/* Enable LID switch such that the wake pin works for the EC */ +#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f40afb7aa62510312164d3a62d44f4b2b911700 Gerrit-Change-Number: 40517 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: util/inteltool: print all Lewisburg GPIO registers
by Maxim Polyakov (Code Review) 09 Jun '23

09 Jun '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40014 ) Change subject: util/inteltool: print all Lewisburg GPIO registers ...................................................................... util/inteltool: print all Lewisburg GPIO registers These changes are in accordance with the documentation: [*] "Intel C620 Series Chipset Platform Controller Hub", datasheet. May 2019. Document Number: 336067-007US Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/gpio_names/lewisburg.h 1 file changed, 220 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40014/1 diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h index 4d59177..d2aba7a 100644 --- a/util/inteltool/gpio_names/lewisburg.h +++ b/util/inteltool/gpio_names/lewisburg.h @@ -4,10 +4,190 @@ #include "gpio_groups.h" #include "sunrise.h" +static const struct gpiocom_register lewisburg_community0_abf_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_A_0"}, + {0x24, "PAD_OWN_GPP_A_1"}, + {0x28, "PAD_OWN_GPP_A_2"}, + {0x2C, "PAD_OWN_GPP_B_0"}, + {0x30, "PAD_OWN_GPP_B_1"}, + {0x34, "PAD_OWN_GPP_B_2"}, + {0x38, "PAD_OWN_GPP_F_0"}, + {0x3C, "PAD_OWN_GPP_F_1"}, + {0x40, "PAD_OWN_GPP_F_2"}, + {0x60, "PADCFGLOCK_GPP_A"}, + {0x64, "PADCFGLOCKTX_GPP_A"}, + {0x68, "PADCFGLOCK_GPP_B"}, + {0x6C, "PADCFGLOCKTX_GPP_B"}, + {0x70, "PADCFGLOCK_GPP_F"}, + {0x74, "PADCFGLOCKTX_GPP_F"}, + {0x80, "HOSTSW_OWN_GPP_A"}, + {0x84, "HOSTSW_OWN_GPP_B"}, + {0x88, "HOSTSW_OWN_GPP_F"}, + {0x100, "GPI_IS_GPP_A"}, + {0x104, "GPI_IS_GPP_B"}, + {0x108, "GPI_IS_GPP_F"}, + {0x110, "GPI_IE_GPP_A"}, + {0x114, "GPI_IE_GPP_B"}, + {0x118, "GPI_IE_GPP_F"}, + {0x120, "GPI_GPE_STS_GPP_A"}, + {0x124, "GPI_GPE_STS_GPP_B"}, + {0x128, "GPI_GPE_STS_GPP_F"}, + {0x130, "GPI_GPE_EN_GPP_A"}, + {0x134, "GPI_GPE_EN_GPP_B"}, + {0x138, "GPI_GPE_EN_GPP_F"}, + {0x144, "GPI_SMI_STS_GPP_B"}, + {0x154, "GPI_SMI_EN_GPP_B"}, + {0x164, "GPI_NMI_STS_GPP_B"}, + {0x174, "GPI_NMI_EN_GPP_B"}, +}; + +static const struct gpiocom_register lewisburg_community1_cde_cfg_registers[] = { + {0x10, "PADBAR"}, + {0x13, "MISCCFG"}, + {0x23, "PAD_OWN_GPP_C_0"}, + {0x24, "PAD_OWN_GPP_C_1"}, + {0x28, "PAD_OWN_GPP_C_2"}, + {0x2C, "PAD_OWN_GPP_D_0"}, + {0x30, "PAD_OWN_GPP_D_1"}, + {0x34, "PAD_OWN_GPP_D_2"}, + {0x38, "PAD_OWN_GPP_E_0"}, + {0x3C, "PAD_OWN_GPP_E_1"}, + {0x60, "PADCFGLOCK_GPP_C_0"}, + {0x64, "PADCFGLOCKTX_GPP_C_0"}, + {0x68, "PADCFGLOCK_GPP_D_0"}, + {0x6C, "PADCFGLOCKTX_GPP_D_0"}, + {0x70, "PADCFGLOCK_GPP_E_0"}, + {0x74, "PADCFGLOCKTX_GPP_E_0"}, + {0x80, "HOSTSW_OWN_GPP_C_0"}, + {0x84, "HOSTSW_OWN_GPP_D_0"}, + {0x88, "HOSTSW_OWN_GPP_E_0"}, + {0x100, "GPI_IS_GPP_C_0"}, + {0x104, "GPI_IS_GPP_D_0"}, + {0x108, "GPI_IS_GPP_E_0"}, + {0x110, "GPI_IE_GPP_C_0"}, + {0x114, "GPI_IE_GPP_D_0"}, + {0x118, "GPI_IE_GPP_E_0"}, + {0x120, "GPI_GPE_STS_GPP_C_0"}, + {0x124, "GPI_GPE_STS_GPP_D_0"}, + {0x128, "GPI_GPE_STS_GPP_E_0"}, + {0x130, "GPI_GPE_EN_GPP_C_0"}, + {0x134, "GPI_GPE_EN_GPP_D_0"}, + {0x138, "GPI_GPE_EN_GPP_E_0"}, + {0x140, "GPI_SMI_STS_GPP_C_0"}, + {0x144, "GPI_SMI_STS_GPP_D_0"}, + {0x148, "GPI_SMI_STS_GPP_E_0"}, + {0x150, "GPI_SMI_EN_GPP_C_0"}, + {0x154, "GPI_SMI_EN_GPP_D_0"}, + {0x158, "GPI_SMI_EN_GPP_E_0"}, + {0x160, "GPI_NMI_STS_GPP_C_0"}, + {0x164, "GPI_NMI_STS_GPP_D_0"}, + {0x168, "GPI_NMI_STS_GPP_E_0"}, + {0x170, "GPI_NMI_EN_GPP_C_0"}, + {0x174, "GPI_NMI_EN_GPP_D_0"}, + {0x178, "GPI_NMI_EN_GPP_E_0"}, + {0x204, "PWMC"}, + {0x20C, "GP_SER_BLINK"}, + {0x210, "GP_SER_CMDSTS"}, + {0x214, "GP_SER_DATA"}, +}; + +static const struct gpiocom_register lewisburg_community2_gpd_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPD_0"}, + {0x24, "PAD_OWN_GPD_1"}, + {0x60, "PADCFGLOCK_GPD_0"}, + {0x64, "PADCFGLOCKTX_GPD_0"}, + {0x80, "HOSTSW_OWN_GPD_0"}, + {0x100, "GPI_IS_GPD_0"}, + {0x110, "GPI_IE_GPD_0"}, + {0x120, "GPI_GPE_STS_GPD_0"}, + {0x130, "GPI_GPE_EN_GPD_0"}, +}; + +static const struct gpiocom_register lewisburg_community3_i_cfg_registers[] = { + {0xC0, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_I_0"}, + {0x24, "PAD_OWN_GPP_I_1"}, + {0x60, "PADCFGLOCK_GPP_I_0"}, + {0x64, "PADCFGLOCKTX_GPP_I_0"}, + {0x80, "HOSTSW_OWN_GPP_I_0"}, + {0x100, "GPI_IS_GPP_I_0"}, + {0x110, "GPI_IE_GPP_I_0"}, + {0x120, "GPI_GPE_STS_GPP_I_0"}, + {0x130, "GPI_GPE_EN_GPP_I_0"}, + {0x140, "GPI_SMI_STS_GPP_I_0"}, + {0x150, "GPI_SMI_EN_GPP_I_0"}, + {0x160, "GPI_NMI_STS_GPP_I_0"}, + {0x170, "GPI_NMI_EN_GPP_I_0"}, +}; + +static const struct gpiocom_register lewisburg_community4_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_J_0"}, + {0x24, "PAD_OWN_GPP_J_1"}, + {0x28, "PAD_OWN_GPP_J_2"}, + {0x2C, "PAD_OWN_GPP_K_0"}, + {0x30, "PAD_OWN_GPP_K_1"}, + {0x60, "PADCFGLOCK_GPP_J"}, + {0x64, "PADCFGLOCKTX_GPP_J"}, + {0x68, "PADCFGLOCK_GPP_K"}, + {0x6C, "PADCFGLOCKTX_GPP_K"}, + {0x80, "HOSTSW_OWN_GPP_J"}, + {0x84, "HOSTSW_OWN_GPP_K"}, + {0x100, "GPI_IS_GPP_J"}, + {0x104, "GPI_IS_GPP_K"}, + {0x110, "GPI_IE_GPP_J"}, + {0x114, "GPI_IE_GPP_K"}, + {0x120, "GPI_GPE_STS_GPP_J"}, + {0x124, "GPI_GPE_STS_GPP_K"}, + {0x130, "GPI_GPE_EN_GPP_J"}, + {0x134, "GPI_GPE_EN_GPP_K"}, +}; + +static const struct gpiocom_register lewisburg_community5_jk_cfg_registers[] = { + {0x0C, "PADBAR"}, + {0x10, "MISCCFG"}, + {0x20, "PAD_OWN_GPP_G_0"}, + {0x24, "PAD_OWN_GPP_G_1"}, + {0x28, "PAD_OWN_GPP_G_2"}, + {0x2C, "PAD_OWN_GPP_H_0"}, + {0x30, "PAD_OWN_GPP_H_1"}, + {0x34, "PAD_OWN_GPP_H_2"}, + {0x38, "PAD_OWN_GPP_L_0"}, + {0x3C, "PAD_OWN_GPP_L_1"}, + {0x40, "PAD_OWN_GPP_L_2"}, + {0x60, "PADCFGLOCK_GPP_G"}, + {0x64, "PADCFGLOCKTX_GPP_G"}, + {0x68, "PADCFGLOCK_GPP_H"}, + {0x6C, "PADCFGLOCKTX_GPP_H"}, + {0x70, "PADCFGLOCK_GPP_L"}, + {0x74, "PADCFGLOCKTX_GPP_L"}, + {0x80, "HOSTSW_OWN_GPP_G"}, + {0x84, "HOSTSW_OWN_GPP_H"}, + {0x88, "HOSTSW_OWN_GPP_L"}, + {0x100, "GPI_IS_GPP_G"}, + {0x104, "GPI_IS_GPP_H"}, + {0x108, "GPI_IS_GPP_L"}, + {0x110, "GPI_IE_GPP_G"}, + {0x114, "GPI_IE_GPP_H"}, + {0x118, "GPI_IE_GPP_L"}, + {0x120, "GPI_GPE_STS_GPP_G"}, + {0x124, "GPI_GPE_STS_GPP_H"}, + {0x128, "GPI_GPE_STS_GPP_L"}, + {0x130, "GPI_GPE_EN_GPP_G"}, + {0x134, "GPI_GPE_EN_GPP_H"}, + {0x138, "GPI_GPE_EN_GPP_L"}, +}; + static const char *const lewisburg_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_,A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_,A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_,A2", "LAD1", "n/a", "ESPI_IO1", "GPP_A3", "LAD2", "n/a", "ESPI_IO2", "GPP_A4", "LAD3", "n/a", "ESPI_IO3", "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", @@ -384,10 +564,12 @@ }; static const struct gpio_community lewisburg_community0_abf = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), - .groups = lewisburg_community0_abf_groups, + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .groups = lewisburg_community0_abf_groups, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .cfg_registers = lewisburg_community0_abf_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community0_abf_cfg_registers), }; static const struct gpio_group *const lewisburg_community1_cde_groups[] = { @@ -397,10 +579,12 @@ }; static const struct gpio_community lewisburg_community1_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), - .groups = lewisburg_community1_cde_groups, + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .groups = lewisburg_community1_cde_groups, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .cfg_registers = lewisburg_community1_cde_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community1_cde_cfg_registers), }; static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { @@ -408,10 +592,12 @@ }; static const struct gpio_community lewisburg_community2_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), - .groups = lewisburg_community2_gpd_groups, + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .groups = lewisburg_community2_gpd_groups, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .cfg_registers = lewisburg_community2_gpd_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community2_gpd_cfg_registers), }; static const struct gpio_group *const lewisburg_community3_i_groups[] = { @@ -419,10 +605,12 @@ }; static const struct gpio_community lewisburg_community3_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), - .groups = lewisburg_community3_i_groups, + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .groups = lewisburg_community3_i_groups, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .cfg_registers = lewisburg_community3_i_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community3_i_cfg_registers), }; static const struct gpio_group *const lewisburg_community4_jk_groups[] = { @@ -431,10 +619,12 @@ }; static const struct gpio_community lewisburg_community4_jk = { - .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0xab, - .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), - .groups = lewisburg_community4_jk_groups, + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .groups = lewisburg_community4_jk_groups, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), }; static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { @@ -444,10 +634,13 @@ }; static const struct gpio_community lewisburg_community5_ghl = { - .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x11, - .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), - .groups = lewisburg_community5_ghl_groups, + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .groups = lewisburg_community5_ghl_groups, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .cfg_registers = lewisburg_community4_jk_cfg_registers, + .cfg_registers_count = ARRAY_SIZE(lewisburg_community4_jk_cfg_registers), + }; static const struct gpio_community *const lewisburg_communities[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/40014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e4e3884f7b087c08325597650b2f2fd5a6a62f Gerrit-Change-Number: 40014 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: util/scripts/ucode_h_to_bin.sh: Fix `shellcheck` warning
by Alex Thiessen (Code Review) 09 Jun '23

09 Jun '23

Alex Thiessen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40945 ) Change subject: util/scripts/ucode_h_to_bin.sh: Fix `shellcheck` warning ...................................................................... util/scripts/ucode_h_to_bin.sh: Fix `shellcheck` warning The attempted fix in commit 21530bd4 "util/scripts/ucode_h_to_bin.sh: Drop disruptive quotes" triggers a `shellcheck` warning because a string is being split implicitly: In util/scripts/ucode_h_to_bin.sh line 52: for UCODE in ${@:2}; do ^-- SC2068: Double quote array expansions to avoid re-splitting elements. Reference: https://github.com/koalaman/shellcheck/wiki/SC2068 Also, accidental globbing will occur, e.g. when a file name contains an asterisk or a question mark. The underlying reason for this weirdness is this script's interface which is neither _usual_ nor well-documented (the code accepts things which don't adhere to the interface, e.g. multiple file lists or whole directory names). Make the split explicit by introducing a separate array variable containing the strings, split on spaces. This also will not trigger globbing. Change-Id: I5fb7d0370ca46e8eb850449612d201d5d164fb6a Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> --- M util/scripts/ucode_h_to_bin.sh 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/40945/1 diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index cb403a4..1072bb9 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -49,7 +49,9 @@ fi } -for UCODE in ${@:2}; do +IFS=' ' read -r -a UCODE_PARAM <<< "${@:2}" + +for UCODE in "${UCODE_PARAM[@]}"; do if [ -d "$UCODE" ]; then for f in "$UCODE/"*.inc do -- To view, visit https://review.coreboot.org/c/coreboot/+/40945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fb7d0370ca46e8eb850449612d201d5d164fb6a Gerrit-Change-Number: 40945 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/deltaur: Update ISH firmware name
by Anil Kumar K (Code Review) 09 Jun '23

09 Jun '23

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40537 ) Change subject: mb/google/deltaur: Update ISH firmware name ...................................................................... mb/google/deltaur: Update ISH firmware name Bug=b:153847811 Branch=master Test=make build successfull Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ic701f224452731e43207836882d649580b76db3a --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/40537/1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index e0b3d50..831c1c4 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -175,7 +175,13 @@ device pci 11.2 off end # UART5 device pci 11.3 off end # UART6 - device pci 12.0 on end # ISH + device pci 12.0 on + chip drivers/intel/ish + register "firmware_name" = ""deltaur_ish.bin"" + device generic 0 on end + end + end # ISH + device pci 12.6 off end # GSPI #2 device pci 13.0 off end # GSPI #3 device pci 13.1 off end # GSPI #4 -- To view, visit https://review.coreboot.org/c/coreboot/+/40537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic701f224452731e43207836882d649580b76db3a Gerrit-Change-Number: 40537 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: Documentation/soc/intel: Add documentation for MCU update
by Varshit B Pandya (Code Review) 09 Jun '23

09 Jun '23

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34657 ) Change subject: Documentation/soc/intel: Add documentation for MCU update ...................................................................... Documentation/soc/intel: Add documentation for MCU update Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- A Documentation/soc/intel/ucode_update/Flash_Layout.PNG A Documentation/soc/intel/ucode_update/microcode_update_model.md 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34657/1 diff --git a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG new file mode 100644 index 0000000..ac18977 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG Binary files differ diff --git a/Documentation/soc/intel/ucode_update/microcode_update_model.md b/Documentation/soc/intel/ucode_update/microcode_update_model.md new file mode 100644 index 0000000..e2d7f35 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/microcode_update_model.md @@ -0,0 +1,43 @@ +# Microcode update mechanism for devices in field + +## Introduction + +Processor microcode (MCU) is akin to processor firmware. Processors may need updates to their microcode to operate correctly. These updates fix bugs/errata that can cause anything from incorrect processing, to code and data corruption, and system lockups. + +##Problem Statement + +As per chrome design, any field updatable FW has to be first verified by vboot (chrome root of trust - CROT) before it is allowed to run on the system. CROT executes on the CPU, hence FW such as MCU loaded before the CPU reset cannot be verified before it actually gets loaded. As a result today Chromebooks are not able to apply MCU in the field. This proposal tries to address the issue + +Prior to CPU reset, the CPU HW locates the FIT table from the storage, walks over the FIT table and picks-up the MCU that matches the CPU Family, Model, Stepping and PLATFORM ID with the highest revision ID. CPU verifies that MCU is signed by Intel and once verification is successful, it attempts to load the MCU. + +However FIT does not contain any fall back mechanism. If one MCU loading fails for whatever reason, it drops the further loading process and moves on to CPU reset. While it is fairly a remote chance, in case of any failure to load MCU which cause hang like situations before CPU reset, a platform based mechanism can be put in place to enter recovery mode. As detailed below, if we are using BUC register based top swap implementation, then an RTC reset may be required to clear top swap bit. + +## Design Proposal + +The proposal relies on the following Intel SoC features: + +1. Top swap, which enables the BIOS to have 2 bootblocks and bot from either using a RTC backed Top swap control bit in BUC register. +2. Firmware Interface Table (FIT) based MCU loading. + +The idea is to have 2 bootblocks, each having its own FIT table. The FIT in one of them will be configured to point to an MCU in RO firmware, and the FIT in other one will point to a fixed flash region (aka MCU staging area), which will contain an MCU from RW firmware. + +Top-swap feature of Intel CPUs, will be used to switch between 2 bootblocks, based on the bootmode i.e., recovery or normal/developer mode. + +Coreboot will keep the MCU staging area updated with the MCU from the currently selected RW firmware. + +## Implementation Details + +1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their own FIT tables. Both bootblocks will be in the RO section. + a. bb_ro_ucode contains a FIT which has pointer to MCU (microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. + b. bb_staged_ucode is identical to bb_ro_ucode but contains a FIT which has pointer to a MCU that will reside in a staging area. +2. Create a MCU staging area + a. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for that SoC. This is a RW region just lke the RW_MRC_CACHE. + b. MCU from RW-A/RW-B will be copied to this region during boot. + c. A Flash Protected Range (FPR) should be configured to write protect this MCU Staging area. + d. bb_staged_ucode FIT points to the MCU in this staging area. +3. The resulting flash layout is shown below, +**Flash Layout** +![Flash Layout][flash_layout] +[flash_layout]: Flash_Layout.PNG + +4. The proposed design uses the PCR register based control for top-swap -- To view, visit https://review.coreboot.org/c/coreboot/+/34657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Gerrit-Change-Number: 34657 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: devicetree: Check destination size while flattening
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41201 ) Change subject: devicetree: Check destination size while flattening ...................................................................... devicetree: Check destination size while flattening * Check that destination buffer doesn't overflow while flattening * Add 128 bytes to the requested space for the FDT in fit_payload.c Change-Id: Ia8300df1abd012d286c10d12cc99bdc05c2710d8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/include/device_tree.h M src/lib/device_tree.c M src/lib/fit_payload.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c 4 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41201/1 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index bd0d151..ddfb6e5 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -116,8 +116,8 @@ /* Figure out how big a device tree would be if it were flattened. */ uint32_t dt_flat_size(const struct device_tree *tree); -/* Flatten a device tree into the buffer pointed to by dest. */ -void dt_flatten(const struct device_tree *tree, void *dest); +/* Flatten a device tree into the buffer with size len pointed to by dest. */ +void dt_flatten(const struct device_tree *tree, void *dest, size_t len); void dt_print_node(const struct device_tree_node *node); /* Read #address-cells and #size-cells properties from a node. */ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index cb81d32..5d4b2b0 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -421,14 +421,21 @@ *strings_start = dstrings; } -void dt_flatten(const struct device_tree *tree, void *start_dest) +void dt_flatten(const struct device_tree *tree, void *start_dest, size_t len) { uint8_t *dest = (uint8_t *)start_dest; + uint8_t *dest_max = ((uint8_t *)start_dest) + len; + + if ((dest + tree->header_size) > dest_max) + goto err; memcpy(dest, tree->header, tree->header_size); struct fdt_header *header = (struct fdt_header *)dest; dest += tree->header_size; + if ((dest + sizeof(uint64_t) * 2) > dest_max) + goto err; + struct device_tree_reserve_map_entry *entry; list_for_each(entry, tree->reserve_map, list_node) dt_flatten_map_entry(entry, (void **)&dest); @@ -439,6 +446,9 @@ uint32_t strings_size = 0; dt_flat_node_size(tree->root, &struct_size, &strings_size); + if ((dest + struct_size) > dest_max) + goto err; + uint8_t *struct_start = dest; header->structure_offset = htobe32(dest - (uint8_t *)start_dest); header->structure_size = htobe32(struct_size); @@ -447,6 +457,9 @@ *((uint32_t *)dest) = htobe32(FDT_TOKEN_END); dest += sizeof(uint32_t); + if ((dest + strings_size) > dest_max) + goto err; + uint8_t *strings_start = dest; header->strings_offset = htobe32(dest - (uint8_t *)start_dest); header->strings_size = htobe32(strings_size); @@ -456,6 +469,11 @@ (void **)&strings_start); header->totalsize = htobe32(dest - (uint8_t *)start_dest); + + return; +err: + printk(BIOS_CRIT, "%s: Buffer overflowed (used %d, max %zd) while flattening devicetree\n", + __func__, (dest - (uint8_t *)start_dest), len); } diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 9cf1542..1b97ad9 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -23,7 +23,7 @@ printk(BIOS_INFO, "FIT: Flattening FDT to %p\n", (void *)fdt->offset); - dt_flatten(dt, (void *)fdt->offset); + dt_flatten(dt, (void *)fdt->offset, fdt->size); prog_segment_loaded(fdt->offset, fdt->size, 0); } @@ -219,7 +219,8 @@ /* Collect infos for fit_payload_arch */ kernel.size = config->kernel->size; - fdt.size = dt_flat_size(dt); + /* Add additional space for fit_add_ramdisk() */ + fdt.size = dt_flat_size(dt) + 128; initrd.size = config->ramdisk ? config->ramdisk->size : 0; /* Invoke arch specific payload placement and fixups */ diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index c270857..3cffb97 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -96,7 +96,7 @@ return; } - dt_flatten(tree, dt); + dt_flatten(tree, dt, dt_flat_size(tree)); /* update HLS */ for (int i = 0; i < CONFIG_MAX_CPUS; i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/41201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8300df1abd012d286c10d12cc99bdc05c2710d8 Gerrit-Change-Number: 41201 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS
by Paul Menzel (Code Review) 09 Jun '23

09 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38304 ) Change subject: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS ...................................................................... emulation/qemu-i440fx: Add \_SB.PCI0.MBRS Linux 5.4.8 shows the ACPI error below. [ 0.732324] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.MBRS], AE_NOT_FOUND (20190816/dswload2-159) [ 0.732784] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20190816/psobject-220) So, add that symbol. Copied from (removed) `src/mainboard/hp/dl145_g1/dsdt.asl`. Change-Id: I0243f6a469f5addbf2f09f3aed52d1a067b22cc9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/emulation/qemu-i440fx/dsdt.asl 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38304/1 diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 9bef7d9..95b4b42 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -33,6 +33,13 @@ Scope(\_SB) { Device(PCI0) { + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + Name(_HID, EisaId("PNP0A03")) Name(_UID, 1) } -- To view, visit https://review.coreboot.org/c/coreboot/+/38304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0243f6a469f5addbf2f09f3aed52d1a067b22cc9 Gerrit-Change-Number: 38304 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo...
by David Gebski (Code Review) 09 Jun '23

09 Jun '23

David Gebski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41484 ) Change subject: Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo T420s ...................................................................... Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo T420s Borrowed text mostly from documentation for Lenovo T420. Added two images showing the pinout. Signed-off-by: Zalckos <mail(a)davidgebski.nl> Change-Id: I9fae5cfd596da144f2161ad35323cb2a6de645a9 --- A Documentation/mainboard/lenovo/t420s.md A Documentation/mainboard/lenovo/t420s_board.jpg A Documentation/mainboard/lenovo/t420s_rpi.jpg 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41484/1 diff --git a/Documentation/mainboard/lenovo/t420s.md b/Documentation/mainboard/lenovo/t420s.md new file mode 100644 index 0000000..ce848c5 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s.md @@ -0,0 +1,22 @@ +# Lenovo T420s + +## Flashing instructions +The flash IC is located at the bottom center of the mainboard. Sadly, +access to the IC is blocked by the magnesum frame, so you need to disassemble +the entire laptop and remove the mainboard. + +Below is a picture of IC on the mainboard with clip attached, and a picture of the Raspberry Pi with cables attached. In this case it's a Winbond flash chip "W25Q64.V". + +![t420s_board](t420s_board.jpg) +![t420s_rpi](t420s_rpi.jpg) + + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and +the general [flashing tutorial]. + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md + diff --git a/Documentation/mainboard/lenovo/t420s_board.jpg b/Documentation/mainboard/lenovo/t420s_board.jpg new file mode 100644 index 0000000..b99ce6e --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_board.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t420s_rpi.jpg b/Documentation/mainboard/lenovo/t420s_rpi.jpg new file mode 100644 index 0000000..e7b7626 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_rpi.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/41484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fae5cfd596da144f2161ad35323cb2a6de645a9 Gerrit-Change-Number: 41484 Gerrit-PatchSet: 1 Gerrit-Owner: David Gebski Gerrit-MessageType: newchange

3 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2020