coreboot-gerrit June 2020

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Change in coreboot[master]: soc/intel/icelake: Make CpuMpPpi implementation default for ICL
by Subrata Banik (Code Review) 05 Oct '20

05 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36839 ) Change subject: soc/intel/icelake: Make CpuMpPpi implementation default for ICL ...................................................................... soc/intel/icelake: Make CpuMpPpi implementation default for ICL TEST=Could able to build and boot ICL DE system Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/fsp_params.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36839/1 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 62c69da..448b82c 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -84,12 +84,10 @@ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) params->Usb3OverCurrentPin[i] = 0; - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - } + /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + /* TODO: Remove me as SkipMpInit is getting deprecated */ + params->SkipMpInit = 0; mainboard_silicon_init_params(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/36839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Gerrit-Change-Number: 36839 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/f2a85m_pro: Fix superio type in devicetree
by Kyösti Mälkki (Code Review) 03 Oct '20

03 Oct '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35855 ) Change subject: asus/f2a85m_pro: Fix superio type in devicetree ...................................................................... asus/f2a85m_pro: Fix superio type in devicetree The superio driver that was linked in is nct6779d but static devicetree expected symbol superio_nuvoton_nct5572d_ops. Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/35855/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index e261505..7637565 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -42,7 +42,7 @@ device pci 14.1 off end # unused device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x780e - chip superio/nuvoton/nct5572d + chip superio/nuvoton/nct6779d device pnp 2e.0 off end # FDC device pnp 2e.1 off end # LPT1 device pnp 2e.2 on # COM1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282 Gerrit-Change-Number: 35855 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
by Felix Held (Code Review) 30 Sep '20

30 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42786 ) Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ...................................................................... [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 5 files changed, 192 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8c37ef5..4282c00 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,6 +8,7 @@ select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME @@ -29,6 +30,7 @@ config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP config MAINBOARD_DIR string @@ -37,10 +39,12 @@ config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME config DEVICETREE string @@ -57,6 +61,7 @@ config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs @@ -105,5 +110,6 @@ config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME -endif # BOARD_AMD_MANDOLIN +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3f..6f51233 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000..6a9b548 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 0x1000000 { + BIOS@0x0 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000..4870a27 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON" + + register "sd_emmc_config" = "SD_EMMC_DISABLE" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 on end # AHCI + device pci 0.1 off end # Ethernet + device pci 0.2 off end # Ethernet + end + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.3 on # - D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000..d38e52a --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_pcie_descriptor pollock_pcie_descriptors[] = +{ + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 1, + .end_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = +{ + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *pcie_descs = pollock_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pollock_pcie_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Gerrit-Change-Number: 42786 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/qemu-x86/car: Move long mode entry right before c entry
by Patrick Rudolph (Code Review) 29 Sep '20

29 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37370 ) Change subject: cpu/qemu-x86/car: Move long mode entry right before c entry ...................................................................... cpu/qemu-x86/car: Move long mode entry right before c entry Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/bootblock_crt0.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37370/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..e167a12 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -30,12 +30,6 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..f7280bf 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -39,6 +39,9 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/37370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Gerrit-Change-Number: 37370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Expand RCBA register list
by Angel Pons (Code Review) 28 Sep '20

28 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40062 ) Change subject: sb/intel/lynxpoint: Expand RCBA register list ...................................................................... sb/intel/lynxpoint: Expand RCBA register list Some registers do not seem to exist, and many were missing. Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0a62803..6d6590a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -445,45 +445,11 @@ /* Southbridge IO BARs */ +#define PMBASE 0x40 #define GPIOBASE 0x48 -#define PMBASE 0x40 +#define CIR0050 0x0050 /* 32bit */ -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ @@ -495,6 +461,9 @@ /* Root Port function number mask */ #define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define CIR0900 0x0900 /* 32bit */ +#define CIR1100 0x1100 /* 32bit */ + #define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ #define TWDR 0x1e18 /* 64bit */ @@ -504,6 +473,41 @@ #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define V0CTL 0x2014 /* 32bit */ +#define V0STS 0x201a /* 16bit */ + +#define V1CTL 0x2020 /* 32bit */ +#define V1STS 0x2026 /* 16bit */ + +#define VPCTL 0x2030 /* 32bit */ +#define VPSTS 0x2038 /* 16bit */ + +#define VMCTL 0x2040 /* 32bit */ +#define VMSTS 0x2048 /* 16bit */ + +#define CIR2088 0x2088 +#define REC 0x20ac +#define LCAP 0x21a4 +#define LCTL 0x21a8 +#define DMIC 0x2234 +#define CIR2238 0x2238 +#define CIR228C 0x228c +#define DMC 0x2304 +#define CIR2314 0x2314 +#define CIR2320 0x2320 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 @@ -526,18 +530,6 @@ #define PIRQG 6 #define PIRQH 7 -/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_READY 0x0001 -#define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 -#define IOBPS_WRITE 0x0700 -#define IOBPU 0x233a -#define IOBPU_MAGIC 0xf000 - #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ @@ -581,26 +573,66 @@ #define D20IR 0x3160 /* 16bit */ #define D21IR 0x3164 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define ACPIIRQEN 0x31e0 /* 32bit */ -#define OIC 0x31fe /* 16bit */ -#define PMSYNC_CONFIG 0x33c4 /* 32bit */ -#define PMSYNC_CONFIG2 0x33cc /* 32bit */ -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(a,b,c,d) \ - (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define ACPIIRQEN 0x31e0 /* 32bit */ + +#define OIC 0x31fe /* 16bit */ + +#define PRSTS 0x3310 +#define CIR3314 0x3314 +#define PM_CFG 0x3318 +#define CIR3324 0x3324 +#define DEEP_S3_POL 0x3328 +#define DEEP_S4_POL 0x332c +#define DEEP_S5_POL 0x3330 +#define PM_CFG2 0x333c +#define CIR3340 0x3340 +#define CIR3344 0x3344 +#define CIR3348 0x3348 +#define CIR3350 0x3350 +#define CIR3360 0x3360 +#define CIR3368 0x3368 +#define CIR3378 0x3378 +#define CIR337C 0x337c +#define CIR3388 0x3388 +#define CIR3390 0x3390 +#define CIR33A0 0x33a0 +#define CIR33B0 0x33b0 +#define CIR33C0 0x33c0 +#define PMSYNC_CONFIG 0x33c4 /* 32bit */ +#define PMSYNC 0x33c8 +#define PMSYNC_CONFIG2 0x33cc /* 32bit */ +#define CIR33D0 0x33d0 +#define CIR33D4 0x33d4 #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) +#define PCH_DISABLE_GBE (1 << 5) +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ #define FD 0x3418 /* 32bit */ +#define CG 0x341c /* 32bit */ +#define FDSW 0x3420 #define DISPBDF 0x3424 /* 16bit */ #define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ +#define GSX_CTRL 0x3454 + +#define CIR3A28 0x3a28 +#define CIR3A2C 0x3a2c +#define CIR3A6C 0x3a6c +#define CIR3A80 0x3a80 +#define CIR3A84 0x3a84 +#define CIR3A88 0x3a88 + +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR)) /* Function Disable 1 RCBA 0x3418 */ #define PCH_DISABLE_ALWAYS (1 << 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/40062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Gerrit-Change-Number: 40062 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: arch/x86/Kconfig: Move pagetables down by 4K
by Patrick Rudolph (Code Review) 28 Sep '20

28 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37394 ) Change subject: arch/x86/Kconfig: Move pagetables down by 4K ...................................................................... arch/x86/Kconfig: Move pagetables down by 4K In case of 64K bootblock the pagetables doesn't fit, as the CBFS header also needs a few bytes. Fixes build error on platforms that use 64KiB bootblock. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37394/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0e6f486..1e27970 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -68,7 +68,7 @@ config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 - default 0xfffea000 + default 0xfffe9000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. -- To view, visit https://review.coreboot.org/c/coreboot/+/37394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Gerrit-Change-Number: 37394 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/intel/206ax: Fix get_cores_per_package
by Evgeny Zinoviev (Code Review) 28 Sep '20

28 Sep '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42413 ) Change subject: cpu/intel/206ax: Fix get_cores_per_package ...................................................................... cpu/intel/206ax: Fix get_cores_per_package Current implementation uses CPUID 0Bh function that returns numbers of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries(). Use MSR 0x35 instead, which returns correct number of logical processors with and without HT. Related to #29669. Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 5 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42413/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9ff0673..44b3360 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -14,18 +14,13 @@ static int get_cores_per_package(void) { - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; + msr_t msr; + int logical_cores; - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; + msr = rdmsr(MSR_CORE_THREAD_COUNT); + logical_cores = msr.lo & 0xffff; - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; + return logical_cores; } static void generate_cstate_entries(acpi_cstate_t *cstates, -- To view, visit https://review.coreboot.org/c/coreboot/+/42413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Gerrit-Change-Number: 42413 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: [WIP]nehalem: Add x86_64 support
by Patrick Rudolph (Code Review) 26 Sep '20

26 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37371 ) Change subject: [WIP]nehalem: Add x86_64 support ...................................................................... [WIP]nehalem: Add x86_64 support Use correct datasize to compile on x86_64. Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc M src/arch/x86/include/arch/cbfs.h M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_2065x/Kconfig M src/cpu/x86/early_reset.S M src/drivers/pc80/tpm/tis.c M src/northbridge/intel/nehalem/raminit.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smihandler.c 14 files changed, 39 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37371/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 45db303..a25d91a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -126,7 +126,7 @@ $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif -bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S +bootblock-y += walkcbfs.S else # ROMCC_BOOTBLOCK diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index ec367ed..78bf2ed 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -33,7 +33,7 @@ static void *walkcbfs(char *target) { struct cbfs_file *head = walkcbfs_head(target); - if ((u32)head != 0) + if ((uintptr_t)head != 0) return CBFS_SUBHEADER(head); /* We should never reach this if 'target' exists */ @@ -51,7 +51,7 @@ static inline unsigned long findstage(char *target) { struct cbfs_stage_restricted *stage = walkcbfs(target); - if ((u32)stage != 0) + if ((uintptr_t)stage != 0) return stage->entry; /* We should never reach this if 'target' exists */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..e458302 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -220,8 +220,20 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + +#ifdef __x86_64__ + + movd %mm2, %rdi + shld %rdi, 32 + movd %mm1, %rsi + or %rsi, %rdi /* tsc */ + + movd %mm0, %rsi /* BIST */ +#else + subl $4, %esp /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -229,6 +241,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 647f67c..b9c43cc 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -56,6 +56,7 @@ .section .text .global update_bsp_microcode +.code32 update_bsp_microcode: /* Keep return address */ diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a76a95d..d816b4e 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_2065X +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index ec015abe..998ebda 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -21,6 +21,7 @@ .section .text .global check_mtrr +.code32 check_mtrr: /* Use the MTRR default type MSR as a proxy for detecting INIT#. diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 39fa70d..27e11bd 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -55,7 +55,7 @@ /* the macro accepts the locality value, but only locality 0 is operational */ #define TIS_REG(LOCALITY, REG) \ - (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + (void *)((uintptr_t)CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) /* hardware registers' offsets */ #define TIS_REG_ACCESS 0x0 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..673cb5a 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1999,7 +1999,7 @@ u32 offset; u8 *base; - base = (u8 *)(totalrank << 28); + base = (u8 *)(uintptr_t)(totalrank << 28); for (offset = 0; offset < 9 * 480; offset += 2) { write32(base + offset * 8, get_etalon2(flip, offset)); write32(base + offset * 8 + 4, get_etalon2(flip, offset)); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..84960ea 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -482,7 +482,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (void *) + mei_base_address = (void *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea7..c0d2494 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -238,7 +238,7 @@ // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..6771a7a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -598,7 +598,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..62fd08a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -372,7 +372,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..33e717a 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -104,7 +104,7 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..a68c89a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -177,7 +177,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (global_nvs_t *)(uintptr_t)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Gerrit-Change-Number: 37371 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1
by Varshit B Pandya (Code Review) 25 Sep '20

25 Sep '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39473 ) Change subject: [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1 ...................................................................... [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I5d0c99211b6ba43a1032322214058db688337b67 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl M src/soc/intel/tigerlake/finalize.c 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39473/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl index 8df60a8..f8c6ae0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -20,7 +20,7 @@ { Method (_ON, 0, Serialized) // _ON_: Power On { - MCCT(1,1,1) // Clock 0, enable, 19.2MHz + //MCCT(1,1,1) // Clock 0, enable, 19.2MHz //Check if another sensor is ON IF(STA0) { @@ -55,7 +55,7 @@ IF(STA0) { //Do nothing since the other sensor is ON - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } ELSE { @@ -63,7 +63,7 @@ CTXS(GPP_D13) //Disable PP2800 lane CTXS(GPP_D14) - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } Store(0,STA1) } diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index aed5cc0..fd5655d 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -108,6 +108,11 @@ pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); + //Hack for enabling CLK + uint32_t test; + write32((void *)0xfdad800c, 0x2); + write32((void *)0xfdad800c, 0x3); + outb(APM_CNT_FINALIZE, APM_CNT); /* Indicate finalize step with post code */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d0c99211b6ba43a1032322214058db688337b67 Gerrit-Change-Number: 39473 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Enable CA perbit mechanism
by Duan Huayang (Code Review) 25 Sep '20

25 Sep '20

Duan Huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41965 ) Change subject: soc/mediatek/mt8183: Enable CA perbit mechanism ...................................................................... soc/mediatek/mt8183: Enable CA perbit mechanism LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin of some CA PIN too small than others, need enable the CA perbit mechanism to avoid those risk. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/emi.h 6 files changed, 83 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/41965/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index cb64e50..3e184ad 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -522,6 +522,19 @@ (0x1 << 31) | (0xa << 21) | (0xa << 26)); setbits32(&ch[0].ao.ckectrl, 0x1 << 23); clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); + + /* CA prebit shift and delay */ + SET32_BITFIELDS(&ch[0].ao.shu[0].selph_ca7, + SHU_SELPH_CA7_DLY_RA0, 0x0, + SHU_SELPH_CA7_DLY_RA1, 0x0, + SHU_SELPH_CA7_DLY_RA2, 0x0, + SHU_SELPH_CA7_DLY_RA3, 0x0, + SHU_SELPH_CA7_DLY_RA4, 0x0, + SHU_SELPH_CA7_DLY_RA5, 0x0); + SET32_BITFIELDS(&ch[0].phy.shu[0].rk[0].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 0x20); + SET32_BITFIELDS(&ch[0].phy.shu[0].rk[1].ca_cmd[9], + SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 0x20); } static void dramc_power_on_sequence(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 69d6f4d..f283a35 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -259,12 +259,34 @@ const struct sdram_params *params, const bool fast_calib) { u32 final_vref, clk_dly, cmd_dly, cs_dly; + const u8 *lpddr_phy_mapping = phy_mapping[chn]; + u8 ca_perbit_delay[CA_NUM_LP4] = {0}; + const u8 lp4_ca_mapping_pop[CHANNEL_MAX][CA_NUM_LP4] = { + [CHANNEL_A] = { + 1, 4, 3, 2, 0, 5 + }, + [CHANNEL_B] = { + 0, 3, 2, 4, 1, 5 + } + }; + + const u8 *ca_mapping = lp4_ca_mapping_pop[chn]; clk_dly = params->cbt_clk_dly[chn][rank]; cmd_dly = params->cbt_cmd_dly[chn][rank]; cs_dly = params->cbt_cs_dly[chn][rank]; final_vref = params->cbt_final_vref[chn][rank]; + /* set MRR pin mux */ + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, lpddr_phy_mapping[8], + MRR_BIT_MUX1_MRR_BIT1_SEL, lpddr_phy_mapping[9], + MRR_BIT_MUX1_MRR_BIT2_SEL, lpddr_phy_mapping[10], + MRR_BIT_MUX1_MRR_BIT3_SEL, lpddr_phy_mapping[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, lpddr_phy_mapping[12], + MRR_BIT_MUX2_MRR_BIT5_SEL, lpddr_phy_mapping[13]); + if (fast_calib) { /* Set CLK and CA delay */ SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], @@ -282,6 +304,24 @@ /* CBT set vref */ dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); dramc_dbg("final_vref: %#x\n", final_vref); + + if (freq_group >= LP4X_DDR3200) { + ca_perbit_delay[0] = params->cbt_ca_perbit_delay[chn][rank][0]; + ca_perbit_delay[1] = params->cbt_ca_perbit_delay[chn][rank][1]; + ca_perbit_delay[2] = params->cbt_ca_perbit_delay[chn][rank][2]; + ca_perbit_delay[3] = params->cbt_ca_perbit_delay[chn][rank][3]; + ca_perbit_delay[4] = params->cbt_ca_perbit_delay[chn][rank][4]; + ca_perbit_delay[5] = params->cbt_ca_perbit_delay[chn][rank][5]; + + /* Set CA perbit delay line calibration results */ + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0], + SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, ca_perbit_delay[ca_mapping[0]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, ca_perbit_delay[ca_mapping[1]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, ca_perbit_delay[ca_mapping[2]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, ca_perbit_delay[ca_mapping[3]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, ca_perbit_delay[ca_mapping[4]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, ca_perbit_delay[ca_mapping[5]]); + } } static void dramc_read_dbi_onoff(size_t chn, bool on) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index 11dd8f3..bcd7c02 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -30,6 +30,7 @@ }; enum { + CA_NUM_LP4 = 6, DQ_DATA_WIDTH = 16, DQS_BIT_NUMBER = 8, DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index 8cadb28..b1ef677 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -11,7 +11,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 3, + DRAMC_PARAM_HEADER_VERSION = 4, }; enum DRAMC_PARAM_STATUS_CODES { diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index d042bfd..ba0b29c 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -798,6 +798,7 @@ DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) +DEFINE_BITFIELD(SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 13, 8) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */ @@ -909,6 +910,32 @@ DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6) DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0) +/* DRAMC_REG_MRR_BIT_MUX1 */ +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0) + +/* DRAMC_REG_SHU_SELPH_CA7 */ +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0) + +/* DRAMC_REG_MRR_BIT_MUX2 */ +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0) + +/* DDRPHY_SHU1_R0_CA_CMD0 */ +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, 23, 20) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, 19, 16) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, 15, 12) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, 11, 8) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, 7, 4) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, 3, 0) + struct dramc_channel_regs { union { struct dramc_ddrphy_ao_regs phy; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 46921fe..48b90cf 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -28,6 +28,7 @@ u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; /* Gating */ u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; -- To view, visit https://review.coreboot.org/c/coreboot/+/41965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47 Gerrit-Change-Number: 41965 Gerrit-PatchSet: 1 Gerrit-Owner: Duan Huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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