Change in coreboot[master]: broadwell: Relocate functions and prototypes
by Angel Pons (Code Review) 30 Oct '20
by Angel Pons (Code Review) 30 Oct '20
30 Oct '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41942 )
Change subject: broadwell: Relocate functions and prototypes
......................................................................
broadwell: Relocate functions and prototypes
Move the code around so that it aligns with Haswell.
Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/cpu/intel/broadwell/Makefile.inc
M src/cpu/intel/broadwell/acpi.c
M src/cpu/intel/broadwell/bootblock.c
M src/cpu/intel/broadwell/broadwell.h
M src/cpu/intel/broadwell/broadwell_early_init.c
R src/cpu/intel/broadwell/broadwell_init.c
M src/cpu/intel/broadwell/chip.c
M src/cpu/intel/broadwell/romstage.c
M src/mainboard/google/auron/romstage.c
M src/mainboard/google/auron/variant.h
M src/northbridge/intel/broadwell/Makefile.inc
A src/northbridge/intel/broadwell/acpi.c
M src/northbridge/intel/broadwell/broadwell.h
R src/northbridge/intel/broadwell/early_init.c
A src/northbridge/intel/broadwell/northbridge.c
M src/northbridge/intel/broadwell/raminit.c
A src/northbridge/intel/broadwell/raminit.h
M src/northbridge/intel/broadwell/refcode.c
A src/northbridge/intel/broadwell/refcode.h
M src/northbridge/intel/broadwell/report_platform.c
D src/northbridge/intel/broadwell/romstage.h
M src/northbridge/intel/broadwell/systemagent.c
M src/southbridge/intel/wildcatpoint/acpi.h
M src/southbridge/intel/wildcatpoint/early_pch.c
M src/southbridge/intel/wildcatpoint/early_smbus.c
M src/southbridge/intel/wildcatpoint/lpc.c
M src/southbridge/intel/wildcatpoint/pch.h
M src/southbridge/intel/wildcatpoint/power_state.c
M src/southbridge/intel/wildcatpoint/ramstage.c
M src/southbridge/intel/wildcatpoint/ramstage.h
A src/southbridge/intel/wildcatpoint/romstage.h
31 files changed, 824 insertions(+), 762 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/1
diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc
index 453b879..ad5dc5b 100644
--- a/src/cpu/intel/broadwell/Makefile.inc
+++ b/src/cpu/intel/broadwell/Makefile.inc
@@ -16,9 +16,10 @@
ramstage-y += acpi.c
+ramstage-y += broadwell_init.c
+
ramstage-y += chip.c
-ramstage-y += cpu.c
ramstage-y += cpu_info.c
smm-y += cpu_info.c
diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c
index bd4eb63..a63914c 100644
--- a/src/cpu/intel/broadwell/acpi.c
+++ b/src/cpu/intel/broadwell/acpi.c
@@ -147,151 +147,26 @@
return cores;
}
-void acpi_init_gnvs(global_nvs_t *gnvs)
+static void generate_C_state_entries(void)
{
- /* Set unknown wake source */
- gnvs->pm1i = -1;
+ acpi_cstate_t map[3];
+ int *set;
+ int i;
- /* CPU core count */
- gnvs->pcnt = dev_count_cpu();
+ config_t *config = config_of_soc();
-#if CONFIG(CONSOLE_CBMEM)
- /* Update the mem console pointer. */
- gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
-#endif
+ if (config->s0ix_enable)
+ set = cstate_set_s0ix;
+ else
+ set = cstate_set_non_s0ix;
-#if CONFIG(CHROMEOS)
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if CONFIG(EC_GOOGLE_CHROMEEC)
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
-#endif
-}
+ for (i = 0; i < 3; i++) {
+ memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
+ map[i].ctype = i + 1;
+ }
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
- MCFG_BASE_ADDRESS, 0, 0, 255);
- return current;
-}
-
-void acpi_fill_in_fadt(acpi_fadt_t *fadt)
-{
- const uint16_t pmbase = ACPI_BASE_ADDRESS;
-
- fadt->sci_int = acpi_sci_irq();
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0;
-
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->gpe0_blk = pmbase + GPE0_STS(0);
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 32;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 87;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
- fadt->reset_value = 6;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.access_size = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.access_size = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- /*
- * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
- * The bit_width field intentionally overflows here.
- * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
- * seems to work fine on Linux 5.0 and Windows 10.
- */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ /* Generate C-state tables */
+ acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
static acpi_tstate_t tss_table_fine[] = {
@@ -346,28 +221,6 @@
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
}
-static void generate_C_state_entries(void)
-{
- acpi_cstate_t map[3];
- int *set;
- int i;
-
- config_t *config = config_of_soc();
-
- if (config->s0ix_enable)
- set = cstate_set_s0ix;
- else
- set = cstate_set_non_s0ix;
-
- for (i = 0; i < 3; i++) {
- memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
- map[i].ctype = i + 1;
- }
-
- /* Generate C-state tables */
- acpigen_write_CST_package(map, ARRAY_SIZE(map));
-}
-
static int calculate_power(int tdp, int p1_ratio, int ratio)
{
u32 m;
@@ -540,70 +393,6 @@
acpigen_write_processor_cnot(cores_per_package);
}
-static unsigned long acpi_fill_dmar(unsigned long current)
-{
- struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
- const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
- const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
- const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
- const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
-
- /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
- if (igfx_dev && igfx_dev->enabled && gfxvtbar
- && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
- unsigned long tmp = current;
-
- current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
- current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
-
- acpi_dmar_drhd_fixup(tmp, current);
-
- /* Add RMRR entry */
- tmp = current;
-
- current += acpi_create_dmar_rmrr(current, 0,
- sa_get_gsm_base(), sa_get_tolud_base() - 1);
- current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
- acpi_dmar_rmrr_fixup(tmp, current);
- }
-
- /* VTVC0BAR has to be set, enabled, and in 32-bit space */
- if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
- const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current,
- DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
- current += acpi_create_dmar_ds_ioapic(current,
- 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
- size_t i;
- for (i = 0; i < 8; ++i)
- current += acpi_create_dmar_ds_msi_hpet(current,
- 0, PCH_HPET_PCI_BUS,
- PCH_HPET_PCI_SLOT, i);
- acpi_dmar_drhd_fixup(tmp, current);
- }
-
- return current;
-}
-
-unsigned long northbridge_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- /* Create DMAR table only if we have VT-d capability. */
- const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
- if (capid0_a & VTD_DISABLE)
- return current;
-
- acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
- printk(BIOS_DEBUG, "ACPI: * DMAR\n");
- acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
- current += dmar->header.length;
- current = acpi_align_current(current);
- acpi_add_table(rsdp, dmar);
-
- return current;
-}
-
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci = acpi_sci_irq();
diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c
index 3290eee..fbaea86 100644
--- a/src/cpu/intel/broadwell/bootblock.c
+++ b/src/cpu/intel/broadwell/bootblock.c
@@ -7,9 +7,10 @@
#include <cpu/x86/mtrr.h>
#include <halt.h>
#include <southbridge/intel/wildcatpoint/rcba.h>
-#include <cpu/intel/broadwell/broadwell.h>
#include <delay.h>
+#include <cpu/intel/broadwell/broadwell.h>
+
static void set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
diff --git a/src/cpu/intel/broadwell/broadwell.h b/src/cpu/intel/broadwell/broadwell.h
index 5654e0a..9e62eea 100644
--- a/src/cpu/intel/broadwell/broadwell.h
+++ b/src/cpu/intel/broadwell/broadwell.h
@@ -108,4 +108,19 @@
u32 cpu_stepping(void);
int cpu_is_ult(void);
+#include <northbridge/intel/broadwell/pei_data.h>
+
+struct chipset_power_state;
+struct romstage_params {
+ struct chipset_power_state *power_state;
+ struct pei_data pei_data;
+};
+
+void set_max_freq(void);
+
+void mainboard_pre_raminit(struct romstage_params *params);
+void mainboard_post_raminit(struct romstage_params *params);
+
+void broadwell_init_cpus(struct device *dev);
+
#endif
diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c
index 4fd23f6..b093ece 100644
--- a/src/cpu/intel/broadwell/broadwell_early_init.c
+++ b/src/cpu/intel/broadwell/broadwell_early_init.c
@@ -4,7 +4,6 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/broadwell/broadwell.h>
-#include <northbridge/intel/broadwell/romstage.h>
u32 cpu_family_model(void)
{
diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/broadwell_init.c
similarity index 97%
rename from src/cpu/intel/broadwell/cpu.c
rename to src/cpu/intel/broadwell/broadwell_init.c
index f8132b5..8c74394 100644
--- a/src/cpu/intel/broadwell/cpu.c
+++ b/src/cpu/intel/broadwell/broadwell_init.c
@@ -1,29 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/cpu.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/mp.h>
+#include <cpu/intel/broadwell/broadwell.h>
+#include <cpu/intel/common/common.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/name.h>
#include <cpu/x86/smm.h>
#include <delay.h>
+#include <device/device.h>
#include <intelblocks/cpulib.h>
-#include <cpu/intel/broadwell/broadwell.h>
+#include <northbridge/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/iomap.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
+#include <southbridge/intel/wildcatpoint/pm.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <southbridge/intel/wildcatpoint/rcba.h>
-#include <northbridge/intel/broadwell/broadwell.h>
#include <southbridge/intel/wildcatpoint/soc_chip.h>
-#include <cpu/intel/common/common.h>
+#include <string.h>
+#include <types.h>
+
+/** power_limit_time_sec_to_msr **/
+
+/** power_limit_time_msr_to_sec **/
+
+/** haswell_family_model **/
+
+/** haswell_stepping **/
+
+/** haswell_is_ult **/
/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
@@ -230,6 +242,10 @@
RCBA32(PMSYNC_CONFIG2) = pmsync2;
}
+/** cpu_config_tdp_levels **/
+
+/** set_power_limits **/
+
static void configure_c_states(void)
{
msr_t msr;
diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c
index 443faf4..c769a80 100644
--- a/src/cpu/intel/broadwell/chip.c
+++ b/src/cpu/intel/broadwell/chip.c
@@ -2,8 +2,11 @@
#include <device/device.h>
#include <device/pci.h>
+#include <cpu/intel/broadwell/broadwell.h>
+#include <northbridge/intel/broadwell/broadwell.h>
#include <southbridge/intel/wildcatpoint/acpi.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
+#include <southbridge/intel/wildcatpoint/pch.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <southbridge/intel/wildcatpoint/soc_chip.h>
diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c
index 35bb592..e33ae9f 100644
--- a/src/cpu/intel/broadwell/romstage.c
+++ b/src/cpu/intel/broadwell/romstage.c
@@ -10,11 +10,14 @@
#include <program_loading.h>
#include <romstage_handoff.h>
#include <timestamp.h>
+#include <cpu/intel/broadwell/broadwell.h>
#include <southbridge/intel/wildcatpoint/gpio.h>
#include <southbridge/intel/wildcatpoint/me.h>
#include <northbridge/intel/broadwell/pei_data.h>
#include <southbridge/intel/wildcatpoint/pm.h>
-#include <northbridge/intel/broadwell/romstage.h>
+#include <northbridge/intel/broadwell/raminit.h>
+#include <southbridge/intel/wildcatpoint/romstage.h>
+#include <northbridge/intel/broadwell/broadwell.h>
#include <southbridge/intel/wildcatpoint/spi.h>
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index 1540299..cf6b447 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -2,9 +2,9 @@
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
+#include <cpu/intel/broadwell/broadwell.h>
#include <northbridge/intel/broadwell/pei_data.h>
#include <northbridge/intel/broadwell/pei_wrapper.h>
-#include <northbridge/intel/broadwell/romstage.h>
#include <variant/spd.h>
#include "variant.h"
diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h
index 9853aa2..20873f0 100644
--- a/src/mainboard/google/auron/variant.h
+++ b/src/mainboard/google/auron/variant.h
@@ -4,7 +4,7 @@
#define VARIANT_H
#include <device/device.h>
-#include <northbridge/intel/broadwell/romstage.h>
+#include <cpu/intel/broadwell/broadwell.h>
int variant_smbios_data(struct device *dev, int *handle,
unsigned long *current);
diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc
index 51cf4a8..69ea826 100644
--- a/src/northbridge/intel/broadwell/Makefile.inc
+++ b/src/northbridge/intel/broadwell/Makefile.inc
@@ -4,6 +4,10 @@
bootblock-y += bootblock.c
+ramstage-y += acpi.c
+
+romstage-y += early_init.c
+
ramstage-y += finalize.c
ramstage-y += igd.c
@@ -13,12 +17,13 @@
postcar-y += memmap.c
ramstage-y += minihd.c
+ramstage-y += northbridge.c
+
ramstage-y += pei_data.c
romstage-y += pei_data.c
romstage-y += raminit.c
romstage-y += report_platform.c
-romstage-y += romstage.c
ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
new file mode 100644
index 0000000..df08537
--- /dev/null
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+#include <console/console.h>
+#include <acpi/acpi.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/pch.h>
+#include <southbridge/intel/wildcatpoint/pci_devs.h>
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+ MCFG_BASE_ADDRESS, 0, 0, 255);
+ return current;
+}
+
+static unsigned long acpi_fill_dmar(unsigned long current)
+{
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
+ const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
+ const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
+ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
+
+ /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
+ if (igfx_dev && igfx_dev->enabled && gfxvtbar
+ && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+
+ /* Add RMRR entry */
+ tmp = current;
+
+ current += acpi_create_dmar_rmrr(current, 0,
+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+ acpi_dmar_rmrr_fixup(tmp, current);
+ }
+
+ /* VTVC0BAR has to be set, enabled, and in 32-bit space */
+ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_drhd(current,
+ DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_ds_ioapic(current,
+ 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+ size_t i;
+ for (i = 0; i < 8; ++i)
+ current += acpi_create_dmar_ds_msi_hpet(current,
+ 0, PCH_HPET_PCI_BUS,
+ PCH_HPET_PCI_SLOT, i);
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ return current;
+}
+
+unsigned long northbridge_write_acpi_tables(const struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ /* Create DMAR table only if we have VT-d capability. */
+ const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
+ if (capid0_a & VTD_DISABLE)
+ return current;
+
+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");
+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+ current += dmar->header.length;
+ current = acpi_align_current(current);
+ acpi_add_table(rsdp, dmar);
+
+ return current;
+}
diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h
index 5f4ad6c..1a8e6cf 100644
--- a/src/northbridge/intel/broadwell/broadwell.h
+++ b/src/northbridge/intel/broadwell/broadwell.h
@@ -126,4 +126,13 @@
uintptr_t sa_get_tolud_base(void);
uintptr_t sa_get_gsm_base(void);
+void report_platform_info(void);
+
+void systemagent_early_init(void);
+
+#include <device/device.h>
+
+unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current,
+ struct acpi_rsdp *rsdp);
+
#endif
diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/early_init.c
similarity index 97%
rename from src/northbridge/intel/broadwell/romstage.c
rename to src/northbridge/intel/broadwell/early_init.c
index 064c203..e1bbcc8 100644
--- a/src/northbridge/intel/broadwell/romstage.c
+++ b/src/northbridge/intel/broadwell/early_init.c
@@ -6,7 +6,6 @@
#include <reg_script.h>
#include <southbridge/intel/wildcatpoint/iomap.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
-#include <northbridge/intel/broadwell/romstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
static const struct reg_script systemagent_early_init_script[] = {
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
new file mode 100644
index 0000000..5122fed
--- /dev/null
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <acpi/acpi.h>
+#include <device/pci_ops.h>
+#include <stdint.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/power_limit.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <cpu/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/iomap.h>
+#include <southbridge/intel/wildcatpoint/pci_devs.h>
+#include <southbridge/intel/wildcatpoint/ramstage.h>
+#include <northbridge/intel/broadwell/broadwell.h>
+
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
+ u32 *len)
+{
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ pciexbar_reg = pci_read_config32(dev, index);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: // 256MB
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
+ (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: // 128M
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
+ (1 << 28)|(1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: // 64M
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
+ (1 << 28)|(1 << 27)|(1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
+{
+ u32 bar;
+
+ bar = pci_read_config32(dev, index);
+
+ /* If not enabled don't report it. */
+ if (!(bar & 0x1))
+ return 0;
+
+ /* Knock down the enable bit. */
+ *base = bar & ~1;
+
+ return 1;
+}
+
+/* There are special BARs that actually are programmed in the MCHBAR. These
+ * Intel special features, but they do consume resources that need to be
+ * accounted for. */
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
+ u32 *len)
+{
+ u32 bar;
+
+ bar = MCHBAR32(index);
+
+ /* If not enabled don't report it. */
+ if (!(bar & 0x1))
+ return 0;
+
+ /* Knock down the enable bit. */
+ *base = bar & ~1;
+
+ return 1;
+}
+
+struct fixed_mmio_descriptor {
+ unsigned int index;
+ u32 size;
+ int (*get_resource)(struct device *dev, unsigned int index,
+ u32 *base, u32 *size);
+ const char *description;
+};
+
+struct fixed_mmio_descriptor mc_fixed_resources[] = {
+ { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
+ { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
+ { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
+ { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
+ { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
+ { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
+};
+
+/*
+ * Add all known fixed MMIO ranges that hang off the host bridge/memory
+ * controller device.
+ */
+static void mc_add_fixed_mmio_resources(struct device *dev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
+ u32 base;
+ u32 size;
+ struct resource *resource;
+ unsigned int index;
+
+ size = mc_fixed_resources[i].size;
+ index = mc_fixed_resources[i].index;
+ if (!mc_fixed_resources[i].get_resource(dev, index,
+ &base, &size))
+ continue;
+
+ resource = new_resource(dev, mc_fixed_resources[i].index);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
+ resource->base = base;
+ resource->size = size;
+ printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
+ __func__, mc_fixed_resources[i].description, index,
+ (unsigned long)base, (unsigned long)(base + size - 1));
+ }
+}
+
+/* Host Memory Map:
+ *
+ * +--------------------------+ TOUUD
+ * | |
+ * +--------------------------+ 4GiB
+ * | PCI Address Space |
+ * +--------------------------+ TOLUD (also maps into MC address space)
+ * | iGD |
+ * +--------------------------+ BDSM
+ * | GTT |
+ * +--------------------------+ BGSM
+ * | TSEG |
+ * +--------------------------+ TSEGMB
+ * | Usage DRAM |
+ * +--------------------------+ 0
+ *
+ * Some of the base registers above can be equal making the size of those
+ * regions 0. The reason is because the memory controller internally subtracts
+ * the base registers from each other to determine sizes of the regions. In
+ * other words, the memory map is in a fixed order no matter what.
+ */
+
+struct map_entry {
+ int reg;
+ int is_64_bit;
+ int is_limit;
+ const char *description;
+};
+
+static void read_map_entry(struct device *dev, struct map_entry *entry,
+ uint64_t *result)
+{
+ uint64_t value;
+ uint64_t mask;
+
+ /* All registers are on a 1MiB granularity. */
+ mask = ((1ULL<<20)-1);
+ mask = ~mask;
+
+ value = 0;
+
+ if (entry->is_64_bit) {
+ value = pci_read_config32(dev, entry->reg + 4);
+ value <<= 32;
+ }
+
+ value |= pci_read_config32(dev, entry->reg);
+ value &= mask;
+
+ if (entry->is_limit)
+ value |= ~mask;
+
+ *result = value;
+}
+
+#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
+ { \
+ .reg = reg_, \
+ .is_64_bit = is_64_, \
+ .is_limit = is_limit_, \
+ .description = desc_, \
+ }
+
+#define MAP_ENTRY_BASE_64(reg_, desc_) \
+ MAP_ENTRY(reg_, 1, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
+ MAP_ENTRY(reg_, 1, 1, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_) \
+ MAP_ENTRY(reg_, 0, 0, desc_)
+
+enum {
+ TOM_REG,
+ TOUUD_REG,
+ MESEG_BASE_REG,
+ MESEG_LIMIT_REG,
+ REMAP_BASE_REG,
+ REMAP_LIMIT_REG,
+ TOLUD_REG,
+ BGSM_REG,
+ BDSM_REG,
+ TSEG_REG,
+ // Must be last.
+ NUM_MAP_ENTRIES
+};
+
+static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
+ [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
+ [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+ [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
+ [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
+ [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
+ [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
+ [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+ [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+ [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+ [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
+};
+
+static void mc_read_map_entries(struct device *dev, uint64_t *values)
+{
+ int i;
+ for (i = 0; i < NUM_MAP_ENTRIES; i++)
+ read_map_entry(dev, &memory_map[i], &values[i]);
+}
+
+static void mc_report_map_entries(struct device *dev, uint64_t *values)
+{
+ int i;
+ for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
+ memory_map[i].description, values[i]);
+ }
+ /* One can validate the BDSM and BGSM against the GGC. */
+ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
+}
+
+static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
+{
+ unsigned long base_k, size_k;
+ unsigned long touud_k;
+ unsigned long index;
+ struct resource *resource;
+ uint64_t mc_values[NUM_MAP_ENTRIES];
+ unsigned long dpr_size = 0;
+ u32 dpr_reg;
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
+ /* Read in the MAP registers and report their values. */
+ mc_read_map_entries(dev, &mc_values[0]);
+ mc_report_map_entries(dev, &mc_values[0]);
+
+ /*
+ * DMA Protected Range can be reserved below TSEG for PCODE patch
+ * or TXT/BootGuard related data. Rather than report a base address
+ * the DPR register reports the TOP of the region, which is the same
+ * as TSEG base. The region size is reported in MiB in bits 11:4.
+ */
+ dpr_reg = pci_read_config32(sa_dev, DPR);
+ if (dpr_reg & DPR_EPM) {
+ dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
+ printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
+ }
+
+ /*
+ * These are the host memory ranges that should be added:
+ * - 0 -> 0xa0000: cacheable
+ * - 0xc0000 -> TSEG : cacheable
+ * - TESG -> BGSM: cacheable with standard MTRRs and reserved
+ * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
+ * - 4GiB -> TOUUD: cacheable
+ *
+ * The default SMRAM space is reserved so that the range doesn't
+ * have to be saved during S3 Resume. Once marked reserved the OS
+ * cannot use the memory. This is a bit of an odd place to reserve
+ * the region, but the CPU devices don't have dev_ops->read_resources()
+ * called on them.
+ *
+ * The range 0xa0000 -> 0xc0000 does not have any resources
+ * associated with it to handle legacy VGA memory. If this range
+ * is not omitted the mtrr code will setup the area as cacheable
+ * causing VGA access to not work.
+ *
+ * The TSEG region is mapped as cacheable so that one can perform
+ * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
+ * precedence over the existing MTRRs covering this region.
+ *
+ * It should be noted that cacheable entry types need to be added in
+ * order. The reason is that the current MTRR code assumes this and
+ * falls over itself if it isn't.
+ *
+ * The resource index starts low and should not meet or exceed
+ * PCI_BASE_ADDRESS_0.
+ */
+ index = *resource_cnt;
+
+ /* 0 - > 0xa0000 */
+ base_k = 0;
+ size_k = (0xa0000 >> 10) - base_k;
+ ram_resource(dev, index++, base_k, size_k);
+
+ /* 0xc0000 -> TSEG - DPR */
+ base_k = 0xc0000 >> 10;
+ size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
+ size_k -= dpr_size >> 10;
+ ram_resource(dev, index++, base_k, size_k);
+
+ /* TSEG - DPR -> BGSM */
+ resource = new_resource(dev, index++);
+ resource->base = mc_values[TSEG_REG] - dpr_size;
+ resource->size = mc_values[BGSM_REG] - resource->base;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+
+ /* BGSM -> TOLUD */
+ resource = new_resource(dev, index++);
+ resource->base = mc_values[BGSM_REG];
+ resource->size = mc_values[TOLUD_REG] - resource->base;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
+
+ /* 4GiB -> TOUUD */
+ base_k = 4096 * 1024; /* 4GiB */
+ touud_k = mc_values[TOUUD_REG] >> 10;
+ size_k = touud_k - base_k;
+ if (touud_k > base_k)
+ ram_resource(dev, index++, base_k, size_k);
+
+ /* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xfffff: RAM
+ */
+ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
+ reserved_ram_resource(dev, index++, (0xc0000 >> 10),
+ (0x100000 - 0xc0000) >> 10);
+
+ if (CONFIG(CHROMEOS))
+ chromeos_reserve_ram_oops(dev, index++);
+
+ *resource_cnt = index;
+}
+
+static void systemagent_read_resources(struct device *dev)
+{
+ int index = 0;
+ const bool vtd_capable =
+ !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+
+ /* Read standard PCI resources. */
+ pci_dev_read_resources(dev);
+
+ /* Add all fixed MMIO resources. */
+ mc_add_fixed_mmio_resources(dev);
+
+ /* Add VT-d MMIO resources if capable */
+ if (vtd_capable) {
+ mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
+ GFXVT_BASE_SIZE / KiB);
+ mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
+ VTVC0_BASE_SIZE / KiB);
+ }
+
+ /* Calculate and add DRAM resources. */
+ mc_add_dram_resources(dev, &index);
+}
+
+static void systemagent_init(struct device *dev)
+{
+ struct soc_power_limits_config *config;
+ u8 bios_reset_cpl, pair;
+
+ /* Enable Power Aware Interrupt Routing */
+ pair = MCHBAR8(MCH_PAIR);
+ pair &= ~0x7; /* Clear 2:0 */
+ pair |= 0x4; /* Fixed Priority */
+ MCHBAR8(MCH_PAIR) = pair;
+
+ /*
+ * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialized memory and power management
+ */
+ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
+ bios_reset_cpl |= 3;
+ MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
+ printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
+
+ /* Configure turbo power limits 1ms after reset complete bit */
+ mdelay(1);
+ config = config_of_soc();
+ set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config);
+}
+
+static struct device_operations systemagent_ops = {
+ .read_resources = systemagent_read_resources,
+ .acpi_fill_ssdt = generate_cpu_entries,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = systemagent_init,
+ .ops_pci = &broadwell_pci_ops,
+};
+
+static const unsigned short systemagent_ids[] = {
+ 0x0a04, /* Haswell ULT */
+ 0x1604, /* Broadwell-U/Y */
+ 0x1610, /* Broadwell-H Desktop */
+ 0x1614, /* Broadwell-H Mobile */
+ 0
+};
+
+static const struct pci_driver systemagent_driver __pci_driver = {
+ .ops = &systemagent_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = systemagent_ids
+};
diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c
index d40c2a3..9e8d8ad 100644
--- a/src/northbridge/intel/broadwell/raminit.c
+++ b/src/northbridge/intel/broadwell/raminit.c
@@ -9,17 +9,54 @@
#include <memory_info.h>
#include <mrc_cache.h>
#include <string.h>
-#if CONFIG(EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
#include <vendorcode/google/chromeos/chromeos.h>
#include <southbridge/intel/wildcatpoint/iomap.h>
#include <northbridge/intel/broadwell/pei_data.h>
#include <northbridge/intel/broadwell/pei_wrapper.h>
#include <southbridge/intel/wildcatpoint/pm.h>
-#include <northbridge/intel/broadwell/romstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
+#include <northbridge/intel/broadwell/raminit.h>
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+void report_memory_config(void)
+{
+ u32 addr_decoder_common, addr_decode_ch[2];
+ int i;
+
+ addr_decoder_common = MCHBAR32(0x5000);
+ addr_decode_ch[0] = MCHBAR32(0x5004);
+ addr_decode_ch[1] = MCHBAR32(0x5008);
+
+ printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
+ (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
+ printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+ addr_decoder_common & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+ u32 ch_conf = addr_decode_ch[i];
+ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
+ i, ch_conf);
+ printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
+ ((ch_conf >> 22) & 1) ? "on" : "off");
+ printk(BIOS_DEBUG, " rank interleave %s\n",
+ ((ch_conf >> 21) & 1) ? "on" : "off");
+ printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+ ((ch_conf >> 17) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? "" : ", selected");
+ printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
+ ((ch_conf >> 8) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+ ((ch_conf >> 18) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? ", selected" : "");
+ }
+}
/*
* Find PEI executable in coreboot filesystem and execute it.
diff --git a/src/northbridge/intel/broadwell/raminit.h b/src/northbridge/intel/broadwell/raminit.h
new file mode 100644
index 0000000..7f324b8
--- /dev/null
+++ b/src/northbridge/intel/broadwell/raminit.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include "pei_data.h"
+
+void raminit(struct pei_data *pei_data);
+void report_memory_config(void);
+
+#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c
index 13be8b6..11df686 100644
--- a/src/northbridge/intel/broadwell/refcode.c
+++ b/src/northbridge/intel/broadwell/refcode.c
@@ -11,6 +11,7 @@
#include <stage_cache.h>
#include <northbridge/intel/broadwell/pei_data.h>
#include <northbridge/intel/broadwell/pei_wrapper.h>
+#include <northbridge/intel/broadwell/refcode.h>
#include <southbridge/intel/wildcatpoint/pm.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
diff --git a/src/northbridge/intel/broadwell/refcode.h b/src/northbridge/intel/broadwell/refcode.h
new file mode 100644
index 0000000..80219eb
--- /dev/null
+++ b/src/northbridge/intel/broadwell/refcode.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BROADWELL_REFCODE_H_
+#define _BROADWELL_REFCODE_H_
+
+#if CONFIG(HAVE_REFCODE_BLOB)
+void broadwell_run_reference_code(void);
+#else
+static inline void broadwell_run_reference_code(void) { }
+#endif
+
+#endif /* _BROADWELL_REFCODE_H_ */
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 3ac4ece..95d9c99 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -9,7 +9,6 @@
#include <cpu/intel/broadwell/broadwell.h>
#include <southbridge/intel/wildcatpoint/pch.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
-#include <northbridge/intel/broadwell/romstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
static struct {
@@ -184,44 +183,3 @@
report_pch_info();
report_igd_info();
}
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-void report_memory_config(void)
-{
- u32 addr_decoder_common, addr_decode_ch[2];
- int i;
-
- addr_decoder_common = MCHBAR32(0x5000);
- addr_decode_ch[0] = MCHBAR32(0x5004);
- addr_decode_ch[1] = MCHBAR32(0x5008);
-
- printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
- (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
- printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
- addr_decoder_common & 3,
- (addr_decoder_common >> 2) & 3,
- (addr_decoder_common >> 4) & 3);
-
- for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
- u32 ch_conf = addr_decode_ch[i];
- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
- i, ch_conf);
- printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
- ((ch_conf >> 22) & 1) ? "on" : "off");
- printk(BIOS_DEBUG, " rank interleave %s\n",
- ((ch_conf >> 21) & 1) ? "on" : "off");
- printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
- ((ch_conf >> 0) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
- ((ch_conf >> 17) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? "" : ", selected");
- printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
- ((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
- ((ch_conf >> 18) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? ", selected" : "");
- }
-}
diff --git a/src/northbridge/intel/broadwell/romstage.h b/src/northbridge/intel/broadwell/romstage.h
deleted file mode 100644
index 275938a..0000000
--- a/src/northbridge/intel/broadwell/romstage.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _BROADWELL_ROMSTAGE_H_
-#define _BROADWELL_ROMSTAGE_H_
-
-#include <stdint.h>
-#include <northbridge/intel/broadwell/pei_data.h>
-
-struct chipset_power_state;
-struct romstage_params {
- struct chipset_power_state *power_state;
- struct pei_data pei_data;
-};
-
-void mainboard_pre_raminit(struct romstage_params *params);
-void mainboard_post_raminit(struct romstage_params *params);
-
-void raminit(struct pei_data *pei_data);
-
-struct chipset_power_state;
-struct chipset_power_state *fill_power_state(void);
-void report_platform_info(void);
-void report_memory_config(void);
-
-void set_max_freq(void);
-
-void systemagent_early_init(void);
-void pch_early_init(void);
-void pch_uart_init(void);
-void intel_early_me_status(void);
-
-#endif
diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c
index 67d78cf..ee5e836 100644
--- a/src/northbridge/intel/broadwell/systemagent.c
+++ b/src/northbridge/intel/broadwell/systemagent.c
@@ -1,19 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <console/console.h>
-#include <acpi/acpi.h>
#include <device/pci_ops.h>
-#include <stdint.h>
-#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <intelblocks/power_limit.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <cpu/intel/broadwell/broadwell.h>
-#include <southbridge/intel/wildcatpoint/iomap.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
-#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
u8 systemagent_revision(void)
@@ -35,419 +26,3 @@
/* Bit 0 is lock bit, not part of address */
return pci_read_config32(sa_dev, BGSM) & ~1;
}
-
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
- u32 *len)
-{
- u32 pciexbar_reg;
-
- *base = 0;
- *len = 0;
-
- pciexbar_reg = pci_read_config32(dev, index);
-
- if (!(pciexbar_reg & (1 << 0)))
- return 0;
-
- switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28));
- *len = 256 * 1024 * 1024;
- return 1;
- case 1: // 128M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28)|(1 << 27));
- *len = 128 * 1024 * 1024;
- return 1;
- case 2: // 64M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28)|(1 << 27)|(1 << 26));
- *len = 64 * 1024 * 1024;
- return 1;
- }
-
- return 0;
-}
-
-static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 bar;
-
- bar = pci_read_config32(dev, index);
-
- /* If not enabled don't report it. */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit. */
- *base = bar & ~1;
-
- return 1;
-}
-
-/* There are special BARs that actually are programmed in the MCHBAR. These
- * Intel special features, but they do consume resources that need to be
- * accounted for. */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
- u32 *len)
-{
- u32 bar;
-
- bar = MCHBAR32(index);
-
- /* If not enabled don't report it. */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit. */
- *base = bar & ~1;
-
- return 1;
-}
-
-struct fixed_mmio_descriptor {
- unsigned int index;
- u32 size;
- int (*get_resource)(struct device *dev, unsigned int index,
- u32 *base, u32 *size);
- const char *description;
-};
-
-struct fixed_mmio_descriptor mc_fixed_resources[] = {
- { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
- { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
- { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
- { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
- { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
- { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
-};
-
-/*
- * Add all known fixed MMIO ranges that hang off the host bridge/memory
- * controller device.
- */
-static void mc_add_fixed_mmio_resources(struct device *dev)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
- u32 base;
- u32 size;
- struct resource *resource;
- unsigned int index;
-
- size = mc_fixed_resources[i].size;
- index = mc_fixed_resources[i].index;
- if (!mc_fixed_resources[i].get_resource(dev, index,
- &base, &size))
- continue;
-
- resource = new_resource(dev, mc_fixed_resources[i].index);
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
- resource->base = base;
- resource->size = size;
- printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
- __func__, mc_fixed_resources[i].description, index,
- (unsigned long)base, (unsigned long)(base + size - 1));
- }
-}
-
-/* Host Memory Map:
- *
- * +--------------------------+ TOUUD
- * | |
- * +--------------------------+ 4GiB
- * | PCI Address Space |
- * +--------------------------+ TOLUD (also maps into MC address space)
- * | iGD |
- * +--------------------------+ BDSM
- * | GTT |
- * +--------------------------+ BGSM
- * | TSEG |
- * +--------------------------+ TSEGMB
- * | Usage DRAM |
- * +--------------------------+ 0
- *
- * Some of the base registers above can be equal making the size of those
- * regions 0. The reason is because the memory controller internally subtracts
- * the base registers from each other to determine sizes of the regions. In
- * other words, the memory map is in a fixed order no matter what.
- */
-
-struct map_entry {
- int reg;
- int is_64_bit;
- int is_limit;
- const char *description;
-};
-
-static void read_map_entry(struct device *dev, struct map_entry *entry,
- uint64_t *result)
-{
- uint64_t value;
- uint64_t mask;
-
- /* All registers are on a 1MiB granularity. */
- mask = ((1ULL<<20)-1);
- mask = ~mask;
-
- value = 0;
-
- if (entry->is_64_bit) {
- value = pci_read_config32(dev, entry->reg + 4);
- value <<= 32;
- }
-
- value |= pci_read_config32(dev, entry->reg);
- value &= mask;
-
- if (entry->is_limit)
- value |= ~mask;
-
- *result = value;
-}
-
-#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
- { \
- .reg = reg_, \
- .is_64_bit = is_64_, \
- .is_limit = is_limit_, \
- .description = desc_, \
- }
-
-#define MAP_ENTRY_BASE_64(reg_, desc_) \
- MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
- MAP_ENTRY(reg_, 1, 1, desc_)
-#define MAP_ENTRY_BASE_32(reg_, desc_) \
- MAP_ENTRY(reg_, 0, 0, desc_)
-
-enum {
- TOM_REG,
- TOUUD_REG,
- MESEG_BASE_REG,
- MESEG_LIMIT_REG,
- REMAP_BASE_REG,
- REMAP_LIMIT_REG,
- TOLUD_REG,
- BGSM_REG,
- BDSM_REG,
- TSEG_REG,
- // Must be last.
- NUM_MAP_ENTRIES
-};
-
-static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
- [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
- [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
- [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
- [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
- [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
- [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
- [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
- [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
- [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
- [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
-};
-
-static void mc_read_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++)
- read_map_entry(dev, &memory_map[i], &values[i]);
-}
-
-static void mc_report_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
- printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
- memory_map[i].description, values[i]);
- }
- /* One can validate the BDSM and BGSM against the GGC. */
- printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
-}
-
-static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
-{
- unsigned long base_k, size_k;
- unsigned long touud_k;
- unsigned long index;
- struct resource *resource;
- uint64_t mc_values[NUM_MAP_ENTRIES];
- unsigned long dpr_size = 0;
- u32 dpr_reg;
- struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-
- /* Read in the MAP registers and report their values. */
- mc_read_map_entries(dev, &mc_values[0]);
- mc_report_map_entries(dev, &mc_values[0]);
-
- /*
- * DMA Protected Range can be reserved below TSEG for PCODE patch
- * or TXT/BootGuard related data. Rather than report a base address
- * the DPR register reports the TOP of the region, which is the same
- * as TSEG base. The region size is reported in MiB in bits 11:4.
- */
- dpr_reg = pci_read_config32(sa_dev, DPR);
- if (dpr_reg & DPR_EPM) {
- dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
- printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
- }
-
- /*
- * These are the host memory ranges that should be added:
- * - 0 -> 0xa0000: cacheable
- * - 0xc0000 -> TSEG : cacheable
- * - TESG -> BGSM: cacheable with standard MTRRs and reserved
- * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
- * - 4GiB -> TOUUD: cacheable
- *
- * The default SMRAM space is reserved so that the range doesn't
- * have to be saved during S3 Resume. Once marked reserved the OS
- * cannot use the memory. This is a bit of an odd place to reserve
- * the region, but the CPU devices don't have dev_ops->read_resources()
- * called on them.
- *
- * The range 0xa0000 -> 0xc0000 does not have any resources
- * associated with it to handle legacy VGA memory. If this range
- * is not omitted the mtrr code will setup the area as cacheable
- * causing VGA access to not work.
- *
- * The TSEG region is mapped as cacheable so that one can perform
- * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
- * precedence over the existing MTRRs covering this region.
- *
- * It should be noted that cacheable entry types need to be added in
- * order. The reason is that the current MTRR code assumes this and
- * falls over itself if it isn't.
- *
- * The resource index starts low and should not meet or exceed
- * PCI_BASE_ADDRESS_0.
- */
- index = *resource_cnt;
-
- /* 0 - > 0xa0000 */
- base_k = 0;
- size_k = (0xa0000 >> 10) - base_k;
- ram_resource(dev, index++, base_k, size_k);
-
- /* 0xc0000 -> TSEG - DPR */
- base_k = 0xc0000 >> 10;
- size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
- size_k -= dpr_size >> 10;
- ram_resource(dev, index++, base_k, size_k);
-
- /* TSEG - DPR -> BGSM */
- resource = new_resource(dev, index++);
- resource->base = mc_values[TSEG_REG] - dpr_size;
- resource->size = mc_values[BGSM_REG] - resource->base;
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
-
- /* BGSM -> TOLUD */
- resource = new_resource(dev, index++);
- resource->base = mc_values[BGSM_REG];
- resource->size = mc_values[TOLUD_REG] - resource->base;
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
-
- /* 4GiB -> TOUUD */
- base_k = 4096 * 1024; /* 4GiB */
- touud_k = mc_values[TOUUD_REG] >> 10;
- size_k = touud_k - base_k;
- if (touud_k > base_k)
- ram_resource(dev, index++, base_k, size_k);
-
- /* Reserve everything between A segment and 1MB:
- *
- * 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xfffff: RAM
- */
- mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
- reserved_ram_resource(dev, index++, (0xc0000 >> 10),
- (0x100000 - 0xc0000) >> 10);
-
- if (CONFIG(CHROMEOS))
- chromeos_reserve_ram_oops(dev, index++);
-
- *resource_cnt = index;
-}
-
-static void systemagent_read_resources(struct device *dev)
-{
- int index = 0;
- const bool vtd_capable =
- !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
-
- /* Read standard PCI resources. */
- pci_dev_read_resources(dev);
-
- /* Add all fixed MMIO resources. */
- mc_add_fixed_mmio_resources(dev);
-
- /* Add VT-d MMIO resources if capable */
- if (vtd_capable) {
- mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
- GFXVT_BASE_SIZE / KiB);
- mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
- VTVC0_BASE_SIZE / KiB);
- }
-
- /* Calculate and add DRAM resources. */
- mc_add_dram_resources(dev, &index);
-}
-
-static void systemagent_init(struct device *dev)
-{
- struct soc_power_limits_config *config;
- u8 bios_reset_cpl, pair;
-
- /* Enable Power Aware Interrupt Routing */
- pair = MCHBAR8(MCH_PAIR);
- pair &= ~0x7; /* Clear 2:0 */
- pair |= 0x4; /* Fixed Priority */
- MCHBAR8(MCH_PAIR) = pair;
-
- /*
- * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
- * that BIOS has initialized memory and power management
- */
- bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
- bios_reset_cpl |= 3;
- MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
- printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
-
- /* Configure turbo power limits 1ms after reset complete bit */
- mdelay(1);
- config = config_of_soc();
- set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config);
-}
-
-static struct device_operations systemagent_ops = {
- .read_resources = systemagent_read_resources,
- .acpi_fill_ssdt = generate_cpu_entries,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = systemagent_init,
- .ops_pci = &broadwell_pci_ops,
-};
-
-static const unsigned short systemagent_ids[] = {
- 0x0a04, /* Haswell ULT */
- 0x1604, /* Broadwell-U/Y */
- 0x1610, /* Broadwell-H Desktop */
- 0x1614, /* Broadwell-H Mobile */
- 0
-};
-
-static const struct pci_driver systemagent_driver __pci_driver = {
- .ops = &systemagent_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = systemagent_ids
-};
diff --git a/src/southbridge/intel/wildcatpoint/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h
index 618b627..c747a4b 100644
--- a/src/southbridge/intel/wildcatpoint/acpi.h
+++ b/src/southbridge/intel/wildcatpoint/acpi.h
@@ -12,9 +12,8 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
-void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
-unsigned long northbridge_write_acpi_tables(const struct device *dev,
- unsigned long current, struct acpi_rsdp *rsdp);
+void acpi_fill_in_fadt(acpi_fadt_t *fadt);
+
#endif
diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c
index e8cb8aa..00ad55f 100644
--- a/src/southbridge/intel/wildcatpoint/early_pch.c
+++ b/src/southbridge/intel/wildcatpoint/early_pch.c
@@ -11,7 +11,7 @@
#include <southbridge/intel/wildcatpoint/pci_devs.h>
#include <southbridge/intel/wildcatpoint/pm.h>
#include <southbridge/intel/wildcatpoint/rcba.h>
-#include <northbridge/intel/broadwell/romstage.h>
+#include <southbridge/intel/wildcatpoint/romstage.h>
#include <southbridge/intel/wildcatpoint/smbus.h>
#include <southbridge/intel/wildcatpoint/soc_chip.h>
diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c
index 6f4d226..0b43cc2 100644
--- a/src/southbridge/intel/wildcatpoint/early_smbus.c
+++ b/src/southbridge/intel/wildcatpoint/early_smbus.c
@@ -6,7 +6,6 @@
#include <southbridge/intel/wildcatpoint/iomap.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
#include <southbridge/intel/wildcatpoint/smbus.h>
-#include <northbridge/intel/broadwell/romstage.h>
static const struct reg_script smbus_init_script[] = {
/* Set SMBUS I/O base address */
diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c
index b7f1fe3..e1b2bec 100644
--- a/src/southbridge/intel/wildcatpoint/lpc.c
+++ b/src/southbridge/intel/wildcatpoint/lpc.c
@@ -15,6 +15,7 @@
#include <cbmem.h>
#include <reg_script.h>
#include <string.h>
+#include <southbridge/intel/wildcatpoint/acpi.h>
#include <southbridge/intel/wildcatpoint/gpio.h>
#include <southbridge/intel/wildcatpoint/iobp.h>
#include <southbridge/intel/wildcatpoint/iomap.h>
@@ -595,6 +596,146 @@
}
}
+void acpi_init_gnvs(global_nvs_t *gnvs)
+{
+ /* Set unknown wake source */
+ gnvs->pm1i = -1;
+
+ /* CPU core count */
+ gnvs->pcnt = dev_count_cpu();
+
+#if CONFIG(CONSOLE_CBMEM)
+ /* Update the mem console pointer. */
+ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
+#endif
+
+#if CONFIG(CHROMEOS)
+ /* Initialize Verified Boot data */
+ chromeos_init_chromeos_acpi(&(gnvs->chromeos));
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+ gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+#endif
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+}
+
+void acpi_fill_in_fadt(acpi_fadt_t *fadt)
+{
+ const uint16_t pmbase = ACPI_BASE_ADDRESS;
+
+ fadt->sci_int = acpi_sci_irq();
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase + PM1_STS;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + PM2_CNT;
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ fadt->gpe0_blk = pmbase + GPE0_STS(0);
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 32;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = 6;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ /*
+ * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
+ * The bit_width field intentionally overflows here.
+ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
+ * seems to work fine on Linux 5.0 and Windows 10.
+ */
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+}
+
static unsigned long broadwell_write_acpi_tables(const struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
diff --git a/src/southbridge/intel/wildcatpoint/pch.h b/src/southbridge/intel/wildcatpoint/pch.h
index 59b5b18..dfe3560 100644
--- a/src/southbridge/intel/wildcatpoint/pch.h
+++ b/src/southbridge/intel/wildcatpoint/pch.h
@@ -29,5 +29,6 @@
int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id);
void pch_disable_devfn(struct device *dev);
+void broadwell_pch_enable_dev(struct device *dev);
#endif
diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c
index 8522caa..419fd4e 100644
--- a/src/southbridge/intel/wildcatpoint/power_state.c
+++ b/src/southbridge/intel/wildcatpoint/power_state.c
@@ -13,7 +13,7 @@
#include <southbridge/intel/wildcatpoint/lpc.h>
#include <southbridge/intel/wildcatpoint/pci_devs.h>
#include <southbridge/intel/wildcatpoint/pm.h>
-#include <northbridge/intel/broadwell/romstage.h>
+#include <southbridge/intel/wildcatpoint/romstage.h>
static struct chipset_power_state power_state;
diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c
index 8859261..5d8ec0e 100644
--- a/src/southbridge/intel/wildcatpoint/ramstage.c
+++ b/src/southbridge/intel/wildcatpoint/ramstage.c
@@ -4,6 +4,7 @@
#include <cbmem.h>
#include <device/device.h>
#include <string.h>
+#include <northbridge/intel/broadwell/refcode.h>
#include <southbridge/intel/wildcatpoint/nvs.h>
#include <southbridge/intel/wildcatpoint/pm.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
diff --git a/src/southbridge/intel/wildcatpoint/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h
index b50cd19..1343dad 100644
--- a/src/southbridge/intel/wildcatpoint/ramstage.h
+++ b/src/southbridge/intel/wildcatpoint/ramstage.h
@@ -7,14 +7,6 @@
#include <southbridge/intel/wildcatpoint/soc_chip.h>
void broadwell_init_pre_device(void *chip_info);
-void broadwell_init_cpus(struct device *dev);
-void broadwell_pch_enable_dev(struct device *dev);
-
-#if CONFIG(HAVE_REFCODE_BLOB)
-void broadwell_run_reference_code(void);
-#else
-static inline void broadwell_run_reference_code(void) { }
-#endif
extern struct pci_operations broadwell_pci_ops;
diff --git a/src/southbridge/intel/wildcatpoint/romstage.h b/src/southbridge/intel/wildcatpoint/romstage.h
new file mode 100644
index 0000000..d780e99
--- /dev/null
+++ b/src/southbridge/intel/wildcatpoint/romstage.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _WILDCATPOINT_ROMSTAGE_H_
+#define _WILDCATPOINT_ROMSTAGE_H_
+
+struct chipset_power_state;
+struct chipset_power_state *fill_power_state(void);
+
+void pch_early_init(void);
+void pch_uart_init(void);
+void intel_early_me_status(void);
+
+#endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/41942
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d
Gerrit-Change-Number: 41942
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1
7
30 Oct '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42620 )
Change subject: broadwell: Align with haswell
......................................................................
broadwell: Align with haswell
Tested with BUILD_TIMELESS=1, google/buddy does not change.
Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/cpu/intel/broadwell/broadwell_init.c
M src/cpu/intel/broadwell/smmrelocate.c
M src/northbridge/intel/broadwell/acpi.c
M src/northbridge/intel/broadwell/bootblock.c
M src/northbridge/intel/broadwell/minihd.c
M src/northbridge/intel/broadwell/northbridge.c
M src/northbridge/intel/broadwell/report_platform.c
M src/southbridge/intel/wildcatpoint/bootblock.c
M src/southbridge/intel/wildcatpoint/ehci.c
M src/southbridge/intel/wildcatpoint/gpio.c
M src/southbridge/intel/wildcatpoint/hda.c
M src/southbridge/intel/wildcatpoint/iobp.c
M src/southbridge/intel/wildcatpoint/lpc.c
M src/southbridge/intel/wildcatpoint/me.c
M src/southbridge/intel/wildcatpoint/me_status.c
M src/southbridge/intel/wildcatpoint/pch.c
M src/southbridge/intel/wildcatpoint/pcie.c
M src/southbridge/intel/wildcatpoint/pmutil.c
M src/southbridge/intel/wildcatpoint/serialio.c
M src/southbridge/intel/wildcatpoint/smbus.c
M src/southbridge/intel/wildcatpoint/smi.c
M src/southbridge/intel/wildcatpoint/smihandler.c
M src/southbridge/intel/wildcatpoint/xhci.c
23 files changed, 457 insertions(+), 477 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42620/1
diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c
index 2ad6aea..5d26232 100644
--- a/src/cpu/intel/broadwell/broadwell_init.c
+++ b/src/cpu/intel/broadwell/broadwell_init.c
@@ -431,7 +431,7 @@
/* Clear out pending MCEs */
configure_mca();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c
index 2a307ef..5599c0b 100644
--- a/src/cpu/intel/broadwell/smmrelocate.c
+++ b/src/cpu/intel/broadwell/smmrelocate.c
@@ -12,10 +12,10 @@
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
-#include <smp/node.h>
-#include <cpu/intel/broadwell/broadwell.h>
-#include <southbridge/intel/wildcatpoint/pci_devs.h>
#include <northbridge/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/pci_devs.h>
+#include <smp/node.h>
+#include "broadwell.h"
static void update_save_state(int cpu, uintptr_t curr_smbase,
@@ -141,6 +141,7 @@
{
uintptr_t tseg_base;
size_t tseg_size;
+
u32 prmrr_base;
u32 prmrr_size;
int phys_bits;
@@ -254,11 +255,11 @@
void smm_lock(void)
{
- struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* LOCK the SMM memory window and enable normal SMM.
* After running this function, only a full reset can
* make the SMM registers writable again.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+ pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM,
+ D_LCK | G_SMRAME | C_BASE_SEG);
}
diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
index df08537..1627074 100644
--- a/src/northbridge/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -25,8 +25,7 @@
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
- if (igfx_dev && igfx_dev->enabled && gfxvtbar
- && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+ if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
@@ -45,16 +44,16 @@
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
+
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current,
- DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
- current += acpi_create_dmar_ds_ioapic(current,
- 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
+ PCH_IOAPIC_PCI_SLOT, 0);
+
size_t i;
for (i = 0; i < 8; ++i)
- current += acpi_create_dmar_ds_msi_hpet(current,
- 0, PCH_HPET_PCI_BUS,
- PCH_HPET_PCI_SLOT, i);
+ current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
+ PCH_HPET_PCI_SLOT, i);
acpi_dmar_drhd_fixup(tmp, current);
}
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
index 89ff992..d661f57 100644
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ b/src/northbridge/intel/broadwell/bootblock.c
@@ -10,16 +10,14 @@
uint32_t reg;
/*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+ * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
+ * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent
+ * non-explicit config accesses use MCFG. This code also assumes that
+ * bootblock_northbridge_init() is the first thing called in the non-asm
+ * boot block code. The final assumption is that no assembly code is using
+ * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = 0;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c
index 7a93b9a..9df1047 100644
--- a/src/northbridge/intel/broadwell/minihd.c
+++ b/src/northbridge/intel/broadwell/minihd.c
@@ -12,30 +12,30 @@
static const u32 minihd_verb_table[] = {
/* coreboot specific header */
- 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD
- 0x80860101, // Subsystem ID
- 0x00000004, // Number of jacks
+ 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of jacks */
/* Enable 3rd Pin and Converter Widget */
0x00878101,
/* Pin Widget 5 - PORT B */
- 0x00571C10,
- 0x00571D00,
- 0x00571E56,
- 0x00571F18,
+ 0x00571c10,
+ 0x00571d00,
+ 0x00571e56,
+ 0x00571f18,
/* Pin Widget 6 - PORT C */
- 0x00671C20,
- 0x00671D00,
- 0x00671E56,
- 0x00671F18,
+ 0x00671c20,
+ 0x00671d00,
+ 0x00671e56,
+ 0x00671f18,
/* Pin Widget 7 - PORT D */
- 0x00771C30,
- 0x00771D00,
- 0x00771E56,
- 0x00771F18,
+ 0x00771c30,
+ 0x00771d00,
+ 0x00771e56,
+ 0x00771f18,
/* Disable 3rd Pin and Converter Widget */
0x00878100,
@@ -48,8 +48,8 @@
static void minihd_init(struct device *dev)
{
struct resource *res;
- u8 *base;
u32 reg32;
+ u8 *base;
int codec_mask, i;
/* Find base address */
@@ -80,8 +80,7 @@
if (codec_mask) {
for (i = 3; i >= 0; i--) {
if (codec_mask & (1 << i))
- hda_codec_init(base, i,
- sizeof(minihd_verb_table),
+ hda_codec_init(base, i, sizeof(minihd_verb_table),
minihd_verb_table);
}
}
@@ -92,10 +91,10 @@
}
static struct device_operations minihd_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &minihd_init,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = minihd_init,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
index 5122fed..dab541a 100644
--- a/src/northbridge/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -16,8 +16,7 @@
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
- u32 *len)
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;
@@ -52,35 +51,31 @@
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
- u32 bar;
+ u32 bar = pci_read_config32(dev, index);
- bar = pci_read_config32(dev, index);
-
- /* If not enabled don't report it. */
+ /* If not enabled don't report it */
if (!(bar & 0x1))
return 0;
- /* Knock down the enable bit. */
+ /* Knock down the enable bit */
*base = bar & ~1;
return 1;
}
-/* There are special BARs that actually are programmed in the MCHBAR. These
- * Intel special features, but they do consume resources that need to be
- * accounted for. */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
- u32 *len)
+/*
+ * There are special BARs that actually are programmed in the MCHBAR. These Intel special
+ * features, but they do consume resources that need to be accounted for.
+ */
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
- u32 bar;
+ u32 bar = MCHBAR32(index);
- bar = MCHBAR32(index);
-
- /* If not enabled don't report it. */
+ /* If not enabled don't report it */
if (!(bar & 0x1))
return 0;
- /* Knock down the enable bit. */
+ /* Knock down the enable bit */
*base = bar & ~1;
return 1;
@@ -89,8 +84,7 @@
struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
- int (*get_resource)(struct device *dev, unsigned int index,
- u32 *base, u32 *size);
+ int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
const char *description;
};
@@ -103,10 +97,7 @@
{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
};
-/*
- * Add all known fixed MMIO ranges that hang off the host bridge/memory
- * controller device.
- */
+/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
static void mc_add_fixed_mmio_resources(struct device *dev)
{
int i;
@@ -119,14 +110,13 @@
size = mc_fixed_resources[i].size;
index = mc_fixed_resources[i].index;
- if (!mc_fixed_resources[i].get_resource(dev, index,
- &base, &size))
+ if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
continue;
resource = new_resource(dev, mc_fixed_resources[i].index);
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+
resource->base = base;
resource->size = size;
printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
@@ -151,10 +141,10 @@
* | Usage DRAM |
* +--------------------------+ 0
*
- * Some of the base registers above can be equal making the size of those
- * regions 0. The reason is because the memory controller internally subtracts
- * the base registers from each other to determine sizes of the regions. In
- * other words, the memory map is in a fixed order no matter what.
+ * Some of the base registers above can be equal, making the size of the regions within 0.
+ * This is because the memory controller internally subtracts the base registers from each
+ * other to determine sizes of the regions. In other words, the memory map regions are always
+ * in a fixed order, no matter what sizes they have.
*/
struct map_entry {
@@ -164,14 +154,13 @@
const char *description;
};
-static void read_map_entry(struct device *dev, struct map_entry *entry,
- uint64_t *result)
+static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
{
uint64_t value;
uint64_t mask;
- /* All registers are on a 1MiB granularity. */
- mask = ((1ULL<<20)-1);
+ /* All registers have a 1MiB granularity */
+ mask = ((1ULL << 20) - 1);
mask = ~mask;
value = 0;
@@ -198,12 +187,9 @@
.description = desc_, \
}
-#define MAP_ENTRY_BASE_64(reg_, desc_) \
- MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
- MAP_ENTRY(reg_, 1, 1, desc_)
-#define MAP_ENTRY_BASE_32(reg_, desc_) \
- MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
enum {
TOM_REG,
@@ -216,28 +202,29 @@
BGSM_REG,
BDSM_REG,
TSEG_REG,
- // Must be last.
- NUM_MAP_ENTRIES
+ /* Must be last */
+ NUM_MAP_ENTRIES,
};
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
- [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
- [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
- [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
+ [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
+ [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+ [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
[MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
- [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
+ [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
[REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
- [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
- [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
- [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
- [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
+ [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+ [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+ [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+ [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), /* FIXME: typo */
};
static void mc_read_map_entries(struct device *dev, uint64_t *values)
{
int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++)
+ for (i = 0; i < NUM_MAP_ENTRIES; i++) {
read_map_entry(dev, &memory_map[i], &values[i]);
+ }
}
static void mc_report_map_entries(struct device *dev, uint64_t *values)
@@ -247,22 +234,20 @@
printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
memory_map[i].description, values[i]);
}
- /* One can validate the BDSM and BGSM against the GGC. */
+ /* One can validate the BDSM and BGSM against the GGC */
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
}
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{
- unsigned long base_k, size_k;
- unsigned long touud_k;
- unsigned long index;
+ unsigned long base_k, size_k, touud_k, index;
struct resource *resource;
uint64_t mc_values[NUM_MAP_ENTRIES];
unsigned long dpr_size = 0;
u32 dpr_reg;
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- /* Read in the MAP registers and report their values. */
+ /* Read in the MAP registers and report their values */
mc_read_map_entries(dev, &mc_values[0]);
mc_report_map_entries(dev, &mc_values[0]);
@@ -280,33 +265,29 @@
/*
* These are the host memory ranges that should be added:
- * - 0 -> 0xa0000: cacheable
- * - 0xc0000 -> TSEG : cacheable
- * - TESG -> BGSM: cacheable with standard MTRRs and reserved
- * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
- * - 4GiB -> TOUUD: cacheable
+ * - 0 -> 0xa0000: cacheable
+ * - 0xc0000 -> TSEG: cacheable
+ * - TSEG -> BGSM: cacheable with standard MTRRs and reserved
+ * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
+ * - 4GiB -> TOUUD: cacheable
*
- * The default SMRAM space is reserved so that the range doesn't
- * have to be saved during S3 Resume. Once marked reserved the OS
- * cannot use the memory. This is a bit of an odd place to reserve
- * the region, but the CPU devices don't have dev_ops->read_resources()
- * called on them.
+ * The default SMRAM space is reserved so that the range doesn't have to be saved
+ * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a
+ * bit of an odd place to reserve the region, but the CPU devices don't have
+ * dev_ops->read_resources() called on them.
*
- * The range 0xa0000 -> 0xc0000 does not have any resources
- * associated with it to handle legacy VGA memory. If this range
- * is not omitted the mtrr code will setup the area as cacheable
- * causing VGA access to not work.
+ * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to
+ * handle legacy VGA memory. If this range is not omitted the mtrr code will setup
+ * the area as cacheable, causing VGA access to not work.
*
- * The TSEG region is mapped as cacheable so that one can perform
- * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
- * precedence over the existing MTRRs covering this region.
+ * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation
+ * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing
+ * MTRRs covering this region.
*
- * It should be noted that cacheable entry types need to be added in
- * order. The reason is that the current MTRR code assumes this and
- * falls over itself if it isn't.
+ * It should be noted that cacheable entry types need to be added in order. The reason
+ * is that the current MTRR code assumes this and falls over itself if it isn't.
*
- * The resource index starts low and should not meet or exceed
- * PCI_BASE_ADDRESS_0.
+ * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0.
*/
index = *resource_cnt;
@@ -346,12 +327,11 @@
/* Reserve everything between A segment and 1MB:
*
- * 0xa0000 - 0xbffff: legacy VGA
+ * 0xa0000 - 0xbffff: Legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
- reserved_ram_resource(dev, index++, (0xc0000 >> 10),
- (0x100000 - 0xc0000) >> 10);
+ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS))
chromeos_reserve_ram_oops(dev, index++);
@@ -359,27 +339,24 @@
*resource_cnt = index;
}
-static void systemagent_read_resources(struct device *dev)
+static void mc_read_resources(struct device *dev)
{
int index = 0;
- const bool vtd_capable =
- !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+ const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
- /* Read standard PCI resources. */
+ /* Read standard PCI resources */
pci_dev_read_resources(dev);
- /* Add all fixed MMIO resources. */
+ /* Add all fixed MMIO resources */
mc_add_fixed_mmio_resources(dev);
- /* Add VT-d MMIO resources if capable */
+ /* Add VT-d MMIO resources, if capable */
if (vtd_capable) {
- mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
- GFXVT_BASE_SIZE / KiB);
- mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
- VTVC0_BASE_SIZE / KiB);
+ mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
+ mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
}
- /* Calculate and add DRAM resources. */
+ /* Calculate and add DRAM resources */
mc_add_dram_resources(dev, &index);
}
@@ -395,7 +372,7 @@
MCHBAR8(MCH_PAIR) = pair;
/*
- * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+ * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialized memory and power management
*/
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
@@ -410,7 +387,7 @@
}
static struct device_operations systemagent_ops = {
- .read_resources = systemagent_read_resources,
+ .read_resources = mc_read_resources,
.acpi_fill_ssdt = generate_cpu_entries,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 95d9c99..c963081 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -85,7 +85,7 @@
strcpy(cpu_string, "Platform info not available");
} else {
u32 *p = (u32 *)cpu_string;
- for (i = 2; i <= 4 ; i++) {
+ for (i = 2; i <= 4; i++) {
cpuidr = cpuid(index + i);
*p++ = cpuidr.eax;
*p++ = cpuidr.ebx;
diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c
index 572ea09..55bb1c3 100644
--- a/src/southbridge/intel/wildcatpoint/bootblock.c
+++ b/src/southbridge/intel/wildcatpoint/bootblock.c
@@ -31,7 +31,7 @@
static void enable_port80_on_lpc(void)
{
/* Enable port 80 POST on LPC. The chipset does this by default,
- * but it doesn't appear to hurt anything. */
+ but it doesn't appear to hurt anything. */
u32 gcs = RCBA32(GCS);
gcs = gcs & ~0x4;
RCBA32(GCS) = gcs;
diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c
index 81ad62d..566b70f 100644
--- a/src/southbridge/intel/wildcatpoint/ehci.c
+++ b/src/southbridge/intel/wildcatpoint/ehci.c
@@ -8,8 +8,7 @@
#include <southbridge/intel/wildcatpoint/ehci.h>
#include <southbridge/intel/wildcatpoint/pch.h>
-static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c
index 62a7335..b0c0476 100644
--- a/src/southbridge/intel/wildcatpoint/gpio.c
+++ b/src/southbridge/intel/wildcatpoint/gpio.c
@@ -13,19 +13,19 @@
* this GPIO maps to. If this is not a PIRQ capable GPIO then
* it will return -1. The GPIO to PIRQ mapping is not linear.
*/
-static int gpio_to_pirq(int gpio)
+static int lp_gpio_to_pirq(int gpio)
{
switch (gpio) {
- case 8: return 0; /* PIRQI */
- case 9: return 1; /* PIRQJ */
- case 10: return 2; /* PIRQK */
- case 13: return 3; /* PIRQL */
- case 14: return 4; /* PIRQM */
- case 45: return 5; /* PIRQN */
- case 46: return 6; /* PIRQO */
- case 47: return 7; /* PIRQP */
- case 48: return 8; /* PIRQQ */
- case 49: return 9; /* PIRQR */
+ case 8: return 0; /* PIRQI */
+ case 9: return 1; /* PIRQJ */
+ case 10: return 2; /* PIRQK */
+ case 13: return 3; /* PIRQL */
+ case 14: return 4; /* PIRQM */
+ case 45: return 5; /* PIRQN */
+ case 46: return 6; /* PIRQO */
+ case 47: return 7; /* PIRQP */
+ case 48: return 8; /* PIRQQ */
+ case 49: return 9; /* PIRQR */
case 50: return 10; /* PIRQS */
case 51: return 11; /* PIRQT */
case 52: return 12; /* PIRQU */
@@ -36,9 +36,10 @@
};
}
-void init_gpios(const struct gpio_config config[])
+void init_gpios(const struct gpio_config map[])
{
- const struct gpio_config *entry;
+ const u16 gpio_base = GPIO_BASE_ADDRESS;
+ const struct gpio_config *config;
u32 owner[3] = {0};
u32 route[3] = {0};
u32 irqen[3] = {0};
@@ -47,56 +48,58 @@
u16 pirq2apic = 0;
int set, bit, gpio = 0;
- for (entry = config; entry->conf0 != GPIO_LIST_END; entry++, gpio++) {
+ for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) {
if (gpio > MAX_GPIO_NUMBER)
break;
/* Setup Configuration registers 1 and 2 */
- outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio));
- outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio));
+ outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio));
+ outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio));
/* Determine set and bit based on GPIO number */
set = gpio >> 5;
bit = gpio % 32;
/* Apply settings to set specific bits */
- owner[set] |= entry->owner << bit;
- route[set] |= entry->route << bit;
- irqen[set] |= entry->irqen << bit;
- reset[set] |= entry->reset << bit;
+ owner[set] |= config->owner << bit;
+ route[set] |= config->route << bit;
+ irqen[set] |= config->irqen << bit;
+ reset[set] |= config->reset << bit;
if (set == 0)
- blink |= entry->blink << bit;
+ blink |= config->blink << bit;
/* PIRQ to IO-APIC map */
- if (entry->pirq == GPIO_PIRQ_APIC_ROUTE) {
- set = gpio_to_pirq(gpio);
+ if (config->pirq == GPIO_PIRQ_APIC_ROUTE) {
+ set = lp_gpio_to_pirq(gpio);
if (set >= 0)
pirq2apic |= 1 << set;
}
}
for (set = 0; set <= 2; set++) {
- outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set));
- outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set));
- outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set));
- outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set));
+ outl(owner[set], gpio_base + GPIO_OWNER(set));
+ outl(route[set], gpio_base + GPIO_ROUTE(set));
+ outl(irqen[set], gpio_base + GPIO_IRQ_IE(set));
+ outl(reset[set], gpio_base + GPIO_RESET(set));
}
- outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK);
- outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN);
+ outl(blink, gpio_base + GPIO_BLINK);
+ outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN);
}
int get_gpio(int gpio_num)
{
+ const u16 gpio_base = GPIO_BASE_ADDRESS;
+
if (gpio_num > MAX_GPIO_NUMBER)
return 0;
- return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
+ return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
}
/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned int get_gpios(const int *gpio_num_array)
@@ -116,15 +119,16 @@
void set_gpio(int gpio_num, int value)
{
+ const u16 gpio_base = GPIO_BASE_ADDRESS;
u32 conf0;
if (gpio_num > MAX_GPIO_NUMBER)
return;
- conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+ conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num));
conf0 &= ~GPO_LEVEL_MASK;
conf0 |= value << GPO_LEVEL_SHIFT;
- outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+ outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num));
}
int gpio_is_native(int gpio_num)
diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c
index 0dbe6cd..68e180d 100644
--- a/src/southbridge/intel/wildcatpoint/hda.c
+++ b/src/southbridge/intel/wildcatpoint/hda.c
@@ -2,16 +2,22 @@
#include <console/console.h>
#include <device/device.h>
-#include <device/azalia_device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
+#include <device/azalia_device.h>
#include <soc/intel/common/hda_verb.h>
#include <southbridge/intel/wildcatpoint/pch.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <southbridge/intel/wildcatpoint/rcba.h>
+/* FIXME: For alignment with Haswell only */
+static inline bool pch_is_lp(void)
+{
+ return true;
+}
+
static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -19,27 +25,31 @@
/* Can support up to 4 codecs */
for (i = 3; i >= 0; i--) {
if (codec_mask & (1 << i))
- hda_codec_init(base, i,
- cim_verb_data_size,
- cim_verb_data);
+ hda_codec_init(base, i, cim_verb_data_size, cim_verb_data);
}
if (pc_beep_verbs_size)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
-static void hda_pch_init(struct device *dev, u8 *base)
+static void azalia_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
u32 reg32;
- if (RCBA32(0x2030) & (1 << 31)) {
+ if (RCBA32(0x2030) & (1UL << 31)) {
reg32 = pci_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01;
reg32 |= (1 << 25);
reg32 |= RCBA32(0x2030) & 0xfe;
pci_write_config32(dev, 0x120, reg32);
+
+ if (!pch_is_lp()) {
+ reg16 = pci_read_config16(dev, 0x78);
+ reg16 &= ~(1 << 11);
+ pci_write_config16(dev, 0x78, reg16);
+ }
} else
printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n");
@@ -48,37 +58,66 @@
pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit
- if (pci_read_config32(dev, 0x120) & ((1 << 24) |
- (1 << 25) | (1 << 26))) {
+ if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) {
reg32 = pci_read_config32(dev, 0x120);
- reg32 &= ~(1 << 31);
+ if (pch_is_lp())
+ reg32 &= ~(1UL << 31);
+ else
+ reg32 |= (1UL << 31);
pci_write_config32(dev, 0x120, reg32);
}
+ /* FIXME: Haswell does this, but we don't on Broadwell, c.f. hda_enable() */
+#if 0
+ reg8 = pci_read_config8(dev, 0x43);
+ if (pch_is_lp())
+ reg8 &= ~(1 << 6);
+ else
+ reg8 |= (1 << 4);
+ pci_write_config8(dev, 0x43, reg8);
+#endif
+
+ if (!pch_is_lp()) {
+ reg32 = pci_read_config32(dev, 0xc0);
+ reg32 |= (1 << 17);
+ pci_write_config32(dev, 0xc0, reg32);
+ }
+
/* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4);
- reg32 |= (1 << 24);
+ if (pch_is_lp())
+ reg32 |= (1 << 24);
+ else
+ reg32 |= (1 << 14);
pci_write_config32(dev, 0xc4, reg32);
+ if (!pch_is_lp()) {
+ reg32 = pci_read_config32(dev, 0xd0);
+ reg32 &= ~(1UL << 31);
+ pci_write_config32(dev, 0xd0, reg32);
+ }
+
reg8 = pci_read_config8(dev, 0x40); // Audio Control
- reg8 |= 1; // Select HDA mode
+ reg8 |= 1; // Select Azalia mode
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
- reg16 = read32(base + 0x0012);
- reg16 |= (1 << 0);
- write32(base + 0x0012, reg16);
+ if (pch_is_lp()) {
+ reg16 = read32(base + 0x0012);
+ reg16 |= (1 << 0);
+ write32(base + 0x0012, reg16);
- /* disable Auto Voltage Detector */
- reg8 = pci_read_config8(dev, 0x42);
- reg8 |= (1 << 2);
- pci_write_config8(dev, 0x42, reg8);
+ /* disable Auto Voltage Detector */
+ reg8 = pci_read_config8(dev, 0x42);
+ reg8 |= (1 << 2);
+ pci_write_config8(dev, 0x42, reg8);
+ }
}
-static void hda_init(struct device *dev)
+static void azalia_init(struct device *dev)
{
u8 *base;
struct resource *res;
@@ -95,7 +134,7 @@
/* Set Bus Master */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- hda_pch_init(dev, base);
+ azalia_pch_init(dev, base);
codec_mask = hda_codec_detect(base);
@@ -134,11 +173,11 @@
}
static struct device_operations hda_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &hda_init,
- .enable = &hda_enable,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .enable = hda_enable,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c
index 3332e26..72cb111 100644
--- a/src/southbridge/intel/wildcatpoint/iobp.c
+++ b/src/southbridge/intel/wildcatpoint/iobp.c
@@ -91,8 +91,12 @@
/* Check for successful transaction */
status = RCBA16(IOBPS);
- if (status & IOBPS_TX_MASK)
+ if (status & IOBPS_TX_MASK) {
printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
+ //return;
+ }
+
+ //printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
}
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c
index 47d3e8f..11c962d 100644
--- a/src/southbridge/intel/wildcatpoint/lpc.c
+++ b/src/southbridge/intel/wildcatpoint/lpc.c
@@ -4,11 +4,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <device/pci_ops.h>
#include <option.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
-#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
@@ -31,6 +31,17 @@
#include <acpi/acpigen.h>
#include <southbridge/intel/common/rtc.h>
+/* FIXME: For alignment with Haswell only */
+static inline bool pch_is_lp(void)
+{
+ return true;
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
@@ -43,11 +54,11 @@
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-
- /* PCH-LP has 39 redirection entries */
- reg32 &= ~0x00ff0000;
- reg32 |= 0x00270000;
-
+ if (pch_is_lp()) {
+ /* PCH-LP has 39 redirection entries */
+ reg32 &= ~0x00ff0000;
+ reg32 |= 0x00270000;
+ }
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
@@ -67,7 +78,8 @@
PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
}
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+/*
+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
* 0x02 - 0010 = Reserved
@@ -103,6 +115,11 @@
pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ /*
+ * Eric Biederman once said we should let the OS do this.
+ * I am not so sure anymore he was right.
+ */
+
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
@@ -112,18 +129,10 @@
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
- case 1: /* INTA# */
- int_line = config->pirqa_routing;
- break;
- case 2: /* INTB# */
- int_line = config->pirqb_routing;
- break;
- case 3: /* INTC# */
- int_line = config->pirqc_routing;
- break;
- case 4: /* INTD# */
- int_line = config->pirqd_routing;
- break;
+ case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4: /* INTD# */ int_line = config->pirqd_routing; break;
}
if (!int_line)
@@ -141,7 +150,8 @@
config_t *config = config_of(dev);
int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
- /* Which state do we want to goto after g3 (power restored)?
+ /*
+ * Which state do we want to go to after G3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*
@@ -411,9 +421,8 @@
static void pch_set_acpi_mode(void)
{
- if (!acpi_is_wakeup_s3()) {
+ if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_ACPI_DISABLE);
- }
}
static void lpc_init(struct device *dev)
@@ -500,8 +509,7 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
- int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)
{
struct resource *res;
@@ -514,12 +522,11 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
- int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
- * device's default claim range add the resource.
+ * device's default, claim range and add the resource.
*/
if (reg_value & 1) {
u16 base = reg_value & 0xfffc;
@@ -540,8 +547,7 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */
- pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
- GPIO_BASE_SIZE, GPIO_BASE);
+ pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GPIO_BASE);
/* PMBASE */
pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
@@ -572,7 +578,7 @@
memset(gnvs, 0, sizeof(global_nvs_t));
}
-static void southcluster_inject_dsdt(const struct device *device)
+static void southbridge_inject_dsdt(const struct device *device)
{
global_nvs_t *gnvs;
@@ -641,13 +647,23 @@
fadt->gpe0_blk = pmbase + GPE0_STS(0);
fadt->gpe1_blk = 0;
- fadt->pm1_evt_len = 4;
+ /*
+ * Some of the lengths here are doubled. This is because they describe
+ * blocks containing two registers, where the size of each register
+ * is found by halving the block length. See Table 5-34 and section
+ * 4.8.3 of the ACPI specification for details.
+ */
+ fadt->pm1_evt_len = 2 * 2;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 32;
+ if (pch_is_lp())
+ fadt->gpe0_blk_len = 2 * 16;
+ else
+ fadt->gpe0_blk_len = 2 * 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
+
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
@@ -659,55 +675,60 @@
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
- fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0;
+
fadt->reset_value = 6;
- fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
- fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
- fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
- fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
- fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
fadt->x_pm2_cnt_blk.addrh = 0x0;
- fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
@@ -725,10 +746,9 @@
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
+ fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
@@ -736,9 +756,9 @@
fadt->x_gpe1_blk.addrh = 0x0;
}
-static unsigned long broadwell_write_acpi_tables(const struct device *device,
- unsigned long current,
- struct acpi_rsdp *rsdp)
+static unsigned long southbridge_write_acpi_tables(const struct device *device,
+ unsigned long current,
+ struct acpi_rsdp *rsdp)
{
if (CONFIG(INTEL_PCH_UART_CONSOLE))
current = acpi_write_dbg2_pci_uart(rsdp, current,
@@ -749,13 +769,13 @@
}
static struct device_operations device_ops = {
- .read_resources = &pch_lpc_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .acpi_inject_dsdt = southcluster_inject_dsdt,
- .write_acpi_tables = broadwell_write_acpi_tables,
- .init = &lpc_init,
- .scan_bus = &scan_static_bus,
+ .read_resources = pch_lpc_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .acpi_inject_dsdt = southbridge_inject_dsdt,
+ .write_acpi_tables = southbridge_write_acpi_tables,
+ .init = lpc_init,
+ .scan_bus = scan_static_bus,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c
index 3b1998e..9520d13 100644
--- a/src/southbridge/intel/wildcatpoint/me.c
+++ b/src/southbridge/intel/wildcatpoint/me.c
@@ -82,7 +82,6 @@
/*
* ME/MEI access helpers using memcpy to avoid aliasing.
*/
-
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
u32 dword = read32(mei_base_address + offset);
@@ -264,8 +263,8 @@
return 0;
}
-static int mei_send_header(u8 me_address, u8 host_address,
- void *header, int header_len, int complete)
+static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len,
+ int complete)
{
struct mei_header mei = {
.client_address = me_address,
@@ -276,8 +275,7 @@
return mei_send_packet(&mei, header);
}
-static int mei_recv_msg(void *header, int header_bytes,
- void *rsp_data, int rsp_bytes)
+static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes)
{
struct mei_header mei_rsp;
struct mei_csr me, host;
@@ -336,8 +334,8 @@
/* Make sure caller passed a buffer with enough space */
if (ndata != (rsp_bytes >> 2)) {
- printk(BIOS_ERR, "ME: not enough room in response buffer: "
- "%u != %u\n", ndata, rsp_bytes >> 2);
+ printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n",
+ ndata, rsp_bytes >> 2);
return -1;
}
@@ -376,8 +374,7 @@
return 0;
/* Read header and data */
- if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp),
- rsp_data, rsp_bytes) < 0)
+ if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), rsp_data, rsp_bytes) < 0)
return -1;
if (!mkhi_rsp.is_response ||
@@ -434,7 +431,7 @@
}
/*
- * mbp clear routine. This will wait for the ME to indicate that
+ * MBP clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
static void intel_me_mbp_clear(struct device *dev)
@@ -487,8 +484,7 @@
};
/* Send request and wait for response */
- if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32),
- &cap_msg, sizeof(cap_msg)) < 0) {
+ if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), &cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
}
@@ -507,20 +503,20 @@
return;
}
- print_cap("Full Network manageability", cap->full_net);
- print_cap("Regular Network manageability", cap->std_net);
- print_cap("Manageability", cap->manageability);
- print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
- print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
- print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
- print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
- print_cap("IPV6", cap->ipv6);
- print_cap("KVM Remote Control (KVM)", cap->kvm);
- print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
- print_cap("Virtual LAN (VLAN)", cap->vlan);
- print_cap("TLS", cap->tls);
- print_cap("Wireless LAN (WLAN)", cap->wlan);
+ print_cap("Full Network manageability", cap->full_net);
+ print_cap("Regular Network manageability", cap->std_net);
+ print_cap("Manageability", cap->manageability);
+ print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
+ print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
+ print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
+ print_cap("ICC Over Clocking", cap->icc_over_clocking);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("IPV6", cap->ipv6);
+ print_cap("KVM Remote Control (KVM)", cap->kvm);
+ print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
+ print_cap("Virtual LAN (VLAN)", cap->vlan);
+ print_cap("TLS", cap->tls);
+ print_cap("Wireless LAN (WLAN)", cap->wlan);
}
/* Send END OF POST message to the ME */
@@ -602,13 +598,12 @@
u16 reg16;
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
return;
/* Make sure IO is disabled */
reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide the PCI device */
@@ -634,6 +629,7 @@
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
return -1;
}
+
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
return 0;
}
diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c
index d11b26c..fc65fc9 100644
--- a/src/southbridge/intel/wildcatpoint/me_status.c
+++ b/src/southbridge/intel/wildcatpoint/me_status.c
@@ -47,7 +47,7 @@
[ME_HFS_STATE_M3] = "M3 without UMA",
[ME_HFS_STATE_M0] = "M0 without UMA",
[ME_HFS_STATE_BRINGUP] = "Bring up",
- [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
+ [ME_HFS_STATE_ERROR] = "M0 without UMA but with error",
};
/* HFS[19:16] Current Operation Mode Values */
@@ -56,7 +56,7 @@
[ME_HFS_MODE_DEBUG] = "Debug",
[ME_HFS_MODE_DIS] = "Soft Temporary Disable",
[ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
- [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
+ [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message",
};
/* HFS[15:12] Error Code Values */
@@ -64,7 +64,7 @@
[ME_HFS_ERROR_NONE] = "No Error",
[ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
[ME_HFS_ERROR_IMAGE] = "Image Failure",
- [ME_HFS_ERROR_DEBUG] = "Debug Failure"
+ [ME_HFS_ERROR_DEBUG] = "Debug Failure",
};
/* HFS2[31:28] ME Progress Code */
@@ -75,121 +75,78 @@
[ME_HFS2_PHASE_POLICY] = "Policy Module",
[ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading",
[ME_HFS2_PHASE_UNKNOWN] = "Unknown",
- [ME_HFS2_PHASE_HOST_COMM] = "Host Communication"
+ [ME_HFS2_PHASE_HOST_COMM] = "Host Communication",
};
/* HFS2[27:24] Power Management Event */
static const char *me_pmevent_values[] = {
- [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
- "Clean Moff->Mx wake",
- [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
- "Moff->Mx wake after an error",
- [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] =
- "Clean global reset",
- [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] =
- "Global reset after an error",
- [ME_HFS2_PMEVENT_CLEAN_ME_RESET] =
- "Clean Intel ME reset",
- [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] =
- "Intel ME reset due to exception",
- [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] =
- "Pseudo-global reset",
- [ME_HFS2_PMEVENT_S0MO_SXM3] =
- "S0/M0->Sx/M3",
- [ME_HFS2_PMEVENT_SXM3_S0M0] =
- "Sx/M3->S0/M0",
- [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] =
- "Non-power cycle reset",
- [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] =
- "Power cycle reset through M3",
- [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] =
- "Power cycle reset through Moff",
- [ME_HFS2_PMEVENT_SXMX_SXMOFF] =
- "Sx/Mx->Sx/Moff"
+ [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake",
+ [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error",
+ [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset",
+ [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error",
+ [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset",
+ [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception",
+ [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset",
+ [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3",
+ [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0",
+ [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset",
+ [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3",
+ [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff",
+ [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff",
};
/* Progress Code 0 states */
static const char *me_progress_rom_values[] = {
- [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
- [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"
+ [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
+ [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE",
};
/* Progress Code 1 states */
static const char *me_progress_bup_values[] = {
- [ME_HFS2_STATE_BUP_INIT] =
- "Initialization starts",
- [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
- "Disable the host wake event",
- [ME_HFS2_STATE_BUP_FLOW_DET] =
- "Flow determination start process",
- [ME_HFS2_STATE_BUP_VSCC_ERR] =
- "Error reading/matching the VSCC table in the descriptor",
- [ME_HFS2_STATE_BUP_CHECK_STRAP] =
- "Check to see if straps say ME DISABLED",
- [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] =
- "Timeout waiting for PWROK",
- [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] =
- "Possibly handle BUP manufacturing override strap",
- [ME_HFS2_STATE_BUP_M3] =
- "Bringup in M3",
- [ME_HFS2_STATE_BUP_M0] =
- "Bringup in M0",
- [ME_HFS2_STATE_BUP_FLOW_DET_ERR] =
- "Flow detection error",
- [ME_HFS2_STATE_BUP_M3_CLK_ERR] =
- "M3 clock switching error",
- [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] =
- "Host error - CPU reset timeout, DID timeout, memory missing",
- [ME_HFS2_STATE_BUP_M3_KERN_LOAD] =
- "M3 kernel load",
- [ME_HFS2_STATE_BUP_T32_MISSING] =
- "T34 missing - cannot program ICC",
- [ME_HFS2_STATE_BUP_WAIT_DID] =
- "Waiting for DID BIOS message",
- [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] =
- "Waiting for DID BIOS message failure",
- [ME_HFS2_STATE_BUP_DID_NO_FAIL] =
- "DID reported no error",
- [ME_HFS2_STATE_BUP_ENABLE_UMA] =
- "Enabling UMA",
- [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] =
- "Enabling UMA error",
- [ME_HFS2_STATE_BUP_SEND_DID_ACK] =
- "Sending DID Ack to BIOS",
- [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] =
- "Sending DID Ack to BIOS error",
- [ME_HFS2_STATE_BUP_M0_CLK] =
- "Switching clocks in M0",
- [ME_HFS2_STATE_BUP_M0_CLK_ERR] =
- "Switching clocks in M0 error",
- [ME_HFS2_STATE_BUP_TEMP_DIS] =
- "ME in temp disable",
- [ME_HFS2_STATE_BUP_M0_KERN_LOAD] =
- "M0 kernel load",
+ [ME_HFS2_STATE_BUP_INIT] = "Initialization starts",
+ [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event",
+ [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process",
+ [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor",
+ [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED",
+ [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK",
+ [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap",
+ [ME_HFS2_STATE_BUP_M3] = "Bringup in M3",
+ [ME_HFS2_STATE_BUP_M0] = "Bringup in M0",
+ [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error",
+ [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error",
+ [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing",
+ [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load",
+ [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC",
+ [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message",
+ [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure",
+ [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error",
+ [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA",
+ [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error",
+ [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS",
+ [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error",
+ [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0",
+ [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error",
+ [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable",
+ [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load",
};
/* Progress Code 3 states */
static const char *me_progress_policy_values[] = {
- [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module",
- [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry",
- [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry",
- [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry",
- [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry",
- [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry",
- [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry",
- [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake",
- [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch",
- [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done",
- [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] =
- "VSCC Data not found for flash device",
- [ME_HFS2_STATE_POLICY_VSCC_INVALID] =
- "VSCC Table is not valid",
- [ME_HFS2_STATE_POLICY_FPB_ERR] =
- "Flash Partition Boundary is outside address space",
- [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] =
- "ME cannot access the chipset descriptor region",
- [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] =
- "Required VSCC values for flash parts do not match",
+ [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module",
+ [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry",
+ [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry",
+ [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry",
+ [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry",
+ [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry",
+ [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry",
+ [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake",
+ [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch",
+ [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done",
+ [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = "VSCC Data not found for flash device",
+ [ME_HFS2_STATE_POLICY_VSCC_INVALID] = "VSCC Table is not valid",
+ [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space",
+ [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region",
+ [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match",
};
void intel_me_status(void)
diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c
index 1ac2967..efee415 100644
--- a/src/southbridge/intel/wildcatpoint/pch.c
+++ b/src/southbridge/intel/wildcatpoint/pch.c
@@ -185,8 +185,7 @@
/* Ensure memory, io, and bus master are all disabled */
reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device if possible */
diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
index 4515ffb..4f9a34a 100644
--- a/src/southbridge/intel/wildcatpoint/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -18,7 +18,7 @@
#include <delay.h>
/* Low Power variant has 6 root ports. */
-#define NUM_ROOT_PORTS 6
+#define MAX_NUM_ROOT_PORTS 6
struct root_port_config {
/* RPFN is a write-once register so keep a copy until it is written */
@@ -34,7 +34,7 @@
int coalesce;
int gbe_port;
int num_ports;
- struct device *ports[NUM_ROOT_PORTS];
+ struct device *ports[MAX_NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
@@ -110,7 +110,7 @@
if (root_port_is_first(dev)) {
rpc.orig_rpfn = RCBA32(RPFN);
rpc.new_rpfn = rpc.orig_rpfn;
- rpc.num_ports = NUM_ROOT_PORTS;
+ rpc.num_ports = MAX_NUM_ROOT_PORTS;
rpc.gbe_port = -1;
/* RP0 f5[3:0] = 0101b*/
pci_update_config8(dev, 0xf5, ~0xa, 0x5);
@@ -338,8 +338,7 @@
}
}
- printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
- rpc.orig_rpfn, rpc.new_rpfn);
+ printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn);
RCBA32(RPFN) = rpc.new_rpfn;
}
@@ -372,8 +371,7 @@
/* Check Root Port Configuration. */
switch (rp) {
case 2:
- /* Root Port 2 is disabled for all lane configurations
- * but config 00b (4x1 links). */
+ /* Root Port 2 is disabled for all lane configs except 00b (4x1 links). */
if ((rpc.strpfusecfg1 >> 14) & 0x3) {
root_port_mark_disable(dev);
return;
@@ -387,8 +385,7 @@
}
break;
case 4:
- /* Root Port 4 is disabled in configs 11b (1x4 links)
- * and 10b (2x2 links). */
+ /* Root Port 4 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */
if ((rpc.strpfusecfg1 >> 14) & 0x2) {
root_port_mark_disable(dev);
return;
@@ -473,8 +470,7 @@
if (do_aspm) {
/* Set ASPM bits in MPC2 register. */
- pci_update_config32(dev, 0xd4, ~(0x3 << 2),
- (1 << 4) | (0x2 << 2));
+ pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
/* Set unique clock exit latency in MPC register. */
pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
@@ -583,6 +579,7 @@
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
+ // This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c
index b66fb87..3024efd 100644
--- a/src/southbridge/intel/wildcatpoint/pmutil.c
+++ b/src/southbridge/intel/wildcatpoint/pmutil.c
@@ -90,10 +90,10 @@
static u16 print_pm1_status(u16 pm1_sts)
{
const char *pm1_sts_bits[] = {
- [0] = "TMROF",
- [4] = "BM",
- [5] = "GBL",
- [8] = "PWRBTN",
+ [0] = "TMROF",
+ [4] = "BM",
+ [5] = "GBL",
+ [8] = "PWRBTN",
[10] = "RTC",
[11] = "PRBTNOR",
[14] = "PCIEXPWAK",
@@ -122,7 +122,6 @@
outw(events, ACPI_BASE_ADDRESS + PM1_EN);
}
-
/*
* SMI
*/
@@ -130,7 +129,7 @@
/* Clear and return SMI status register */
static u32 reset_smi_status(void)
{
- u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
+ const u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
return smi_sts;
}
@@ -139,13 +138,13 @@
static u32 print_smi_status(u32 smi_sts)
{
const char *smi_sts_bits[] = {
- [2] = "BIOS",
- [3] = "LEGACY_USB",
- [4] = "SLP_SMI",
- [5] = "APM",
- [6] = "SWSMI_TMR",
- [8] = "PM1",
- [9] = "GPE0",
+ [2] = "BIOS",
+ [3] = "LEGACY_USB",
+ [4] = "SLP_SMI",
+ [5] = "APM",
+ [6] = "SWSMI_TMR",
+ [8] = "PM1",
+ [9] = "GPE0",
[10] = "GPI",
[11] = "MCSMI",
[12] = "DEVMON",
@@ -193,7 +192,6 @@
outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
}
-
/*
* ALT_GP_SMI
*/
@@ -270,13 +268,13 @@
static u32 print_tco_status(u32 tco_sts)
{
const char *tco_sts_bits[] = {
- [0] = "NMI2SMI",
- [1] = "SW_TCO",
- [2] = "TCO_INT",
- [3] = "TIMEOUT",
- [7] = "NEWCENTURY",
- [8] = "BIOSWR",
- [9] = "DMISCI",
+ [0] = "NMI2SMI",
+ [1] = "SW_TCO",
+ [2] = "TCO_INT",
+ [3] = "TIMEOUT",
+ [7] = "NEWCENTURY",
+ [8] = "BIOSWR",
+ [9] = "DMISCI",
[10] = "DMISMI",
[12] = "DMISERR",
[13] = "SLVSEL",
@@ -318,7 +316,7 @@
*/
/* Clear a GPE0 status and return events that are enabled and active */
-static u32 reset_gpe(u16 sts_reg, u16 en_reg)
+static u32 reset_gpe_status(u16 sts_reg, u16 en_reg)
{
u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);
u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);
@@ -359,11 +357,11 @@
u32 clear_gpe_status(void)
{
const char *gpe0_sts_3_bits[] = {
- [1] = "HOTPLUG",
- [2] = "SWGPE",
- [6] = "TCO_SCI",
- [7] = "SMB_WAK",
- [9] = "PCI_EXP",
+ [1] = "HOTPLUG",
+ [2] = "SWGPE",
+ [6] = "TCO_SCI",
+ [7] = "SMB_WAK",
+ [9] = "PCI_EXP",
[10] = "BATLOW",
[11] = "PME",
[12] = "ME",
@@ -372,10 +370,10 @@
[18] = "WADT"
};
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64);
- return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
+ print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
+ print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
+ print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64);
+ return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
gpe0_sts_3_bits);
}
diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c
index 3dbbc6e..613f2ac 100644
--- a/src/southbridge/intel/wildcatpoint/serialio.c
+++ b/src/southbridge/intel/wildcatpoint/serialio.c
@@ -271,10 +271,10 @@
}
static struct device_operations device_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &serialio_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &serialio_init,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = serialio_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = serialio_init,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c
index b8177e5..5cfd277 100644
--- a/src/southbridge/intel/wildcatpoint/smbus.c
+++ b/src/southbridge/intel/wildcatpoint/smbus.c
@@ -1,16 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/io.h>
#include <device/device.h>
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <southbridge/intel/wildcatpoint/iomap.h>
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <southbridge/intel/wildcatpoint/smbus.h>
-#include <device/smbus_host.h>
static void pch_smbus_init(struct device *dev)
{
@@ -54,8 +53,8 @@
}
static struct smbus_bus_operations lops_smbus_bus = {
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
+ .read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static void smbus_read_resources(struct device *dev)
diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c
index 75eeb02d..c6f8361 100644
--- a/src/southbridge/intel/wildcatpoint/smi.c
+++ b/src/southbridge/intel/wildcatpoint/smi.c
@@ -39,7 +39,8 @@
enable_pm1(pm1_events);
disable_gpe(PME_B0_EN);
- /* Enable SMI generation:
+ /*
+ * Enable SMI generation:
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c
index 98e26ca..782ba14 100644
--- a/src/southbridge/intel/wildcatpoint/smihandler.c
+++ b/src/southbridge/intel/wildcatpoint/smihandler.c
@@ -69,12 +69,12 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u16 reg16;
-
pci_devfn_t dev = PCI_DEV(bus, slot, func);
+
val = pci_read_config32(dev, PCI_VENDOR_ID);
if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
+ val == 0x0000ffff || val == 0xffff0000)
continue;
/* Disable Bus Mastering for this one device */
@@ -86,7 +86,7 @@
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
@@ -96,10 +96,9 @@
}
/*
- * Turn off the backlight if it is on, and wait for the specified
- * backlight off delay. This will allow panel power timings to meet
- * spec and prevent brief garbage on the screen when turned off
- * during firmware with power button triggered SMI.
+ * Turn off the backlight if it is on, and wait for the specified backlight off delay.
+ * This will allow panel power timings to meet spec and prevent brief garbage on the
+ * screen when turned off during firmware with power button triggered SMI.
*/
static void backlight_off(void)
{
@@ -255,11 +254,11 @@
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
state = smm_get_save_state(node);
- /* Check for Synchronous IO (bit0==1) */
+ /* Check for Synchronous IO (bit0 == 1) */
if (!(state->io_misc_info & (1 << 0)))
continue;
- /* Make sure it was a write (bit4==0) */
+ /* Make sure it was a write (bit4 == 0) */
if (state->io_misc_info & (1 << 4))
continue;
@@ -372,11 +371,9 @@
{
u16 pm1_sts = clear_pm1_status();
- /* While OSPM is not active, poweroff immediately
- * on a power button event.
- */
+ /* While OSPM is not active, poweroff immediately on a power button event */
if (pm1_sts & PWRBTN_STS) {
- /* power button pressed */
+ /* Power button pressed */
elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
disable_pm1_control(-1UL);
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
@@ -431,8 +428,7 @@
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pci_write_config32(PCH_DEV_LPC, BIOS_CNTL,
- (bios_cntl & ~1));
+ pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, bios_cntl & ~1);
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
@@ -454,6 +450,7 @@
static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
+
u32 trap_sts, trap_cycle;
u32 data, mask = 0;
int i;
@@ -475,13 +472,12 @@
return;
}
- /* IOTRAP(2) currently unused
- * IOTRAP(1) currently unused */
+ /* IOTRAP(2) currently unused */
+ /* IOTRAP(1) currently unused */
/* IOTRAP(0) SMIC */
if (IOTRAP(0)) {
- // It's a write
- if (!(trap_cycle & (1 << 24))) {
+ if (!(trap_cycle & (1 << 24))) { // It's a write
printk(BIOS_DEBUG, "SMI1 command\n");
data = RCBA32(0x1e18);
data &= mask;
@@ -492,15 +488,15 @@
// Fall through to debug
}
- printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
- trap_cycle & 0xfffc);
- for (i = 0; i < 4; i++)
+ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+
+ for (i = 0; i < 4; i++) {
if (IOTRAP(i))
printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ }
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
- printk(BIOS_DEBUG, " read/write: %s\n",
- (trap_cycle & (1 << 24)) ? "read" : "write");
+ printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) {
/* Write Cycle */
@@ -549,16 +545,14 @@
/**
* @brief Interrupt handler for SMI#
- *
- * @param smm_revision revision of the smm state save map
*/
-
void southbridge_smi_handler(void)
{
int i;
u32 smi_sts;
- /* We need to clear the SMI status registers, or we won't see what's
+ /*
+ * We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
smi_sts = clear_smi_status();
@@ -570,8 +564,7 @@
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occurred, but no "
- "handler available.\n", i);
+ "SMI_STS[%d] occurred, but no handler available.\n", i);
}
}
}
diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c
index cef2bed..2469cfd 100644
--- a/src/southbridge/intel/wildcatpoint/xhci.c
+++ b/src/southbridge/intel/wildcatpoint/xhci.c
@@ -185,7 +185,7 @@
}
#else /* !__SIMPLE_DEVICE__ */
-static void xhci_init(struct device *dev)
+static void usb_xhci_init(struct device *dev)
{
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
u16 reg16;
@@ -207,8 +207,8 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .init = usb_xhci_init,
.ops_pci = &broadwell_pci_ops,
- .init = xhci_init,
};
static const unsigned short pci_device_ids[] = {
--
To view, visit https://review.coreboot.org/c/coreboot/+/42620
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0
Gerrit-Change-Number: 42620
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
2
9
Change in coreboot[master]: lynxpoint/wildcatpoint: Factor out IOBP
by Angel Pons (Code Review) 30 Oct '20
by Angel Pons (Code Review) 30 Oct '20
30 Oct '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42625 )
Change subject: lynxpoint/wildcatpoint: Factor out IOBP
......................................................................
lynxpoint/wildcatpoint: Factor out IOBP
Change-Id: Id1abb8ce630c8232812f3a892224b37f55273b4a
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/lynxpoint/iobp.c
M src/southbridge/intel/lynxpoint/iobp.h
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/wildcatpoint/Makefile.inc
D src/southbridge/intel/wildcatpoint/iobp.c
M src/southbridge/intel/wildcatpoint/iobp.h
6 files changed, 36 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42625/1
diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c
index 3df6940..ee5518e 100644
--- a/src/southbridge/intel/lynxpoint/iobp.c
+++ b/src/southbridge/intel/lynxpoint/iobp.c
@@ -2,8 +2,8 @@
#include <console/console.h>
#include <delay.h>
-#include "pch.h"
-#include "iobp.h"
+#include <southbridge/intel/lynxpoint/iobp.h>
+#include <southbridge/intel/lynxpoint/pch.h>
#define IOBP_RETRY 1000
@@ -109,3 +109,31 @@
pch_iobp_write(address, data);
}
+
+void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
+{
+ if (!data || !resp)
+ return;
+
+ *resp = -1;
+ if (!iobp_poll())
+ return;
+
+ /* RCBA2330[31:0] = Address */
+ RCBA32(IOBPIRI) = addr;
+ /* RCBA2338[15:8] = opcode */
+ RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code;
+ /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */
+ RCBA16(IOBPU) = IOBPU_MAGIC | route_id;
+
+ if (op_code == IOBP_PCICFG_WRITE)
+ RCBA32(IOBPD) = *data;
+ /* Set RCBA2338[0] to trigger IOBP transaction*/
+ RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1;
+
+ if (!iobp_poll())
+ return;
+
+ *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1;
+ *data = RCBA32(IOBPD);
+}
diff --git a/src/southbridge/intel/lynxpoint/iobp.h b/src/southbridge/intel/lynxpoint/iobp.h
index c8669ba..458e6be 100644
--- a/src/southbridge/intel/lynxpoint/iobp.h
+++ b/src/southbridge/intel/lynxpoint/iobp.h
@@ -8,5 +8,6 @@
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
#endif
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index f9a5562..291a554 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -521,6 +521,8 @@
#define IOBPS_WRITE 0x0700
#define IOBPU 0x233a
#define IOBPU_MAGIC 0xf000
+#define IOBP_PCICFG_READ 0x0400
+#define IOBP_PCICFG_WRITE 0x0500
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc
index 49a2094..b98493b 100644
--- a/src/southbridge/intel/wildcatpoint/Makefile.inc
+++ b/src/southbridge/intel/wildcatpoint/Makefile.inc
@@ -11,8 +11,8 @@
romstage-y += gpio.c
smm-y += gpio.c
ramstage-y += hda.c
-ramstage-y += iobp.c
-romstage-y += iobp.c
+ramstage-y += ../lynxpoint/iobp.c
+romstage-y += ../lynxpoint/iobp.c
ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += me_status.c
diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c
deleted file mode 100644
index 51dd8a6..0000000
--- a/src/southbridge/intel/wildcatpoint/iobp.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <delay.h>
-#include <southbridge/intel/wildcatpoint/iobp.h>
-#include <southbridge/intel/wildcatpoint/rcba.h>
-
-#define IOBP_RETRY 1000
-
-static inline int iobp_poll(void)
-{
- unsigned int try;
-
- for (try = IOBP_RETRY; try > 0; try--) {
- u16 status = RCBA16(IOBPS);
- if ((status & IOBPS_READY) == 0)
- return 1;
- udelay(10);
- }
-
- printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
- return 0;
-}
-
-u32 pch_iobp_read(u32 address)
-{
- u16 status;
-
- if (!iobp_poll())
- return 0;
-
- /* Set the address */
- RCBA32(IOBPIRI) = address;
-
- /* READ OPCODE */
- status = RCBA16(IOBPS);
- status &= ~IOBPS_MASK;
- status |= IOBPS_READ;
- RCBA16(IOBPS) = status;
-
- /* Undocumented magic */
- RCBA16(IOBPU) = IOBPU_MAGIC;
-
- /* Set ready bit */
- status = RCBA16(IOBPS);
- status |= IOBPS_READY;
- RCBA16(IOBPS) = status;
-
- if (!iobp_poll())
- return 0;
-
- /* Check for successful transaction */
- status = RCBA16(IOBPS);
- if (status & IOBPS_TX_MASK) {
- printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
- return 0;
- }
-
- /* Read IOBP data */
- return RCBA32(IOBPD);
-}
-
-void pch_iobp_write(u32 address, u32 data)
-{
- u16 status;
-
- if (!iobp_poll())
- return;
-
- /* Set the address */
- RCBA32(IOBPIRI) = address;
-
- /* WRITE OPCODE */
- status = RCBA16(IOBPS);
- status &= ~IOBPS_MASK;
- status |= IOBPS_WRITE;
- RCBA16(IOBPS) = status;
-
- RCBA32(IOBPD) = data;
-
- /* Undocumented magic */
- RCBA16(IOBPU) = IOBPU_MAGIC;
-
- /* Set ready bit */
- status = RCBA16(IOBPS);
- status |= IOBPS_READY;
- RCBA16(IOBPS) = status;
-
- if (!iobp_poll())
- return;
-
- /* Check for successful transaction */
- status = RCBA16(IOBPS);
- if (status & IOBPS_TX_MASK) {
- printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
- return;
- }
-
- printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
- u32 data = pch_iobp_read(address);
-
- /* Update the data */
- data &= andvalue;
- data |= orvalue;
-
- pch_iobp_write(address, data);
-}
-
-void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
-{
- if (!data || !resp)
- return;
-
- *resp = -1;
- if (!iobp_poll())
- return;
-
- /* RCBA2330[31:0] = Address */
- RCBA32(IOBPIRI) = addr;
- /* RCBA2338[15:8] = opcode */
- RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code;
- /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */
- RCBA16(IOBPU) = IOBPU_MAGIC | route_id;
-
- if (op_code == IOBP_PCICFG_WRITE)
- RCBA32(IOBPD) = *data;
- /* Set RCBA2338[0] to trigger IOBP transaction*/
- RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1;
-
- if (!iobp_poll())
- return;
-
- *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1;
- *data = RCBA32(IOBPD);
-}
diff --git a/src/southbridge/intel/wildcatpoint/iobp.h b/src/southbridge/intel/wildcatpoint/iobp.h
index e3a6993..a0bdd33 100644
--- a/src/southbridge/intel/wildcatpoint/iobp.h
+++ b/src/southbridge/intel/wildcatpoint/iobp.h
@@ -1,11 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _BROADWELL_IOBP_H_
-#define _BROADWELL_IOBP_H_
-
-u32 pch_iobp_read(u32 address);
-void pch_iobp_write(u32 address, u32 data);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
-
-#endif
+#include <southbridge/intel/lynxpoint/iobp.h>
--
To view, visit https://review.coreboot.org/c/coreboot/+/42625
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id1abb8ce630c8232812f3a892224b37f55273b4a
Gerrit-Change-Number: 42625
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1
4
Change in coreboot[master]: Merge Haswell and Broadwell files
by Angel Pons (Code Review) 30 Oct '20
by Angel Pons (Code Review) 30 Oct '20
30 Oct '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files
......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/cpu/intel/broadwell/Makefile.inc
M src/cpu/intel/broadwell/acpi.c
D src/cpu/intel/broadwell/bootblock.c
M src/cpu/intel/broadwell/broadwell_init.c
D src/cpu/intel/broadwell/smmrelocate.c
M src/cpu/intel/haswell/acpi.c
A src/cpu/intel/haswell/acpi_common.c
M src/cpu/intel/haswell/bootblock.c
A src/cpu/intel/haswell/cstate_def.c
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
A src/cpu/intel/haswell/hsw_bdw_init_common.c
M src/cpu/intel/haswell/smmrelocate.c
M src/northbridge/intel/broadwell/Makefile.inc
M src/northbridge/intel/broadwell/acpi/broadwell.asl
D src/northbridge/intel/broadwell/bootblock.c
M src/northbridge/intel/broadwell/broadwell.h
M src/northbridge/intel/broadwell/igd.c
D src/northbridge/intel/broadwell/minihd.c
M src/northbridge/intel/broadwell/northbridge.c
R src/northbridge/intel/haswell/acpi/ctdp.asl
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
A src/northbridge/intel/haswell/northbridge_common.c
M src/northbridge/intel/haswell/report_platform.c
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/wildcatpoint/bootblock.c
M src/southbridge/intel/wildcatpoint/iomap.h
M src/southbridge/intel/wildcatpoint/pch.c
M src/southbridge/intel/wildcatpoint/spi.h
36 files changed, 1,129 insertions(+), 2,636 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/1
diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc
index ad5dc5b..4b89975 100644
--- a/src/cpu/intel/broadwell/Makefile.inc
+++ b/src/cpu/intel/broadwell/Makefile.inc
@@ -6,7 +6,7 @@
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/intel/common
-bootblock-y += bootblock.c
+bootblock-y += ../haswell/bootblock.c
bootblock-y += ../../../cpu/intel/car/bootblock.c
bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += ../../../cpu/x86/early_reset.S
@@ -25,7 +25,7 @@
romstage-y += romstage.c
-ramstage-y += smmrelocate.c
+ramstage-y += ../haswell/smmrelocate.c
bootblock-y += tsc_freq.c
ramstage-y += tsc_freq.c
diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c
index a63914c..f96c260 100644
--- a/src/cpu/intel/broadwell/acpi.c
+++ b/src/cpu/intel/broadwell/acpi.c
@@ -25,99 +25,8 @@
#include <southbridge/intel/wildcatpoint/soc_chip.h>
#include <intelblocks/cpulib.h>
-/*
- * List of supported C-states in this processor. Only the ULT parts support C8,
- * C9, and C10.
- */
-enum {
- C_STATE_C0, /* 0 */
- C_STATE_C1, /* 1 */
- C_STATE_C1E, /* 2 */
- C_STATE_C3, /* 3 */
- C_STATE_C6_SHORT_LAT, /* 4 */
- C_STATE_C6_LONG_LAT, /* 5 */
- C_STATE_C7_SHORT_LAT, /* 6 */
- C_STATE_C7_LONG_LAT, /* 7 */
- C_STATE_C7S_SHORT_LAT, /* 8 */
- C_STATE_C7S_LONG_LAT, /* 9 */
- C_STATE_C8, /* 10 */
- C_STATE_C9, /* 11 */
- C_STATE_C10, /* 12 */
- NUM_C_STATES
-};
-
-#define MWAIT_RES(state, sub_state) \
- { \
- .addrl = (((state) << 4) | (sub_state)), \
- .space_id = ACPI_ADDRESS_SPACE_FIXED, \
- .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
- .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
- .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
- }
-
-static acpi_cstate_t cstate_map[NUM_C_STATES] = {
- [C_STATE_C0] = { },
- [C_STATE_C1] = {
- .latency = 0,
- .power = 1000,
- .resource = MWAIT_RES(0, 0),
- },
- [C_STATE_C1E] = {
- .latency = 0,
- .power = 1000,
- .resource = MWAIT_RES(0, 1),
- },
- [C_STATE_C3] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = 900,
- .resource = MWAIT_RES(1, 0),
- },
- [C_STATE_C6_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 800,
- .resource = MWAIT_RES(2, 0),
- },
- [C_STATE_C6_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 800,
- .resource = MWAIT_RES(2, 1),
- },
- [C_STATE_C7_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 700,
- .resource = MWAIT_RES(3, 0),
- },
- [C_STATE_C7_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 700,
- .resource = MWAIT_RES(3, 1),
- },
- [C_STATE_C7S_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 700,
- .resource = MWAIT_RES(3, 2),
- },
- [C_STATE_C7S_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 700,
- .resource = MWAIT_RES(3, 3),
- },
- [C_STATE_C8] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
- .power = 600,
- .resource = MWAIT_RES(4, 0),
- },
- [C_STATE_C9] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
- .power = 500,
- .resource = MWAIT_RES(5, 0),
- },
- [C_STATE_C10] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
- .power = 400,
- .resource = MWAIT_RES(6, 0),
- },
-};
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/cstate_def.c>
static int cstate_set_s0ix[3] = {
C_STATE_C1E,
@@ -131,22 +40,6 @@
C_STATE_C7S_LONG_LAT
};
-static int get_cores_per_package(void)
-{
- struct cpuinfo_x86 c;
- struct cpuid_result result;
- int cores = 1;
-
- get_fms(&c, cpuid_eax(1));
- if (c.x86 != 6)
- return 1;
-
- result = cpuid_ext(0xb, 1);
- cores = result.ebx & 0xff;
-
- return cores;
-}
-
static void generate_C_state_entries(void)
{
acpi_cstate_t map[3];
@@ -169,229 +62,13 @@
acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
-static acpi_tstate_t tss_table_fine[] = {
- { 100, 1000, 0, 0x00, 0 },
- { 94, 940, 0, 0x1f, 0 },
- { 88, 880, 0, 0x1e, 0 },
- { 82, 820, 0, 0x1d, 0 },
- { 75, 760, 0, 0x1c, 0 },
- { 69, 700, 0, 0x1b, 0 },
- { 63, 640, 0, 0x1a, 0 },
- { 57, 580, 0, 0x19, 0 },
- { 50, 520, 0, 0x18, 0 },
- { 44, 460, 0, 0x17, 0 },
- { 38, 400, 0, 0x16, 0 },
- { 32, 340, 0, 0x15, 0 },
- { 25, 280, 0, 0x14, 0 },
- { 19, 220, 0, 0x13, 0 },
- { 13, 160, 0, 0x12, 0 },
-};
-
-static acpi_tstate_t tss_table_coarse[] = {
- { 100, 1000, 0, 0x00, 0 },
- { 88, 875, 0, 0x1f, 0 },
- { 75, 750, 0, 0x1e, 0 },
- { 63, 625, 0, 0x1d, 0 },
- { 50, 500, 0, 0x1c, 0 },
- { 38, 375, 0, 0x1b, 0 },
- { 25, 250, 0, 0x1a, 0 },
- { 13, 125, 0, 0x19, 0 },
-};
-
-static void generate_T_state_entries(int core, int cores_per_package)
+static inline void get_pmbase(void)
{
- /* Indicate SW_ALL coordination for T-states */
- acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
-
- /* Indicate FFixedHW so OS will use MSR */
- acpigen_write_empty_PTC();
-
- /* Set a T-state limit that can be modified in NVS */
- acpigen_write_TPC("\\TLVL");
-
- /*
- * CPUID.(EAX=6):EAX[5] indicates support
- * for extended throttle levels.
- */
- if (cpuid_eax(6) & (1 << 5))
- acpigen_write_TSS_package(
- ARRAY_SIZE(tss_table_fine), tss_table_fine);
- else
- acpigen_write_TSS_package(
- ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+ return ACPI_BASE_ADDRESS;
}
-static int calculate_power(int tdp, int p1_ratio, int ratio)
-{
- u32 m;
- u32 power;
-
- /*
- * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
- *
- * Power = (ratio / p1_ratio) * m * tdp
- */
-
- m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
- m = (m * m) / 1000;
-
- power = ((ratio * 100000 / p1_ratio) / 100);
- power *= (m / 100) * (tdp / 1000);
- power /= 1000;
-
- return (int)power;
-}
-
-static void generate_P_state_entries(int core, int cores_per_package)
-{
- int ratio_min, ratio_max, ratio_turbo, ratio_step;
- int coord_type, power_max, power_unit, num_entries;
- int ratio, power, clock, clock_max;
- msr_t msr;
-
- /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
- msr = rdmsr(MSR_MISC_PWR_MGMT);
- if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
- coord_type = SW_ANY;
- else
- coord_type = HW_ALL;
-
- /* Get bus ratio limits and calculate clock speeds */
- msr = rdmsr(MSR_PLATFORM_INFO);
- ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
-
- /* Determine if this CPU has configurable TDP */
- if (cpu_config_tdp_levels()) {
- /* Set max ratio to nominal TDP ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- ratio_max = msr.lo & 0xff;
- } else {
- /* Max Non-Turbo Ratio */
- ratio_max = (msr.lo >> 8) & 0xff;
- }
- clock_max = ratio_max * CPU_BCLK;
-
- /* Calculate CPU TDP in mW */
- msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
- power_unit = 2 << ((msr.lo & 0xf) - 1);
- msr = rdmsr(MSR_PKG_POWER_SKU);
- power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
-
- /* Write _PCT indicating use of FFixedHW */
- acpigen_write_empty_PCT();
-
- /* Write _PPC with no limit on supported P-state */
- acpigen_write_PPC_NVS();
-
- /* Write PSD indicating configured coordination type */
- acpigen_write_PSD_package(core, 1, coord_type);
-
- /* Add P-state entries in _PSS table */
- acpigen_write_name("_PSS");
-
- /* Determine ratio points */
- ratio_step = PSS_RATIO_STEP;
- num_entries = (ratio_max - ratio_min) / ratio_step;
- while (num_entries > PSS_MAX_ENTRIES-1) {
- ratio_step <<= 1;
- num_entries >>= 1;
- }
-
- /* P[T] is Turbo state if enabled */
- if (get_turbo_state() == TURBO_ENABLED) {
- /* _PSS package count including Turbo */
- acpigen_write_package(num_entries + 2);
-
- msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
- ratio_turbo = msr.lo & 0xff;
-
- /* Add entry for Turbo ratio */
- acpigen_write_PSS_package(
- clock_max + 1, /*MHz*/
- power_max, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio_turbo << 8, /*control*/
- ratio_turbo << 8); /*status*/
- } else {
- /* _PSS package count without Turbo */
- acpigen_write_package(num_entries + 1);
- }
-
- /* First regular entry is max non-turbo ratio */
- acpigen_write_PSS_package(
- clock_max, /*MHz*/
- power_max, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio_max << 8, /*control*/
- ratio_max << 8); /*status*/
-
- /* Generate the remaining entries */
- for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
- ratio >= ratio_min; ratio -= ratio_step) {
-
- /* Calculate power at this ratio */
- power = calculate_power(power_max, ratio_max, ratio);
- clock = ratio * CPU_BCLK;
-
- acpigen_write_PSS_package(
- clock, /*MHz*/
- power, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio << 8, /*control*/
- ratio << 8); /*status*/
- }
-
- /* Fix package length */
- acpigen_pop_len();
-}
-
-void generate_cpu_entries(const struct device *device)
-{
- int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
- int totalcores = dev_count_cpu();
- int cores_per_package = get_cores_per_package();
- int numcpus = totalcores/cores_per_package;
-
- printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
- numcpus, cores_per_package);
-
- for (cpuID = 1; cpuID <= numcpus; cpuID++) {
- for (coreID = 1; coreID <= cores_per_package; coreID++) {
- if (coreID > 1) {
- pcontrol_blk = 0;
- plen = 0;
- }
-
- /* Generate processor \_SB.CPUx */
- acpigen_write_processor(
- (cpuID - 1) * cores_per_package+coreID - 1,
- pcontrol_blk, plen);
-
- /* Generate P-state tables */
- generate_P_state_entries(
- coreID - 1, cores_per_package);
-
- /* Generate C-state tables */
- generate_C_state_entries();
-
- /* Generate T-state tables */
- generate_T_state_entries(
- cpuID - 1, cores_per_package);
-
- acpigen_pop_len();
- }
- }
-
- /* PPKG is usually used for thermal management
- of the first and only package. */
- acpigen_write_processor_package("PPKG", 0, cores_per_package);
-
- /* Add a method to notify processor nodes */
- acpigen_write_processor_cnot(cores_per_package);
-}
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/acpi_common.c>
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c
deleted file mode 100644
index 72f8205..0000000
--- a/src/cpu/intel/broadwell/bootblock.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <arch/bootblock.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <halt.h>
-#include <southbridge/intel/wildcatpoint/rcba.h>
-#include <delay.h>
-
-#include <cpu/intel/broadwell/broadwell.h>
-
-static void set_flex_ratio_to_tdp_nominal(void)
-{
- msr_t flex_ratio, msr;
- u32 soft_reset;
- u8 nominal_ratio;
-
- /* Check for Flex Ratio support */
- flex_ratio = rdmsr(MSR_FLEX_RATIO);
- if (!(flex_ratio.lo & FLEX_RATIO_EN))
- return;
-
- /* Check for >0 configurable TDPs */
- msr = rdmsr(MSR_PLATFORM_INFO);
- if (((msr.hi >> 1) & 3) == 0)
- return;
-
- /* Use nominal TDP ratio for flex ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- nominal_ratio = msr.lo & 0xff;
-
- /* See if flex ratio is already set to nominal TDP ratio */
- if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
- return;
-
- /* Set flex ratio to nominal TDP ratio */
- flex_ratio.lo &= ~0xff00;
- flex_ratio.lo |= nominal_ratio << 8;
- flex_ratio.lo |= FLEX_RATIO_LOCK;
- wrmsr(MSR_FLEX_RATIO, flex_ratio);
-
- /* Set flex ratio in soft reset data register bits 11:6.
- * RCBA region is enabled in southbridge bootblock */
- soft_reset = RCBA32(SOFT_RESET_DATA);
- soft_reset &= ~(0x3f << 6);
- soft_reset |= (nominal_ratio & 0x3f) << 6;
- RCBA32(SOFT_RESET_DATA) = soft_reset;
-
- /* Set soft reset control to use register value */
- RCBA32_OR(SOFT_RESET_CTRL, 1);
-
- /* Delay before reset to avoid potential TPM lockout */
- mdelay(30);
-
- /* Issue warm reset, will be "CPU only" due to soft reset data */
- outb(0x0, 0xcf9);
- outb(0x6, 0xcf9);
- halt();
-}
-
-void bootblock_early_cpu_init(void)
-{
- /* Set flex ratio and reset if needed */
- set_flex_ratio_to_tdp_nominal();
-}
diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c
index 5d26232..7c0ce54 100644
--- a/src/cpu/intel/broadwell/broadwell_init.c
+++ b/src/cpu/intel/broadwell/broadwell_init.c
@@ -36,80 +36,12 @@
/** haswell_is_ult **/
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
- * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
- * when a core is woken up. */
-static int pcode_ready(void)
-{
- int wait_count;
- const int delay_step = 10;
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/hsw_bdw_init_common.c>
- wait_count = 0;
- do {
- if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
- return 0;
- wait_count += delay_step;
- udelay(delay_step);
- } while (wait_count < 1000);
+/** cpu_config_tdp_levels **/
- return -1;
-}
-
-static void calibrate_24mhz_bclk(void)
-{
- int err_code;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
- return;
- }
-
- /* A non-zero value initiates the PCODE calibration. */
- MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
- MCHBAR32(BIOS_MAILBOX_INTERFACE) =
- MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
- return;
- }
-
- err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
-
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n",
- err_code);
-
- /* Read the calibrated value. */
- MCHBAR32(BIOS_MAILBOX_INTERFACE) =
- MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
- return;
- }
-
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n",
- MCHBAR32(BIOS_MAILBOX_DATA));
-}
-
-static u32 pcode_mailbox_read(u32 command)
-{
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
- return 0;
- }
-
- /* Send command and start transaction */
- MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
- return 0;
- }
-
- /* Read mailbox */
- return MCHBAR32(BIOS_MAILBOX_DATA);
-}
+/** set_power_limits **/
static int pcode_mailbox_write(u32 command, u32 data)
{
@@ -195,56 +127,6 @@
pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
}
-static void configure_pch_power_sharing(void)
-{
- u32 pch_power, pch_power_ext, pmsync, pmsync2;
- int i;
-
- /* Read PCH Power levels from PCODE */
- pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
- pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
-
- printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
- pch_power, pch_power_ext);
-
- pmsync = RCBA32(PMSYNC_CONFIG);
- pmsync2 = RCBA32(PMSYNC_CONFIG2);
-
- /* Program PMSYNC_TPR_CONFIG PCH power limit values
- * pmsync[0:4] = mailbox[0:5]
- * pmsync[8:12] = mailbox[6:11]
- * pmsync[16:20] = mailbox[12:17]
- */
- for (i = 0; i < 3; i++) {
- u32 level = pch_power & 0x3f;
- pch_power >>= 6;
- pmsync &= ~(0x1f << (i * 8));
- pmsync |= (level & 0x1f) << (i * 8);
- }
- RCBA32(PMSYNC_CONFIG) = pmsync;
-
- /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
- * pmsync2[0:4] = mailbox[23:18]
- * pmsync2[8:12] = mailbox_ext[6:11]
- * pmsync2[16:20] = mailbox_ext[12:17]
- * pmsync2[24:28] = mailbox_ext[18:22]
- */
- pmsync2 &= ~0x1f;
- pmsync2 |= pch_power & 0x1f;
-
- for (i = 1; i < 4; i++) {
- u32 level = pch_power_ext & 0x3f;
- pch_power_ext >>= 6;
- pmsync2 &= ~(0x1f << (i * 8));
- pmsync2 |= (level & 0x1f) << (i * 8);
- }
- RCBA32(PMSYNC_CONFIG2) = pmsync2;
-}
-
-/** cpu_config_tdp_levels **/
-
-/** set_power_limits **/
-
static void configure_c_states(void)
{
msr_t msr;
@@ -321,50 +203,6 @@
}
}
-static void configure_misc(void)
-{
- msr_t msr;
-
- msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
- wrmsr(IA32_MISC_ENABLE, msr);
-
- /* Disable Thermal interrupts */
- msr.lo = 0;
- msr.hi = 0;
- wrmsr(IA32_THERM_INTERRUPT, msr);
-
- /* Enable package critical interrupt only */
- msr.lo = 1 << 4;
- msr.hi = 0;
- wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
-}
-
-static void enable_lapic_tpr(void)
-{
- msr_t msr;
-
- msr = rdmsr(MSR_PIC_MSG_CONTROL);
- msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
- wrmsr(MSR_PIC_MSG_CONTROL, msr);
-}
-
-static void configure_dca_cap(void)
-{
- uint32_t feature_flag;
- msr_t msr;
-
- /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- feature_flag = cpu_get_feature_flags_ecx();
- if (feature_flag & CPUID_DCA) {
- msr = rdmsr(IA32_PLATFORM_DCA_CAP);
- msr.lo |= 1;
- wrmsr(IA32_PLATFORM_DCA_CAP, msr);
- }
-}
-
static void set_max_ratio(void)
{
msr_t msr, perf_ctl;
@@ -409,22 +247,6 @@
printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- int num_banks;
-
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & 0xff;
- msr.lo = msr.hi = 0;
- /* TODO(adurbin): This should only be done on a cold boot. Also, some
- * of these banks are core vs package scope. For now every CPU clears
- * every bank. */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-}
-
/* All CPUs including BSP will run the following function. */
static void cpu_core_init(struct device *cpu)
{
@@ -457,9 +279,6 @@
enable_turbo();
}
-/* MP initialization support. */
-static const void *microcode_patch;
-
static void pre_mp_init(void)
{
/* Setup MTRRs based on physical address size. */
@@ -471,37 +290,6 @@
configure_pch_power_sharing();
}
-static int get_cpu_count(void)
-{
- msr_t msr;
- int num_threads;
- int num_cores;
-
- msr = rdmsr(MSR_CORE_THREAD_COUNT);
- num_threads = (msr.lo >> 0) & 0xffff;
- num_cores = (msr.lo >> 16) & 0xffff;
- printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
- num_cores, num_threads);
-
- return num_threads;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
- microcode_patch = intel_microcode_find();
- *microcode = microcode_patch;
- *parallel = 1;
-}
-
-static void per_cpu_smm_trigger(void)
-{
- /* Relocate the SMM handler. */
- smm_relocate();
-
- /* After SMM relocation a 2nd microcode load is required. */
- intel_microcode_load_unlocked(microcode_patch);
-}
-
static void post_mp_init(void)
{
/* Set Max Ratio */
diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c
deleted file mode 100644
index 5599c0b..0000000
--- a/src/cpu/intel/broadwell/smmrelocate.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <cpu/intel/em64t101_save_state.h>
-#include <cpu/intel/smm_reloc.h>
-#include <console/console.h>
-#include <northbridge/intel/broadwell/broadwell.h>
-#include <southbridge/intel/wildcatpoint/pci_devs.h>
-#include <smp/node.h>
-#include "broadwell.h"
-
-
-static void update_save_state(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase,
- struct smm_relocation_params *relo_params)
-{
- u32 smbase;
- u32 iedbase;
-
- /* The relocated handler runs with all CPUs concurrently. Therefore
- * stagger the entry points adjusting SMBASE downwards by save state
- * size * CPU num. */
- smbase = staggered_smbase;
- iedbase = relo_params->ied_base;
-
- printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
- smbase, iedbase);
-
- /* All threads need to set IEDBASE and SMBASE to the relocated
- * handler region. However, the save state location depends on the
- * smm_save_state_in_msrs field in the relocation parameters. If
- * smm_save_state_in_msrs is non-zero then the CPUs are relocating
- * the SMM handler in parallel, and each CPUs save state area is
- * located in their respective MSR space. If smm_save_state_in_msrs
- * is zero then the SMM relocation is happening serially so the
- * save state is at the same default location for all CPUs. */
- if (relo_params->smm_save_state_in_msrs) {
- msr_t smbase_msr;
- msr_t iedbase_msr;
-
- smbase_msr.lo = smbase;
- smbase_msr.hi = 0;
-
- /* According the BWG the IEDBASE MSR is in bits 63:32. It's
- * not clear why it differs from the SMBASE MSR. */
- iedbase_msr.lo = 0;
- iedbase_msr.hi = iedbase;
-
- wrmsr(SMBASE_MSR, smbase_msr);
- wrmsr(IEDBASE_MSR, iedbase_msr);
- } else {
- em64t101_smm_state_save_area_t *save_state;
-
- save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
- sizeof(*save_state));
-
- save_state->smbase = smbase;
- save_state->iedbase = iedbase;
- }
-}
-
-/* Returns 1 if SMM MSR save state was set. */
-static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
-{
- msr_t smm_mca_cap;
-
- smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
- if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
- msr_t smm_feature_control;
-
- smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
- smm_feature_control.hi = 0;
- smm_feature_control.lo |= SMM_CPU_SAVE_EN;
- wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
- relo_params->smm_save_state_in_msrs = 1;
- }
- return relo_params->smm_save_state_in_msrs;
-}
-
-/* The relocation work is actually performed in SMM context, but the code
- * resides in the ramstage module. This occurs by trampolining from the default
- * SMRAM entry point to here. */
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase)
-{
- msr_t mtrr_cap;
- struct smm_relocation_params *relo_params = &smm_reloc_params;
-
- printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
-
- /* Determine if the processor supports saving state in MSRs. If so,
- * enable it before the non-BSPs run so that SMM relocation can occur
- * in parallel in the non-BSP CPUs. */
- if (cpu == 0) {
- /* If smm_save_state_in_msrs is 1 then that means this is the
- * 2nd time through the relocation handler for the BSP.
- * Parallel SMM handler relocation is taking place. However,
- * it is desired to access other CPUs save state in the real
- * SMM handler. Therefore, disable the SMM save state in MSRs
- * feature. */
- if (relo_params->smm_save_state_in_msrs) {
- msr_t smm_feature_control;
-
- smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
- smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
- wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
- } else if (bsp_setup_msr_save_state(relo_params))
- /* Just return from relocation handler if MSR save
- * state is enabled. In that case the BSP will come
- * back into the relocation handler to setup the new
- * SMBASE as well disabling SMM save state in MSRs. */
- return;
- }
-
- /* Make appropriate changes to the save state map. */
- update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
-
- /* Write PRMRR and SMRR MSRs based on indicated support. */
- mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (mtrr_cap.lo & SMRR_SUPPORTED)
- write_smrr(relo_params);
-
- if (mtrr_cap.lo & PRMRR_SUPPORTED) {
- write_prmrr(relo_params);
- /* UNCORE_PRMRR msrs are package level. Therefore, only
- * configure these MSRs on the BSP. */
- if (cpu == 0)
- write_uncore_prmrr(relo_params);
- }
-}
-
-static void fill_in_relocation_params(struct smm_relocation_params *params)
-{
- uintptr_t tseg_base;
- size_t tseg_size;
-
- u32 prmrr_base;
- u32 prmrr_size;
- int phys_bits;
- /* All range registers are aligned to 4KiB */
- const u32 rmask = ~((1 << 12) - 1);
-
- /* Some of the range registers are dependent on the number of physical
- * address bits supported. */
- phys_bits = cpuid_eax(0x80000008) & 0xff;
-
- /* The range bounded by the TSEGMB and BGSM registers encompasses the
- * SMRAM range as well as the IED range. However, the SMRAM available
- * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
- */
- smm_region(&tseg_base, &tseg_size);
-
- /* SMRR has 32-bits of valid address aligned to 4KiB. */
- params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
- params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
- params->smrr_mask.hi = 0;
-
- smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size);
-
- /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */
- prmrr_base = (params->ied_base + (2 << 20)) & rmask;
- prmrr_size = params->ied_size - (2 << 20);
-
- /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent
- * on the number of physical address bits supported. */
- params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK;
- params->prmrr_base.hi = 0;
- params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask)
- | MTRR_PHYS_MASK_VALID;
- params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1;
-
- /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */
- params->uncore_prmrr_base.lo = prmrr_base;
- params->uncore_prmrr_base.hi = 0;
- params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
- MTRR_PHYS_MASK_VALID;
- params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
-}
-
-static void setup_ied_area(struct smm_relocation_params *params)
-{
- char *ied_base;
-
- struct ied_header ied = {
- .signature = "INTEL RSVD",
- .size = params->ied_size,
- .reserved = {0},
- };
-
- ied_base = (void *)params->ied_base;
-
- /* Place IED header at IEDBASE. */
- memcpy(ied_base, &ied, sizeof(ied));
-
- /* Zero out 32KiB at IEDBASE + 1MiB */
- memset(ied_base + (1 << 20), 0, (32 << 10));
-}
-
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size)
-{
- printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
-
- fill_in_relocation_params(&smm_reloc_params);
-
- smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
-
- setup_ied_area(&smm_reloc_params);
-
- *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
-}
-
-void smm_initialize(void)
-{
- /* Clear the SMM state in the southbridge. */
- smm_southbridge_clear_state();
-
- /*
- * Run the relocation handler for on the BSP to check and set up
- * parallel SMM relocation.
- */
- smm_initiate_relocation();
-
- if (smm_reloc_params.smm_save_state_in_msrs)
- printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
-}
-
-/* The default SMM entry can happen in parallel or serially. If the
- * default SMM entry is done in parallel the BSP has already setup
- * the saving state to each CPU's MSRs. At least one save state size
- * is required for the initial SMM entry for the BSP to determine if
- * parallel SMM relocation is even feasible. */
-void smm_relocate(void)
-{
- /*
- * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
- * shall take place. Run the relocation handler a second time on the
- * BSP to do * the final move. For APs, a relocation handler always
- * needs to be run.
- */
- if (smm_reloc_params.smm_save_state_in_msrs)
- smm_initiate_relocation_parallel();
- else if (!boot_cpu())
- smm_initiate_relocation();
-}
-
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 676acce..0deb358 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -14,22 +14,6 @@
#include <southbridge/intel/lynxpoint/pch.h>
-static int get_cores_per_package(void)
-{
- struct cpuinfo_x86 c;
- struct cpuid_result result;
- int cores = 1;
-
- get_fms(&c, cpuid_eax(1));
- if (c.x86 != 6)
- return 1;
-
- result = cpuid_ext(0xb, 1);
- cores = result.ebx & 0xff;
-
- return cores;
-}
-
static void generate_cstate_entries(acpi_cstate_t *cstates,
int c1, int c2, int c3)
{
@@ -109,229 +93,8 @@
acpigen_pop_len();
}
-static acpi_tstate_t tss_table_fine[] = {
- { 100, 1000, 0, 0x00, 0 },
- { 94, 940, 0, 0x1f, 0 },
- { 88, 880, 0, 0x1e, 0 },
- { 82, 820, 0, 0x1d, 0 },
- { 75, 760, 0, 0x1c, 0 },
- { 69, 700, 0, 0x1b, 0 },
- { 63, 640, 0, 0x1a, 0 },
- { 57, 580, 0, 0x19, 0 },
- { 50, 520, 0, 0x18, 0 },
- { 44, 460, 0, 0x17, 0 },
- { 38, 400, 0, 0x16, 0 },
- { 32, 340, 0, 0x15, 0 },
- { 25, 280, 0, 0x14, 0 },
- { 19, 220, 0, 0x13, 0 },
- { 13, 160, 0, 0x12, 0 },
-};
-
-static acpi_tstate_t tss_table_coarse[] = {
- { 100, 1000, 0, 0x00, 0 },
- { 88, 875, 0, 0x1f, 0 },
- { 75, 750, 0, 0x1e, 0 },
- { 63, 625, 0, 0x1d, 0 },
- { 50, 500, 0, 0x1c, 0 },
- { 38, 375, 0, 0x1b, 0 },
- { 25, 250, 0, 0x1a, 0 },
- { 13, 125, 0, 0x19, 0 },
-};
-
-static void generate_T_state_entries(int core, int cores_per_package)
-{
- /* Indicate SW_ALL coordination for T-states */
- acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
-
- /* Indicate FFixedHW so OS will use MSR */
- acpigen_write_empty_PTC();
-
- /* Set a T-state limit that can be modified in NVS */
- acpigen_write_TPC("\\TLVL");
-
- /*
- * CPUID.(EAX=6):EAX[5] indicates support
- * for extended throttle levels.
- */
- if (cpuid_eax(6) & (1 << 5))
- acpigen_write_TSS_package(
- ARRAY_SIZE(tss_table_fine), tss_table_fine);
- else
- acpigen_write_TSS_package(
- ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
-}
-
-static int calculate_power(int tdp, int p1_ratio, int ratio)
-{
- u32 m;
- u32 power;
-
- /*
- * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
- *
- * Power = (ratio / p1_ratio) * m * tdp
- */
-
- m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
- m = (m * m) / 1000;
-
- power = ((ratio * 100000 / p1_ratio) / 100);
- power *= (m / 100) * (tdp / 1000);
- power /= 1000;
-
- return (int)power;
-}
-
-static void generate_P_state_entries(int core, int cores_per_package)
-{
- int ratio_min, ratio_max, ratio_turbo, ratio_step;
- int coord_type, power_max, power_unit, num_entries;
- int ratio, power, clock, clock_max;
- msr_t msr;
-
- /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
- msr = rdmsr(MSR_MISC_PWR_MGMT);
- if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
- coord_type = SW_ANY;
- else
- coord_type = HW_ALL;
-
- /* Get bus ratio limits and calculate clock speeds */
- msr = rdmsr(MSR_PLATFORM_INFO);
- ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
-
- /* Determine if this CPU has configurable TDP */
- if (cpu_config_tdp_levels()) {
- /* Set max ratio to nominal TDP ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- ratio_max = msr.lo & 0xff;
- } else {
- /* Max Non-Turbo Ratio */
- ratio_max = (msr.lo >> 8) & 0xff;
- }
- clock_max = ratio_max * HASWELL_BCLK;
-
- /* Calculate CPU TDP in mW */
- msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
- power_unit = 2 << ((msr.lo & 0xf) - 1);
- msr = rdmsr(MSR_PKG_POWER_SKU);
- power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
-
- /* Write _PCT indicating use of FFixedHW */
- acpigen_write_empty_PCT();
-
- /* Write _PPC with no limit on supported P-state */
- acpigen_write_PPC_NVS();
-
- /* Write PSD indicating configured coordination type */
- acpigen_write_PSD_package(core, 1, coord_type);
-
- /* Add P-state entries in _PSS table */
- acpigen_write_name("_PSS");
-
- /* Determine ratio points */
- ratio_step = PSS_RATIO_STEP;
- num_entries = (ratio_max - ratio_min) / ratio_step;
- while (num_entries > PSS_MAX_ENTRIES-1) {
- ratio_step <<= 1;
- num_entries >>= 1;
- }
-
- /* P[T] is Turbo state if enabled */
- if (get_turbo_state() == TURBO_ENABLED) {
- /* _PSS package count including Turbo */
- acpigen_write_package(num_entries + 2);
-
- msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
- ratio_turbo = msr.lo & 0xff;
-
- /* Add entry for Turbo ratio */
- acpigen_write_PSS_package(
- clock_max + 1, /*MHz*/
- power_max, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio_turbo << 8, /*control*/
- ratio_turbo << 8); /*status*/
- } else {
- /* _PSS package count without Turbo */
- acpigen_write_package(num_entries + 1);
- }
-
- /* First regular entry is max non-turbo ratio */
- acpigen_write_PSS_package(
- clock_max, /*MHz*/
- power_max, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio_max << 8, /*control*/
- ratio_max << 8); /*status*/
-
- /* Generate the remaining entries */
- for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
- ratio >= ratio_min; ratio -= ratio_step) {
-
- /* Calculate power at this ratio */
- power = calculate_power(power_max, ratio_max, ratio);
- clock = ratio * HASWELL_BCLK;
-
- acpigen_write_PSS_package(
- clock, /*MHz*/
- power, /*mW*/
- PSS_LATENCY_TRANSITION, /*lat1*/
- PSS_LATENCY_BUSMASTER, /*lat2*/
- ratio << 8, /*control*/
- ratio << 8); /*status*/
- }
-
- /* Fix package length */
- acpigen_pop_len();
-}
-
-void generate_cpu_entries(const struct device *device)
-{
- int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
- int totalcores = dev_count_cpu();
- int cores_per_package = get_cores_per_package();
- int numcpus = totalcores/cores_per_package;
-
- printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
- numcpus, cores_per_package);
-
- for (cpuID = 1; cpuID <= numcpus; cpuID++) {
- for (coreID = 1; coreID <= cores_per_package; coreID++) {
- if (coreID > 1) {
- pcontrol_blk = 0;
- plen = 0;
- }
-
- /* Generate processor \_SB.CPUx */
- acpigen_write_processor(
- (cpuID-1)*cores_per_package+coreID-1,
- pcontrol_blk, plen);
-
- /* Generate P-state tables */
- generate_P_state_entries(
- coreID-1, cores_per_package);
-
- /* Generate C-state tables */
- generate_C_state_entries();
-
- /* Generate T-state tables */
- generate_T_state_entries(
- cpuID-1, cores_per_package);
-
- acpigen_pop_len();
- }
- }
-
- /* PPKG is usually used for thermal management
- of the first and only package. */
- acpigen_write_processor_package("PPKG", 0, cores_per_package);
-
- /* Add a method to notify processor nodes */
- acpigen_write_processor_cnot(cores_per_package);
-}
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/acpi_common.c>
struct chip_operations cpu_intel_haswell_ops = {
CHIP_NAME("Intel Haswell CPU")
diff --git a/src/cpu/intel/haswell/acpi_common.c b/src/cpu/intel/haswell/acpi_common.c
new file mode 100644
index 0000000..545f319
--- /dev/null
+++ b/src/cpu/intel/haswell/acpi_common.c
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is being included from other C files! */
+
+static int get_cores_per_package(void)
+{
+ struct cpuinfo_x86 c;
+ struct cpuid_result result;
+ int cores = 1;
+
+ get_fms(&c, cpuid_eax(1));
+ if (c.x86 != 6)
+ return 1;
+
+ result = cpuid_ext(0xb, 1);
+ cores = result.ebx & 0xff;
+
+ return cores;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+ { 100, 1000, 0, 0x00, 0 },
+ { 94, 940, 0, 0x1f, 0 },
+ { 88, 880, 0, 0x1e, 0 },
+ { 82, 820, 0, 0x1d, 0 },
+ { 75, 760, 0, 0x1c, 0 },
+ { 69, 700, 0, 0x1b, 0 },
+ { 63, 640, 0, 0x1a, 0 },
+ { 57, 580, 0, 0x19, 0 },
+ { 50, 520, 0, 0x18, 0 },
+ { 44, 460, 0, 0x17, 0 },
+ { 38, 400, 0, 0x16, 0 },
+ { 32, 340, 0, 0x15, 0 },
+ { 25, 280, 0, 0x14, 0 },
+ { 19, 220, 0, 0x13, 0 },
+ { 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+ { 100, 1000, 0, 0x00, 0 },
+ { 88, 875, 0, 0x1f, 0 },
+ { 75, 750, 0, 0x1e, 0 },
+ { 63, 625, 0, 0x1d, 0 },
+ { 50, 500, 0, 0x1c, 0 },
+ { 38, 375, 0, 0x1b, 0 },
+ { 25, 250, 0, 0x1a, 0 },
+ { 13, 125, 0, 0x19, 0 },
+};
+
+static void generate_T_state_entries(int core, int cores_per_package)
+{
+ /* Indicate SW_ALL coordination for T-states */
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+ /* Indicate FFixedHW so OS will use MSR */
+ acpigen_write_empty_PTC();
+
+ /* Set a T-state limit that can be modified in NVS */
+ acpigen_write_TPC("\\TLVL");
+
+ /*
+ * CPUID.(EAX=6):EAX[5] indicates support
+ * for extended throttle levels.
+ */
+ if (cpuid_eax(6) & (1 << 5))
+ acpigen_write_TSS_package(
+ ARRAY_SIZE(tss_table_fine), tss_table_fine);
+ else
+ acpigen_write_TSS_package(
+ ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+ u32 m;
+ u32 power;
+
+ /*
+ * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+ *
+ * Power = (ratio / p1_ratio) * m * tdp
+ */
+
+ m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+ m = (m * m) / 1000;
+
+ power = ((ratio * 100000 / p1_ratio) / 100);
+ power *= (m / 100) * (tdp / 1000);
+ power /= 1000;
+
+ return (int)power;
+}
+
+#ifndef HASWELL_BCLK
+#define HASWELL_BCLK CPU_BCLK
+#endif
+
+static void generate_P_state_entries(int core, int cores_per_package)
+{
+ int ratio_min, ratio_max, ratio_turbo, ratio_step;
+ int coord_type, power_max, power_unit, num_entries;
+ int ratio, power, clock, clock_max;
+ msr_t msr;
+
+ /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+ msr = rdmsr(MSR_MISC_PWR_MGMT);
+ if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+ coord_type = SW_ANY;
+ else
+ coord_type = HW_ALL;
+
+ /* Get bus ratio limits and calculate clock speeds */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+
+ /* Determine if this CPU has configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ /* Set max ratio to nominal TDP ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ ratio_max = msr.lo & 0xff;
+ } else {
+ /* Max Non-Turbo Ratio */
+ ratio_max = (msr.lo >> 8) & 0xff;
+ }
+ clock_max = ratio_max * HASWELL_BCLK;
+
+ /* Calculate CPU TDP in mW */
+ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+ msr = rdmsr(MSR_PKG_POWER_SKU);
+ power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
+
+ /* Write _PCT indicating use of FFixedHW */
+ acpigen_write_empty_PCT();
+
+ /* Write _PPC with no limit on supported P-state */
+ acpigen_write_PPC_NVS();
+
+ /* Write PSD indicating configured coordination type */
+ acpigen_write_PSD_package(core, 1, coord_type);
+
+ /* Add P-state entries in _PSS table */
+ acpigen_write_name("_PSS");
+
+ /* Determine ratio points */
+ ratio_step = PSS_RATIO_STEP;
+ num_entries = (ratio_max - ratio_min) / ratio_step;
+ while (num_entries > PSS_MAX_ENTRIES-1) {
+ ratio_step <<= 1;
+ num_entries >>= 1;
+ }
+
+ /* P[T] is Turbo state if enabled */
+ if (get_turbo_state() == TURBO_ENABLED) {
+ /* _PSS package count including Turbo */
+ acpigen_write_package(num_entries + 2);
+
+ msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+ ratio_turbo = msr.lo & 0xff;
+
+ /* Add entry for Turbo ratio */
+ acpigen_write_PSS_package(
+ clock_max + 1, /*MHz*/
+ power_max, /*mW*/
+ PSS_LATENCY_TRANSITION, /*lat1*/
+ PSS_LATENCY_BUSMASTER, /*lat2*/
+ ratio_turbo << 8, /*control*/
+ ratio_turbo << 8); /*status*/
+ } else {
+ /* _PSS package count without Turbo */
+ acpigen_write_package(num_entries + 1);
+ }
+
+ /* First regular entry is max non-turbo ratio */
+ acpigen_write_PSS_package(
+ clock_max, /*MHz*/
+ power_max, /*mW*/
+ PSS_LATENCY_TRANSITION, /*lat1*/
+ PSS_LATENCY_BUSMASTER, /*lat2*/
+ ratio_max << 8, /*control*/
+ ratio_max << 8); /*status*/
+
+ /* Generate the remaining entries */
+ for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+ ratio >= ratio_min; ratio -= ratio_step) {
+
+ /* Calculate power at this ratio */
+ power = calculate_power(power_max, ratio_max, ratio);
+ clock = ratio * HASWELL_BCLK;
+
+ acpigen_write_PSS_package(
+ clock, /*MHz*/
+ power, /*mW*/
+ PSS_LATENCY_TRANSITION, /*lat1*/
+ PSS_LATENCY_BUSMASTER, /*lat2*/
+ ratio << 8, /*control*/
+ ratio << 8); /*status*/
+ }
+
+ /* Fix package length */
+ acpigen_pop_len();
+}
+
+void generate_cpu_entries(const struct device *device)
+{
+ int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
+ int totalcores = dev_count_cpu();
+ int cores_per_package = get_cores_per_package();
+ int numcpus = totalcores/cores_per_package;
+
+ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+ numcpus, cores_per_package);
+
+ for (cpuID = 1; cpuID <= numcpus; cpuID++) {
+ for (coreID = 1; coreID <= cores_per_package; coreID++) {
+ if (coreID > 1) {
+ pcontrol_blk = 0;
+ plen = 0;
+ }
+
+ /* Generate processor \_SB.CPUx */
+ acpigen_write_processor(
+ (cpuID - 1) * cores_per_package+coreID - 1,
+ pcontrol_blk, plen);
+
+ /* Generate P-state tables */
+ generate_P_state_entries(
+ coreID - 1, cores_per_package);
+
+ /* Generate C-state tables */
+ generate_C_state_entries();
+
+ /* Generate T-state tables */
+ generate_T_state_entries(
+ cpuID - 1, cores_per_package);
+
+ acpigen_pop_len();
+ }
+ }
+
+ /* PPKG is usually used for thermal management
+ of the first and only package. */
+ acpigen_write_processor_package("PPKG", 0, cores_per_package);
+
+ /* Add a method to notify processor nodes */
+ acpigen_write_processor_cnot(cores_per_package);
+}
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index c9e3f2a..6b5d85f 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -5,11 +5,17 @@
#include <cpu/x86/msr.h>
#include <arch/io.h>
#include <halt.h>
+#include <delay.h>
-#include "haswell.h"
-
+#if CONFIG(CPU_INTEL_HASWELL)
+#include <cpu/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#elif CONFIG(CPU_INTEL_BROADWELL)
+#include <cpu/intel/broadwell/broadwell.h>
+#include <southbridge/intel/wildcatpoint/rcba.h>
+#endif
+
static void set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
@@ -50,6 +56,10 @@
/* Set soft reset control to use register value */
RCBA32_OR(SOFT_RESET_CTRL, 1);
+ /* Delay before reset to avoid potential TPM lockout */
+ if (CONFIG(CPU_INTEL_BROADWELL))
+ mdelay(30);
+
/* Issue warm reset, will be "CPU only" due to soft reset data */
outb(0x0, 0xcf9);
outb(0x6, 0xcf9);
diff --git a/src/cpu/intel/haswell/cstate_def.c b/src/cpu/intel/haswell/cstate_def.c
new file mode 100644
index 0000000..ede75b0
--- /dev/null
+++ b/src/cpu/intel/haswell/cstate_def.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is being included from other C files! */
+
+/*
+ * List of supported C-states in this processor. Only the ULT parts support C8,
+ * C9, and C10.
+ */
+enum {
+ C_STATE_C0, /* 0 */
+ C_STATE_C1, /* 1 */
+ C_STATE_C1E, /* 2 */
+ C_STATE_C3, /* 3 */
+ C_STATE_C6_SHORT_LAT, /* 4 */
+ C_STATE_C6_LONG_LAT, /* 5 */
+ C_STATE_C7_SHORT_LAT, /* 6 */
+ C_STATE_C7_LONG_LAT, /* 7 */
+ C_STATE_C7S_SHORT_LAT, /* 8 */
+ C_STATE_C7S_LONG_LAT, /* 9 */
+ C_STATE_C8, /* 10 */
+ C_STATE_C9, /* 11 */
+ C_STATE_C10, /* 12 */
+ NUM_C_STATES
+};
+
+#define MWAIT_RES(state, sub_state) \
+ { \
+ .addrl = (((state) << 4) | (sub_state)), \
+ .space_id = ACPI_ADDRESS_SPACE_FIXED, \
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
+ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
+ }
+
+static acpi_cstate_t cstate_map[NUM_C_STATES] = {
+ [C_STATE_C0] = { },
+ [C_STATE_C1] = {
+ .latency = 0,
+ .power = 1000,
+ .resource = MWAIT_RES(0, 0),
+ },
+ [C_STATE_C1E] = {
+ .latency = 0,
+ .power = 1000,
+ .resource = MWAIT_RES(0, 1),
+ },
+ [C_STATE_C3] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = 900,
+ .resource = MWAIT_RES(1, 0),
+ },
+ [C_STATE_C6_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+ .power = 800,
+ .resource = MWAIT_RES(2, 0),
+ },
+ [C_STATE_C6_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+ .power = 800,
+ .resource = MWAIT_RES(2, 1),
+ },
+ [C_STATE_C7_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+ .power = 700,
+ .resource = MWAIT_RES(3, 0),
+ },
+ [C_STATE_C7_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+ .power = 700,
+ .resource = MWAIT_RES(3, 1),
+ },
+ [C_STATE_C7S_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+ .power = 700,
+ .resource = MWAIT_RES(3, 2),
+ },
+ [C_STATE_C7S_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+ .power = 700,
+ .resource = MWAIT_RES(3, 3),
+ },
+ [C_STATE_C8] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
+ .power = 600,
+ .resource = MWAIT_RES(4, 0),
+ },
+ [C_STATE_C9] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
+ .power = 500,
+ .resource = MWAIT_RES(5, 0),
+ },
+ [C_STATE_C10] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
+ .power = 400,
+ .resource = MWAIT_RES(6, 0),
+ },
+};
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 7906b83..e47429c 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -29,15 +29,30 @@
#define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_PIC_MSG_CONTROL 0x2e
+#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
-
+#define MSR_FEATURE_CONFIG 0x13c
+#define SMM_MCA_CAP_MSR 0x17d
+#define SMM_CPU_SVRSTR_BIT 57
+#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
#define MSR_POWER_CTL 0x1fc
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+#define SMM_FEATURE_CONTROL_MSR 0x4e0
+#define SMM_CPU_SAVE_EN (1 << 1)
#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
@@ -77,6 +92,14 @@
#define MSR_CONFIG_TDP_CONTROL 0x64b
#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+/* SMM save state MSRs */
+#define SMBASE_MSR 0xc20
+#define IEDBASE_MSR 0xc22
+
+/* MTRR_CAP_MSR bits */
+#define SMRR_SUPPORTED (1 << 11)
+#define PRMRR_SUPPORTED (1 << 12)
+
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index e621638..e88c9ef 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -34,99 +34,8 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
-/*
- * List of supported C-states in this processor. Only the ULT parts support C8,
- * C9, and C10.
- */
-enum {
- C_STATE_C0, /* 0 */
- C_STATE_C1, /* 1 */
- C_STATE_C1E, /* 2 */
- C_STATE_C3, /* 3 */
- C_STATE_C6_SHORT_LAT, /* 4 */
- C_STATE_C6_LONG_LAT, /* 5 */
- C_STATE_C7_SHORT_LAT, /* 6 */
- C_STATE_C7_LONG_LAT, /* 7 */
- C_STATE_C7S_SHORT_LAT, /* 8 */
- C_STATE_C7S_LONG_LAT, /* 9 */
- C_STATE_C8, /* 10 */
- C_STATE_C9, /* 11 */
- C_STATE_C10, /* 12 */
- NUM_C_STATES
-};
-
-#define MWAIT_RES(state, sub_state) \
- { \
- .addrl = (((state) << 4) | (sub_state)), \
- .space_id = ACPI_ADDRESS_SPACE_FIXED, \
- .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
- .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
- .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
- }
-
-static acpi_cstate_t cstate_map[NUM_C_STATES] = {
- [C_STATE_C0] = { },
- [C_STATE_C1] = {
- .latency = 0,
- .power = 1000,
- .resource = MWAIT_RES(0, 0),
- },
- [C_STATE_C1E] = {
- .latency = 0,
- .power = 1000,
- .resource = MWAIT_RES(0, 1),
- },
- [C_STATE_C3] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
- .power = 900,
- .resource = MWAIT_RES(1, 0),
- },
- [C_STATE_C6_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 800,
- .resource = MWAIT_RES(2, 0),
- },
- [C_STATE_C6_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 800,
- .resource = MWAIT_RES(2, 1),
- },
- [C_STATE_C7_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 700,
- .resource = MWAIT_RES(3, 0),
- },
- [C_STATE_C7_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 700,
- .resource = MWAIT_RES(3, 1),
- },
- [C_STATE_C7S_SHORT_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
- .power = 700,
- .resource = MWAIT_RES(3, 2),
- },
- [C_STATE_C7S_LONG_LAT] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
- .power = 700,
- .resource = MWAIT_RES(3, 3),
- },
- [C_STATE_C8] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
- .power = 600,
- .resource = MWAIT_RES(4, 0),
- },
- [C_STATE_C9] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
- .power = 500,
- .resource = MWAIT_RES(5, 0),
- },
- [C_STATE_C10] = {
- .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
- .power = 400,
- .resource = MWAIT_RES(6, 0),
- },
-};
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/cstate_def.c>
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
@@ -207,179 +116,9 @@
return ult;
}
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
- * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
- * when a core is woken up. */
-static int pcode_ready(void)
-{
- int wait_count;
- const int delay_step = 10;
- wait_count = 0;
- do {
- if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
- return 0;
- wait_count += delay_step;
- udelay(delay_step);
- } while (wait_count < 1000);
-
- return -1;
-}
-
-static void calibrate_24mhz_bclk(void)
-{
- int err_code;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
- return;
- }
-
- /* A non-zero value initiates the PCODE calibration. */
- MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
- MCHBAR32(BIOS_MAILBOX_INTERFACE) =
- MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
- return;
- }
-
- err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
-
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n",
- err_code);
-
- /* Read the calibrated value. */
- MCHBAR32(BIOS_MAILBOX_INTERFACE) =
- MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
- return;
- }
-
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n",
- MCHBAR32(BIOS_MAILBOX_DATA));
-}
-
-static u32 pcode_mailbox_read(u32 command)
-{
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
- return 0;
- }
-
- /* Send command and start transaction */
- MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
-
- if (pcode_ready() < 0) {
- printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
- return 0;
- }
-
- /* Read mailbox */
- return MCHBAR32(BIOS_MAILBOX_DATA);
-}
-
-static void initialize_vr_config(void)
-{
- msr_t msr;
-
- printk(BIOS_DEBUG, "Initializing VR config.\n");
-
- /* Configure VR_CURRENT_CONFIG. */
- msr = rdmsr(MSR_VR_CURRENT_CONFIG);
- /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
- * on ULT systems. */
- msr.hi &= 0xc0000000;
- msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */
- msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */
- msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
-
- if (haswell_is_ult())
- msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
- /* Leave the max instantaneous current limit (12:0) to default. */
- wrmsr(MSR_VR_CURRENT_CONFIG, msr);
-
- /* Configure VR_MISC_CONFIG MSR. */
- msr = rdmsr(MSR_VR_MISC_CONFIG);
- /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */
- msr.hi &= ~(0x3ff << (40 - 32));
- msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
- /* Set IOUT_OFFSET to 0. */
- msr.hi &= ~0xff;
- /* Set exit ramp rate to fast. */
- msr.hi |= (1 << (50 - 32));
- /* Set entry ramp rate to slow. */
- msr.hi &= ~(1 << (51 - 32));
- /* Enable decay mode on C-state entry. */
- msr.hi |= (1 << (52 - 32));
- if (haswell_is_ult()) {
- /* Set the slow ramp rate to be fast ramp rate / 4 */
- msr.hi &= ~(0x3 << (53 - 32));
- msr.hi |= (0x01 << (53 - 32));
- }
- /* Set MIN_VID (31:24) to allow CPU to have full control. */
- msr.lo &= ~0xff000000;
- wrmsr(MSR_VR_MISC_CONFIG, msr);
-
- /* Configure VR_MISC_CONFIG2 MSR. */
- if (haswell_is_ult()) {
- msr = rdmsr(MSR_VR_MISC_CONFIG2);
- msr.lo &= ~0xffff;
- /* Allow CPU to control minimum voltage completely (15:8) and
- * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
- msr.lo |= 0x006f;
- wrmsr(MSR_VR_MISC_CONFIG2, msr);
- }
-}
-
-static void configure_pch_power_sharing(void)
-{
- u32 pch_power, pch_power_ext, pmsync, pmsync2;
- int i;
-
- /* Read PCH Power levels from PCODE */
- pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
- pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
-
- printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
- pch_power, pch_power_ext);
-
- pmsync = RCBA32(PMSYNC_CONFIG);
- pmsync2 = RCBA32(PMSYNC_CONFIG2);
-
- /* Program PMSYNC_TPR_CONFIG PCH power limit values
- * pmsync[0:4] = mailbox[0:5]
- * pmsync[8:12] = mailbox[6:11]
- * pmsync[16:20] = mailbox[12:17]
- */
- for (i = 0; i < 3; i++) {
- u32 level = pch_power & 0x3f;
- pch_power >>= 6;
- pmsync &= ~(0x1f << (i * 8));
- pmsync |= (level & 0x1f) << (i * 8);
- }
- RCBA32(PMSYNC_CONFIG) = pmsync;
-
- /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
- * pmsync2[0:4] = mailbox[23:18]
- * pmsync2[8:12] = mailbox_ext[6:11]
- * pmsync2[16:20] = mailbox_ext[12:17]
- * pmsync2[24:28] = mailbox_ext[18:22]
- */
- pmsync2 &= ~0x1f;
- pmsync2 |= pch_power & 0x1f;
-
- for (i = 1; i < 4; i++) {
- u32 level = pch_power_ext & 0x3f;
- pch_power_ext >>= 6;
- pmsync2 &= ~(0x1f << (i * 8));
- pmsync2 |= (level & 0x1f) << (i * 8);
- }
- RCBA32(PMSYNC_CONFIG2) = pmsync2;
-}
+/* FIXME: For verification purposes only */
+#include <cpu/intel/haswell/hsw_bdw_init_common.c>
int cpu_config_tdp_levels(void)
{
@@ -466,6 +205,59 @@
}
}
+static void initialize_vr_config(void)
+{
+ msr_t msr;
+
+ printk(BIOS_DEBUG, "Initializing VR config.\n");
+
+ /* Configure VR_CURRENT_CONFIG. */
+ msr = rdmsr(MSR_VR_CURRENT_CONFIG);
+ /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
+ * on ULT systems. */
+ msr.hi &= 0xc0000000;
+ msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */
+ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */
+ msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
+
+ if (haswell_is_ult())
+ msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
+ /* Leave the max instantaneous current limit (12:0) to default. */
+ wrmsr(MSR_VR_CURRENT_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG MSR. */
+ msr = rdmsr(MSR_VR_MISC_CONFIG);
+ /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */
+ msr.hi &= ~(0x3ff << (40 - 32));
+ msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
+ /* Set IOUT_OFFSET to 0. */
+ msr.hi &= ~0xff;
+ /* Set exit ramp rate to fast. */
+ msr.hi |= (1 << (50 - 32));
+ /* Set entry ramp rate to slow. */
+ msr.hi &= ~(1 << (51 - 32));
+ /* Enable decay mode on C-state entry. */
+ msr.hi |= (1 << (52 - 32));
+ if (haswell_is_ult()) {
+ /* Set the slow ramp rate to be fast ramp rate / 4 */
+ msr.hi &= ~(0x3 << (53 - 32));
+ msr.hi |= (0x01 << (53 - 32));
+ }
+ /* Set MIN_VID (31:24) to allow CPU to have full control. */
+ msr.lo &= ~0xff000000;
+ wrmsr(MSR_VR_MISC_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG2 MSR. */
+ if (haswell_is_ult()) {
+ msr = rdmsr(MSR_VR_MISC_CONFIG2);
+ msr.lo &= ~0xffff;
+ /* Allow CPU to control minimum voltage completely (15:8) and
+ * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
+ msr.lo |= 0x006f;
+ wrmsr(MSR_VR_MISC_CONFIG2, msr);
+ }
+}
+
static void configure_c_states(void)
{
msr_t msr;
@@ -556,50 +348,6 @@
}
}
-static void configure_misc(void)
-{
- msr_t msr;
-
- msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
- wrmsr(IA32_MISC_ENABLE, msr);
-
- /* Disable Thermal interrupts */
- msr.lo = 0;
- msr.hi = 0;
- wrmsr(IA32_THERM_INTERRUPT, msr);
-
- /* Enable package critical interrupt only */
- msr.lo = 1 << 4;
- msr.hi = 0;
- wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
-}
-
-static void enable_lapic_tpr(void)
-{
- msr_t msr;
-
- msr = rdmsr(MSR_PIC_MSG_CONTROL);
- msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
- wrmsr(MSR_PIC_MSG_CONTROL, msr);
-}
-
-static void configure_dca_cap(void)
-{
- uint32_t feature_flag;
- msr_t msr;
-
- /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- feature_flag = cpu_get_feature_flags_ecx();
- if (feature_flag & CPUID_DCA) {
- msr = rdmsr(IA32_PLATFORM_DCA_CAP);
- msr.lo |= 1;
- wrmsr(IA32_PLATFORM_DCA_CAP, msr);
- }
-}
-
static void set_max_ratio(void)
{
msr_t msr, perf_ctl;
@@ -642,22 +390,6 @@
policy);
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- int num_banks;
-
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & 0xff;
- msr.lo = msr.hi = 0;
- /* TODO(adurbin): This should only be done on a cold boot. Also, some
- * of these banks are core vs package scope. For now every CPU clears
- * every bank. */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-}
-
/* All CPUs including BSP will run the following function. */
static void haswell_init(struct device *cpu)
{
@@ -693,9 +425,6 @@
enable_turbo();
}
-/* MP initialization support. */
-static const void *microcode_patch;
-
static void pre_mp_init(void)
{
/* Setup MTRRs based on physical address size. */
@@ -710,37 +439,6 @@
}
}
-static int get_cpu_count(void)
-{
- msr_t msr;
- int num_threads;
- int num_cores;
-
- msr = rdmsr(MSR_CORE_THREAD_COUNT);
- num_threads = (msr.lo >> 0) & 0xffff;
- num_cores = (msr.lo >> 16) & 0xffff;
- printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
- num_cores, num_threads);
-
- return num_threads;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
- microcode_patch = intel_microcode_find();
- *microcode = microcode_patch;
- *parallel = 1;
-}
-
-static void per_cpu_smm_trigger(void)
-{
- /* Relocate the SMM handler. */
- smm_relocate();
-
- /* After SMM relocation a 2nd microcode load is required. */
- intel_microcode_load_unlocked(microcode_patch);
-}
-
static void post_mp_init(void)
{
/* Now that all APs have been relocated as well as the BSP let SMIs
diff --git a/src/cpu/intel/haswell/hsw_bdw_init_common.c b/src/cpu/intel/haswell/hsw_bdw_init_common.c
new file mode 100644
index 0000000..b32ccf9
--- /dev/null
+++ b/src/cpu/intel/haswell/hsw_bdw_init_common.c
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is being included from other C files! */
+
+/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
+ * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
+ * when a core is woken up. */
+static int pcode_ready(void)
+{
+ int wait_count;
+ const int delay_step = 10;
+
+ wait_count = 0;
+ do {
+ if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
+ return 0;
+ wait_count += delay_step;
+ udelay(delay_step);
+ } while (wait_count < 1000);
+
+ return -1;
+}
+
+static void calibrate_24mhz_bclk(void)
+{
+ int err_code;
+
+ if (pcode_ready() < 0) {
+ printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
+ return;
+ }
+
+ /* A non-zero value initiates the PCODE calibration. */
+ MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
+ MCHBAR32(BIOS_MAILBOX_INTERFACE) =
+ MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
+
+ if (pcode_ready() < 0) {
+ printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
+ return;
+ }
+
+ err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
+
+ printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n",
+ err_code);
+
+ /* Read the calibrated value. */
+ MCHBAR32(BIOS_MAILBOX_INTERFACE) =
+ MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
+
+ if (pcode_ready() < 0) {
+ printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n",
+ MCHBAR32(BIOS_MAILBOX_DATA));
+}
+
+static u32 pcode_mailbox_read(u32 command)
+{
+ if (pcode_ready() < 0) {
+ printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
+ return 0;
+ }
+
+ /* Send command and start transaction */
+ MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
+
+ if (pcode_ready() < 0) {
+ printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
+ return 0;
+ }
+
+ /* Read mailbox */
+ return MCHBAR32(BIOS_MAILBOX_DATA);
+}
+
+static void configure_pch_power_sharing(void)
+{
+ u32 pch_power, pch_power_ext, pmsync, pmsync2;
+ int i;
+
+ /* Read PCH Power levels from PCODE */
+ pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
+ pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
+
+ printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
+ pch_power, pch_power_ext);
+
+ pmsync = RCBA32(PMSYNC_CONFIG);
+ pmsync2 = RCBA32(PMSYNC_CONFIG2);
+
+ /* Program PMSYNC_TPR_CONFIG PCH power limit values
+ * pmsync[0:4] = mailbox[0:5]
+ * pmsync[8:12] = mailbox[6:11]
+ * pmsync[16:20] = mailbox[12:17]
+ */
+ for (i = 0; i < 3; i++) {
+ u32 level = pch_power & 0x3f;
+ pch_power >>= 6;
+ pmsync &= ~(0x1f << (i * 8));
+ pmsync |= (level & 0x1f) << (i * 8);
+ }
+ RCBA32(PMSYNC_CONFIG) = pmsync;
+
+ /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
+ * pmsync2[0:4] = mailbox[23:18]
+ * pmsync2[8:12] = mailbox_ext[6:11]
+ * pmsync2[16:20] = mailbox_ext[12:17]
+ * pmsync2[24:28] = mailbox_ext[18:22]
+ */
+ pmsync2 &= ~0x1f;
+ pmsync2 |= pch_power & 0x1f;
+
+ for (i = 1; i < 4; i++) {
+ u32 level = pch_power_ext & 0x3f;
+ pch_power_ext >>= 6;
+ pmsync2 &= ~(0x1f << (i * 8));
+ pmsync2 |= (level & 0x1f) << (i * 8);
+ }
+ RCBA32(PMSYNC_CONFIG2) = pmsync2;
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+
+ /* Disable Thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ wrmsr(IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+ uint32_t feature_flag;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
+ msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ int i;
+ int num_banks;
+
+ msr = rdmsr(IA32_MCG_CAP);
+ num_banks = msr.lo & 0xff;
+ msr.lo = msr.hi = 0;
+ /* TODO(adurbin): This should only be done on a cold boot. Also, some
+ * of these banks are core vs package scope. For now every CPU clears
+ * every bank. */
+ for (i = 0; i < num_banks; i++)
+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+static int get_cpu_count(void)
+{
+ msr_t msr;
+ int num_threads;
+ int num_cores;
+
+ msr = rdmsr(MSR_CORE_THREAD_COUNT);
+ num_threads = (msr.lo >> 0) & 0xffff;
+ num_cores = (msr.lo >> 16) & 0xffff;
+ printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
+ num_cores, num_threads);
+
+ return num_threads;
+}
+
+/* MP initialization support. */
+static const void *microcode_patch;
+
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+ microcode_patch = intel_microcode_find();
+ *microcode = microcode_patch;
+ *parallel = 1;
+}
+
+static void per_cpu_smm_trigger(void)
+{
+ /* Relocate the SMM handler. */
+ smm_relocate();
+
+ /* After SMM relocation a 2nd microcode load is required. */
+ intel_microcode_load_unlocked(microcode_patch);
+}
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 5e4e028..309c4fa 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -12,28 +12,16 @@
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <southbridge/intel/lynxpoint/pch.h>
#include <smp/node.h>
-#include "haswell.h"
-#define MSR_PRMRR_PHYS_BASE 0x1f4
-#define MSR_PRMRR_PHYS_MASK 0x1f5
-#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
-#define SMM_MCA_CAP_MSR 0x17d
-#define SMM_CPU_SVRSTR_BIT 57
-#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define SMM_CPU_SAVE_EN (1 << 1)
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
+#if CONFIG(CPU_INTEL_HASWELL)
+#include <northbridge/intel/haswell/haswell.h>
+#include <cpu/intel/haswell/haswell.h>
-#define SMRR_SUPPORTED (1 << 11)
-#define PRMRR_SUPPORTED (1 << 12)
-
-
+#elif CONFIG(CPU_INTEL_BROADWELL)
+#include <northbridge/intel/broadwell/broadwell.h>
+#include <cpu/intel/broadwell/broadwell.h>
+#endif
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
@@ -199,7 +187,7 @@
params->uncore_prmrr_base.lo = prmrr_base;
params->uncore_prmrr_base.hi = 0;
params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
- MTRR_PHYS_MASK_VALID;
+ MTRR_PHYS_MASK_VALID;
params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
}
diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc
index 69ea826..59b200b 100644
--- a/src/northbridge/intel/broadwell/Makefile.inc
+++ b/src/northbridge/intel/broadwell/Makefile.inc
@@ -2,7 +2,7 @@
CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include
-bootblock-y += bootblock.c
+bootblock-y += ../haswell/bootblock.c
ramstage-y += acpi.c
@@ -15,7 +15,7 @@
ramstage-y += memmap.c
romstage-y += memmap.c
postcar-y += memmap.c
-ramstage-y += minihd.c
+ramstage-y += ../haswell/minihd.c
ramstage-y += northbridge.c
diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl
index 12296cb..2f9c071 100644
--- a/src/northbridge/intel/broadwell/acpi/broadwell.asl
+++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl
@@ -2,170 +2,7 @@
#include <southbridge/intel/wildcatpoint/iomap.h>
-Name (_HID, EISAID ("PNP0A08")) // PCIe
-Name (_CID, EISAID ("PNP0A03")) // PCI
-
-Name (_BBN, 0)
-
-Device (MCHC)
-{
- Name (_ADR, 0x00000000) // 0:0.0
-
- OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
- Field (MCHP, DWordAcc, NoLock, Preserve)
- {
- Offset (0x70), // ME Base Address
- MEBA, 64,
- Offset (0xa0), // Top of Used Memory
- TOM, 64,
- Offset (0xbc), // Top of Low Used Memory
- TLUD, 32,
- }
-}
-
-// Current Resource Settings
-Name (MCRS, ResourceTemplate()
-{
- // Bus Numbers
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
-
- // IO Region 0
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
-
- // PCI Config Space
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- // IO Region 1
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
-
- // VGA memory (0xa0000-0xbffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000,,, ASEG)
-
- // OPROM reserved (0xc0000-0xc3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
- 0x00004000,,, OPR0)
-
- // OPROM reserved (0xc4000-0xc7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
- 0x00004000,,, OPR1)
-
- // OPROM reserved (0xc8000-0xcbfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
- 0x00004000,,, OPR2)
-
- // OPROM reserved (0xcc000-0xcffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
- 0x00004000,,, OPR3)
-
- // OPROM reserved (0xd0000-0xd3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
- 0x00004000,,, OPR4)
-
- // OPROM reserved (0xd4000-0xd7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
- 0x00004000,,, OPR5)
-
- // OPROM reserved (0xd8000-0xdbfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
- 0x00004000,,, OPR6)
-
- // OPROM reserved (0xdc000-0xdffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
- 0x00004000,,, OPR7)
-
- // BIOS Extension (0xe0000-0xe3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
- 0x00004000,,, ESG0)
-
- // BIOS Extension (0xe4000-0xe7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
- 0x00004000,,, ESG1)
-
- // BIOS Extension (0xe8000-0xebfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
- 0x00004000,,, ESG2)
-
- // BIOS Extension (0xec000-0xeffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
- 0x00004000,,, ESG3)
-
- // System BIOS (0xf0000-0xfffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
- 0x00010000,,, FSEG)
-
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PM01)
-
- // TPM Area (0xfed40000-0xfed44fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
- 0x00005000,,, TPMR)
-})
-
-Method (_CRS, 0, Serialized)
-{
- // Find PCI resource area in MCRS
- CreateDwordField(MCRS, ^PM01._MIN, PMIN)
- CreateDwordField(MCRS, ^PM01._MAX, PMAX)
- CreateDwordField(MCRS, ^PM01._LEN, PLEN)
-
- // Fix up PCI memory region
- // Start with Top of Lower Usable DRAM
- // Lower 20 bits of TOLUD register need to be masked since they contain lock and
- // reserved bits.
- Local0 = ^MCHC.TLUD & (0xfff << 20)
- Local1 = ^MCHC.MEBA
-
- // Check if ME base is equal
- If (Local0 == Local1) {
- // Use Top Of Memory instead
- // Lower 20 bits of TOM register need to be masked since they contain lock and
- // reserved bits.
- Local0 = ^MCHC.TOM & (0x7ffff << 20)
- }
-
- PMIN = Local0
- PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
- PLEN = (PMAX - PMIN) + 1
-
- Return (MCRS)
-}
+#include <northbridge/intel/haswell/acpi/hostbridge.asl>
/* PCI Device Resource Consumption */
Device (PDRC)
@@ -193,5 +30,8 @@
/* PCI IRQ assignment */
#include "pci_irqs.asl"
-/* Configurable TDP */
-#include "ctdp.asl"
+Scope (\_SB.PCI0.MCHC)
+{
+ /* Configurable TDP */
+ #include <northbridge/intel/haswell/acpi/ctdp.asl>
+}
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
deleted file mode 100644
index d661f57..0000000
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/bootblock.h>
-#include <device/pci_ops.h>
-#include <southbridge/intel/wildcatpoint/pci_devs.h>
-#include <northbridge/intel/broadwell/broadwell.h>
-
-void bootblock_early_northbridge_init(void)
-{
- uint32_t reg;
-
- /*
- * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
- * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent
- * non-explicit config accesses use MCFG. This code also assumes that
- * bootblock_northbridge_init() is the first thing called in the non-asm
- * boot block code. The final assumption is that no assembly code is using
- * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
- *
- * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
- */
- reg = 0;
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
-}
diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h
index 1a8e6cf..ed8356d 100644
--- a/src/northbridge/intel/broadwell/broadwell.h
+++ b/src/northbridge/intel/broadwell/broadwell.h
@@ -25,7 +25,8 @@
#define MCH_BROADWELL_REV_E0 0x08
#define MCH_BROADWELL_REV_F0 0x09
-/* Device 0:0.0 PCI configuration space */
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define EPBAR 0x40
#define MCHBAR 0x48
@@ -60,24 +61,26 @@
#define D_LCK (1 << 4)
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-#define CAPID0_A 0xe4
-#define VTD_DISABLE (1 << 23)
-#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
-#define DMAR_LCKDN (1 << 31)
-#define PRSCAPDIS (1 << 2)
-#define MESEG_BASE 0x70 /* Management Engine Base. */
-#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
-#define REMAPBASE 0x90 /* Remap base. */
-#define REMAPLIMIT 0x98 /* Remap limit. */
-#define TOM 0xa0 /* Top of DRAM in memory controller space. */
+#define MESEG_BASE 0x70 /* Management Engine Base */
+#define MESEG_LIMIT 0x78 /* Management Engine Limit */
+#define REMAPBASE 0x90 /* Remap base */
+#define REMAPLIMIT 0x98 /* Remap limit */
+#define TOM 0xa0 /* Top of DRAM in memory controller space */
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
#define BDSM 0xb0 /* Base Data Stolen Memory */
#define BGSM 0xb4 /* Base GTT Stolen Memory */
#define TSEG 0xb8 /* TSEG base */
#define TOLUD 0xbc /* Top of Low Used Memory */
+
#define SKPAD 0xdc /* Scratchpad Data */
+#define CAPID0_A 0xe4
+#define VTD_DISABLE (1 << 23)
+#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
+#define DMAR_LCKDN (1 << 31)
+#define PRSCAPDIS (1 << 2)
+
/* MCHBAR */
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))
@@ -89,7 +92,7 @@
#define GFXVTBAR 0x5400
#define EDRAMBAR 0x5408
#define VTVC0BAR 0x5410
-#define MCH_PAIR 0x5418
+#define INTRDIRCTL 0x5418
#define GDXCBAR 0x5420
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c
index b032782..f752638 100644
--- a/src/northbridge/intel/broadwell/igd.c
+++ b/src/northbridge/intel/broadwell/igd.c
@@ -24,7 +24,7 @@
#include <northbridge/intel/broadwell/igd.h>
#include <types.h>
-#define GT_RETRY 1000
+#define GTT_RETRY 1000
enum {
GT_CDCLK_DEFAULT = 0,
GT_CDCLK_337,
@@ -43,7 +43,7 @@
/* Enable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable Counters */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
@@ -104,10 +104,10 @@
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
/* Set RC6 VIDs */
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
@@ -127,13 +127,13 @@
/* Disable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
/* Enable power well for DP and Audio */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
- (1 << 30), (1 << 30), GT_RETRY),
+ (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END
};
@@ -141,7 +141,7 @@
static const struct reg_script broadwell_early_init_script[] = {
/* Enable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable push bus metric control and shift */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
@@ -206,10 +206,10 @@
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
/* Set RC6 VIDs */
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
@@ -228,12 +228,12 @@
/* Disable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
/* Enable power well for DP and Audio */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
- (1 << 30), (1 << 30), GT_RETRY),
+ (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END
};
@@ -267,13 +267,15 @@
}
int gtt_poll(u32 reg, u32 mask, u32 value)
-{ unsigned int try = GT_RETRY;
+{
+ unsigned int try = GTT_RETRY;
u32 data;
while (try--) {
data = gtt_read(reg);
if ((data & mask) == value)
return 1;
+
udelay(10);
}
@@ -327,21 +329,22 @@
Reference clock is 24MHz. We can choose either a 16
or a 128 step increment. Use 16 if we would have less
than 100 steps otherwise. */
- const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
+ const unsigned int refclock = 24 * 1000 * 1000;
+ const unsigned int hz_limit = refclock / 128 / 100;
unsigned int pwm_increment, pwm_period;
u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
- south_chicken2 |= 1 << 5;
+ south_chicken2 |= LPT_PWM_GRANULARITY;
} else {
pwm_increment = 128;
- south_chicken2 &= ~(1 << 5);
+ south_chicken2 &= ~LPT_PWM_GRANULARITY;
}
gtt_write(SOUTH_CHICKEN2, south_chicken2);
- pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
/* Start with a 50% duty cycle. */
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
@@ -489,7 +492,7 @@
gtt_rmw(0x64810, 0xfffff800, dpdiv);
}
-static void igd_init(struct device *dev)
+static void gma_func0_init(struct device *dev)
{
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
u32 rp1_gfx_freq;
@@ -580,11 +583,11 @@
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static struct device_operations igd_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &igd_init,
+static struct device_operations gma_func0_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gma_func0_init,
.ops_pci = &broadwell_pci_ops,
.acpi_fill_ssdt = gma_generate_ssdt,
};
@@ -603,8 +606,8 @@
0,
};
-static const struct pci_driver igd_driver __pci_driver = {
- .ops = &igd_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
+static const struct pci_driver gma_driver __pci_driver = {
+ .ops = &gma_func0_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c
deleted file mode 100644
index 9df1047..0000000
--- a/src/northbridge/intel/broadwell/minihd.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/mmio.h>
-#include <soc/intel/common/hda_verb.h>
-#include <southbridge/intel/wildcatpoint/ramstage.h>
-#include <northbridge/intel/broadwell/igd.h>
-
-static const u32 minihd_verb_table[] = {
- /* coreboot specific header */
- 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */
- 0x80860101, /* Subsystem ID */
- 4, /* Number of jacks */
-
- /* Enable 3rd Pin and Converter Widget */
- 0x00878101,
-
- /* Pin Widget 5 - PORT B */
- 0x00571c10,
- 0x00571d00,
- 0x00571e56,
- 0x00571f18,
-
- /* Pin Widget 6 - PORT C */
- 0x00671c20,
- 0x00671d00,
- 0x00671e56,
- 0x00671f18,
-
- /* Pin Widget 7 - PORT D */
- 0x00771c30,
- 0x00771d00,
- 0x00771e56,
- 0x00771f18,
-
- /* Disable 3rd Pin and Converter Widget */
- 0x00878100,
-
- /* Dummy entries to fill out the table */
- 0x00878100,
- 0x00878100,
-};
-
-static void minihd_init(struct device *dev)
-{
- struct resource *res;
- u32 reg32;
- u8 *base;
- int codec_mask, i;
-
- /* Find base address */
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (!res)
- return;
-
- base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
-
- /* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* Mini-HD configuration */
- reg32 = read32(base + 0x100c);
- reg32 &= 0xfffc0000;
- reg32 |= 0x4;
- write32(base + 0x100c, reg32);
-
- reg32 = read32(base + 0x1010);
- reg32 &= 0xfffc0000;
- reg32 |= 0x4b;
- write32(base + 0x1010, reg32);
-
- /* Init the codec and write the verb table */
- codec_mask = hda_codec_detect(base);
-
- if (codec_mask) {
- for (i = 3; i >= 0; i--) {
- if (codec_mask & (1 << i))
- hda_codec_init(base, i, sizeof(minihd_verb_table),
- minihd_verb_table);
- }
- }
-
- /* Set EM4/EM5 registers */
- write32(base + 0x0100c, igd_get_reg_em4());
- write32(base + 0x01010, igd_get_reg_em5());
-}
-
-static struct device_operations minihd_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = minihd_init,
- .ops_pci = &broadwell_pci_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
- 0x0a0c, /* Haswell */
- 0x160c, /* Broadwell */
- 0
-};
-
-static const struct pci_driver minihd_driver __pci_driver = {
- .ops = &minihd_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
index 480c17a..bf403f6 100644
--- a/src/northbridge/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -16,227 +16,8 @@
#include <southbridge/intel/wildcatpoint/ramstage.h>
#include <northbridge/intel/broadwell/broadwell.h>
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 pciexbar_reg;
-
- *base = 0;
- *len = 0;
-
- pciexbar_reg = pci_read_config32(dev, index);
-
- if (!(pciexbar_reg & (1 << 0)))
- return 0;
-
- switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28));
- *len = 256 * 1024 * 1024;
- return 1;
- case 1: // 128M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28)|(1 << 27));
- *len = 128 * 1024 * 1024;
- return 1;
- case 2: // 64M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
- (1 << 28)|(1 << 27)|(1 << 26));
- *len = 64 * 1024 * 1024;
- return 1;
- }
-
- return 0;
-}
-
-static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 bar = pci_read_config32(dev, index);
-
- /* If not enabled don't report it */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit */
- *base = bar & ~1;
-
- return 1;
-}
-
-/*
- * There are special BARs that actually are programmed in the MCHBAR. These Intel special
- * features, but they do consume resources that need to be accounted for.
- */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 bar = MCHBAR32(index);
-
- /* If not enabled don't report it */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit */
- *base = bar & ~1;
-
- return 1;
-}
-
-struct fixed_mmio_descriptor {
- unsigned int index;
- u32 size;
- int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
- const char *description;
-};
-
-struct fixed_mmio_descriptor mc_fixed_resources[] = {
- { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
- { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
- { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
- { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
- { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
- { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
-};
-
-/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
-static void mc_add_fixed_mmio_resources(struct device *dev)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
- u32 base;
- u32 size;
- struct resource *resource;
- unsigned int index;
-
- size = mc_fixed_resources[i].size;
- index = mc_fixed_resources[i].index;
- if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
- continue;
-
- resource = new_resource(dev, mc_fixed_resources[i].index);
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
-
- resource->base = base;
- resource->size = size;
- printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
- __func__, mc_fixed_resources[i].description, index,
- (unsigned long)base, (unsigned long)(base + size - 1));
- }
-}
-
-/* Host Memory Map:
- *
- * +--------------------------+ TOUUD
- * | |
- * +--------------------------+ 4GiB
- * | PCI Address Space |
- * +--------------------------+ TOLUD (also maps into MC address space)
- * | iGD |
- * +--------------------------+ BDSM
- * | GTT |
- * +--------------------------+ BGSM
- * | TSEG |
- * +--------------------------+ TSEGMB
- * | Usage DRAM |
- * +--------------------------+ 0
- *
- * Some of the base registers above can be equal, making the size of the regions within 0.
- * This is because the memory controller internally subtracts the base registers from each
- * other to determine sizes of the regions. In other words, the memory map regions are always
- * in a fixed order, no matter what sizes they have.
- */
-
-struct map_entry {
- int reg;
- int is_64_bit;
- int is_limit;
- const char *description;
-};
-
-static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
-{
- uint64_t value;
- uint64_t mask;
-
- /* All registers have a 1MiB granularity */
- mask = ((1ULL << 20) - 1);
- mask = ~mask;
-
- value = 0;
-
- if (entry->is_64_bit) {
- value = pci_read_config32(dev, entry->reg + 4);
- value <<= 32;
- }
-
- value |= pci_read_config32(dev, entry->reg);
- value &= mask;
-
- if (entry->is_limit)
- value |= ~mask;
-
- *result = value;
-}
-
-#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
- { \
- .reg = reg_, \
- .is_64_bit = is_64_, \
- .is_limit = is_limit_, \
- .description = desc_, \
- }
-
-#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
-#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
-
-enum {
- TOM_REG,
- TOUUD_REG,
- MESEG_BASE_REG,
- MESEG_LIMIT_REG,
- REMAP_BASE_REG,
- REMAP_LIMIT_REG,
- TOLUD_REG,
- BGSM_REG,
- BDSM_REG,
- TSEG_REG,
- /* Must be last */
- NUM_MAP_ENTRIES,
-};
-
-static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
- [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
- [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
- [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
- [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
- [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
- [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
- [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
- [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
- [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
- [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
-};
-
-static void mc_read_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
- read_map_entry(dev, &memory_map[i], &values[i]);
- }
-}
-
-static void mc_report_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
- printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
- memory_map[i].description, values[i]);
- }
- /* One can validate the BDSM and BGSM against the GGC */
- printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
-}
+/* FIXME: For verification purposes only */
+#include <northbridge/intel/haswell/northbridge_common.c>
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{
@@ -248,8 +29,8 @@
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Read in the MAP registers and report their values */
- mc_read_map_entries(dev, &mc_values[0]);
- mc_report_map_entries(dev, &mc_values[0]);
+ mc_read_map_entries(dev, mc_values);
+ mc_report_map_entries(dev, mc_values);
/*
* DMA Protected Range can be reserved below TSEG for PCODE patch
@@ -339,41 +120,20 @@
*resource_cnt = index;
}
-static void mc_read_resources(struct device *dev)
-{
- int index = 0;
- const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
-
- /* Read standard PCI resources */
- pci_dev_read_resources(dev);
-
- /* Add all fixed MMIO resources */
- mc_add_fixed_mmio_resources(dev);
-
- /* Add VT-d MMIO resources, if capable */
- if (vtd_capable) {
- mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
- mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
- }
-
- /* Calculate and add DRAM resources */
- mc_add_dram_resources(dev, &index);
-}
-
-static void systemagent_init(struct device *dev)
+static void northbridge_init(struct device *dev)
{
struct soc_power_limits_config *config;
u8 bios_reset_cpl, pair;
/* Enable Power Aware Interrupt Routing */
- pair = MCHBAR8(MCH_PAIR);
+ pair = MCHBAR8(INTRDIRCTL);
pair &= ~0x7; /* Clear 2:0 */
pair |= 0x4; /* Fixed Priority */
- MCHBAR8(MCH_PAIR) = pair;
+ MCHBAR8(INTRDIRCTL) = pair;
/*
* Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
- * that BIOS has initialized memory and power management
+ * that BIOS has initialized memory and power management.
*/
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
bios_reset_cpl |= 3;
@@ -391,7 +151,7 @@
.acpi_fill_ssdt = generate_cpu_entries,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = systemagent_init,
+ .init = northbridge_init,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/northbridge/intel/broadwell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl
similarity index 78%
rename from src/northbridge/intel/broadwell/acpi/ctdp.asl
rename to src/northbridge/intel/haswell/acpi/ctdp.asl
index 8391482..59fd37c 100644
--- a/src/northbridge/intel/broadwell/acpi/ctdp.asl
+++ b/src/northbridge/intel/haswell/acpi/ctdp.asl
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-Scope (\_SB.PCI0.MCHC)
-{
Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
Name (CTCC, 0) /* CTDP Current Selection */
Name (CTCN, 0) /* CTDP Nominal Select */
@@ -9,8 +7,7 @@
Name (CTCU, 2) /* CTDP Up Select */
Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory,
- Add (MCH_BASE_ADDRESS, 0x5000), 0x1000)
+ OperationRegion (MCHB, SystemMemory, Add (DEFAULT_MCHBAR, 0x5000), 0x1000)
Field (MCHB, DWordAcc, Lock, Preserve)
{
Offset (0x930), /* PACKAGE_POWER_SKU */
@@ -62,17 +59,16 @@
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
- Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_SB.CP00._PSS), Local1)
+ Local0 = One /* Start at P1 */
+ Local1 = SizeOf (\_SB.CP00._PSS)
- While (LLess (Local0, Local1)) {
+ While (Local0 < Local1) {
/* Store _PSS entry Control value to Local2 */
- ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
- If (LEqual (Local2, Arg0)) {
- Return (Subtract (Local0, 1))
+ Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
+ If (Local2 == Arg0) {
+ Return (Local0 - 1)
}
- Increment (Local0)
+ Local0++
}
Return (0)
@@ -81,9 +77,19 @@
/* Calculate PL2 based on chip type */
Method (CPL2, 1, NotSerialized)
{
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
+ If (\ISLP ()) {
+ /* Haswell ULT PL2 = 25W */
+ Return (25 * 8)
+ } Else {
+ /* Haswell Mobile PL2 = 1.25 * PL1 */
+ Return ((Arg0 * 125) / 100)
+ }
+#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL)
/* Haswell ULT PL2 = 25W */
/* FIXME: update for broadwell */
Return (Multiply (25, 8))
+#endif
}
/* Set Config TDP Down */
@@ -100,23 +106,23 @@
Store ("Set TDP Down", Debug)
/* Set CTC */
- Store (CTCD, CTCS)
+ CTCS = CTCD
/* Set TAR */
- Store (TARD, TARS)
+ TARS = TARD
/* Set PPC limit and notify OS */
- Store (PSSS (TARD), PPCM)
+ PPCM = PSSS (TARD)
PPCN ()
/* Set PL2 */
- Store (CPL2 (CTDD), PL2V)
+ PL2V = CPL2 (CTDD)
/* Set PL1 */
- Store (CTDD, PL1V)
+ PL1V = CTDD
/* Store the new TDP Down setting */
- Store (CTCD, CTCC)
+ CTCC = CTCD
Release (CTCM)
Return (1)
@@ -128,7 +134,7 @@
If (Acquire (CTCM, 100)) {
Return (0)
}
- If (LEqual (CTCN, CTCC)) {
+ If (CTCN == CTCC) {
Release (CTCM)
Return (0)
}
@@ -136,23 +142,23 @@
Store ("Set TDP Nominal", Debug)
/* Set PL1 */
- Store (CTDN, PL1V)
+ PL1V = CTDN
/* Set PL2 */
- Store (CPL2 (CTDN), PL2V)
+ PL2V = CPL2 (CTDN)
/* Set PPC limit and notify OS */
- Store (PSSS (TARN), PPCM)
+ PPCM = PSSS (TARN)
PPCN ()
/* Set TAR */
- Store (TARN, TARS)
+ TARS = TARN
/* Set CTC */
- Store (CTCN, CTCS)
+ CTCS = CTCN
/* Store the new TDP Nominal setting */
- Store (CTCN, CTCC)
+ CTCC = CTCN
Release (CTCM)
Return (1)
@@ -161,7 +167,7 @@
/* Calculate PL1 value based on requested TDP */
Method (TDPP, 1, NotSerialized)
{
- Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
+ Return (((PUNI - 1) << 2) * Arg0)
}
/* Enable Controllable TDP to limit PL1 to requested value */
@@ -174,19 +180,19 @@
Store ("Enable PL1 Limit", Debug)
/* Set _PPC to LFM */
- Store (PSSS (LFM_), Local0)
- Add (Local0, 1, PPCM)
+ Local0 = PSSS (LFM_)
+ PPCM = Local0 + 1
\PPCN ()
/* Set TAR to LFM-1 */
- Subtract (LFM_, 1, TARS)
+ TARS = LFM_ - 1
/* Set PL1 to desired value */
- Store (PL1V, SPL1)
- Store (TDPP (Arg0), PL1V)
+ SPL1 = PL1V
+ PL1V = TDPP (Arg0)
/* Set PL1 CLAMP bit */
- Store (One, PL1C)
+ PL1C = 1
Release (CTCM)
Return (1)
@@ -202,19 +208,18 @@
Store ("Disable PL1 Limit", Debug)
/* Clear PL1 CLAMP bit */
- Store (Zero, PL1C)
+ PL1C = 0
/* Set PL1 to normal value */
- Store (SPL1, PL1V)
+ PL1V = SPL1
/* Set TAR to 0 */
- Store (Zero, TARS)
+ TARS = 0
/* Set _PPC to 0 */
- Store (Zero, PPCM)
+ PPCM = 0
\PPCN ()
Release (CTCM)
Return (1)
}
-}
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index 4a9debf..7ab47ac 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h"
+
#include "hostbridge.asl"
#include "peg.asl"
#include <southbridge/intel/common/rcba.h>
@@ -30,6 +31,6 @@
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
- Return(PDRS)
+ Return (PDRS)
}
}
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index dd4b79a..5e694a6 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -1,18 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+Name (_HID, EISAID ("PNP0A08")) // PCIe
+Name (_CID, EISAID ("PNP0A03")) // PCI
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
-
-Name(_BBN, 0)
+Name (_BBN, 0)
Device (MCHC)
{
- Name(_ADR, 0x00000000) // 0:0.0
+ Name (_ADR, 0x00000000) // 0:0.0
- OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+ OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
Field (MCHP, DWordAcc, NoLock, Preserve)
{
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
Offset (0x40), // EPBAR
EPEN, 1, // Enable
, 11, //
@@ -34,10 +34,12 @@
DMEN, 1, // Enable
, 11, //
DMBR, 24, // DMIBAR
+#endif
Offset (0x70), // ME Base Address
MEBA, 64,
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
// ...
Offset (0x80), // PAM0
@@ -74,6 +76,7 @@
, 2,
PM6H, 2,
, 2,
+#endif
Offset (0xa0), // Top of Used Memory
TOM, 64,
@@ -82,223 +85,9 @@
TLUD, 32,
}
- Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
- Name (CTCC, 0) /* CTDP Current Selection */
- Name (CTCN, 0) /* CTDP Nominal Select */
- Name (CTCD, 1) /* CTDP Down Select */
- Name (CTCU, 2) /* CTDP Up Select */
- Name (SPL1, 0) /* Saved PL1 value */
-
- OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000)
- Field (MCHB, DWordAcc, Lock, Preserve)
- {
- Offset (0x930), /* PACKAGE_POWER_SKU */
- CTDN, 15, /* CTDP Nominal PL1 */
- Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
- PUNI, 4, /* Power Units */
- , 4,
- EUNI, 5, /* Energy Units */
- , 3,
- TUNI, 4, /* Time Units */
- Offset (0x958), /* PLATFORM_INFO */
- , 40,
- LFM_, 8, /* Maximum Efficiency Ratio (LFM) */
- Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
- PL1V, 15, /* Power Limit 1 Value */
- PL1E, 1, /* Power Limit 1 Enable */
- PL1C, 1, /* Power Limit 1 Clamp */
- PL1T, 7, /* Power Limit 1 Time */
- Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
- PL2V, 15, /* Power Limit 2 Value */
- PL2E, 1, /* Power Limit 2 Enable */
- PL2C, 1, /* Power Limit 2 Clamp */
- PL2T, 7, /* Power Limit 2 Time */
- Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
- TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
- Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
- CTDD, 15, /* CTDP Down PL1 */
- , 1,
- TARD, 8, /* CTDP Down Turbo Activation Ratio */
- Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
- CTDU, 15, /* CTDP Up PL1 */
- , 1,
- TARU, 8, /* CTDP Up Turbo Activation Ratio */
- Offset (0xf50), /* CONFIG_TDP_CONTROL */
- CTCS, 2, /* CTDP Select */
- Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
- TARS, 8, /* Turbo Activation Ratio Select */
- }
-
- /*
- * Search CPU0 _PSS looking for control = arg0 and then
- * return previous P-state entry number for new _PPC
- *
- * Format of _PSS:
- * Name (_PSS, Package () {
- * Package (6) { freq, power, tlat, blat, control, status }
- * }
- */
- External (\_SB.CP00._PSS)
- Method (PSSS, 1, NotSerialized)
- {
- Local0 = One /* Start at P1 */
- Local1 = SizeOf (\_SB.CP00._PSS)
-
- While (Local0 < Local1) {
- /* Store _PSS entry Control value to Local2 */
- Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
- If (Local2 == Arg0) {
- Return (Local0 - 1)
- }
- Local0++
- }
-
- Return (0)
- }
-
- /* Calculate PL2 based on chip type */
- Method (CPL2, 1, NotSerialized)
- {
- If (\ISLP ()) {
- /* Haswell ULT PL2 = 25W */
- Return (25 * 8)
- } Else {
- /* Haswell Mobile PL2 = 1.25 * PL1 */
- Return ((Arg0 * 125) / 100)
- }
- }
-
- /* Set Config TDP Down */
- Method (STND, 0, Serialized)
- {
- If (Acquire (CTCM, 100)) {
- Return (0)
- }
- If (LEqual (CTCD, CTCC)) {
- Release (CTCM)
- Return (0)
- }
-
- Store ("Set TDP Down", Debug)
-
- /* Set CTC */
- CTCS = CTCD
-
- /* Set TAR */
- TARS = TARD
-
- /* Set PPC limit and notify OS */
- PPCM = PSSS (TARD)
- PPCN ()
-
- /* Set PL2 */
- PL2V = CPL2 (CTDD)
-
- /* Set PL1 */
- PL1V = CTDD
-
- /* Store the new TDP Down setting */
- CTCC = CTCD
-
- Release (CTCM)
- Return (1)
- }
-
- /* Set Config TDP Nominal from Down */
- Method (STDN, 0, Serialized)
- {
- If (Acquire (CTCM, 100)) {
- Return (0)
- }
- If (CTCN == CTCC) {
- Release (CTCM)
- Return (0)
- }
-
- Store ("Set TDP Nominal", Debug)
-
- /* Set PL1 */
- PL1V = CTDN
-
- /* Set PL2 */
- PL2V = CPL2 (CTDN)
-
- /* Set PPC limit and notify OS */
- PPCM = PSSS (TARN)
- PPCN ()
-
- /* Set TAR */
- TARS = TARN
-
- /* Set CTC */
- CTCS = CTCN
-
- /* Store the new TDP Nominal setting */
- CTCC = CTCN
-
- Release (CTCM)
- Return (1)
- }
-
- /* Calculate PL1 value based on requested TDP */
- Method (TDPP, 1, NotSerialized)
- {
- Return (((PUNI - 1) << 2) * Arg0)
- }
-
- /* Enable Controllable TDP to limit PL1 to requested value */
- Method (CTLE, 1, Serialized)
- {
- If (Acquire (CTCM, 100)) {
- Return (0)
- }
-
- Store ("Enable PL1 Limit", Debug)
-
- /* Set _PPC to LFM */
- Local0 = PSSS (LFM_)
- PPCM = Local0 + 1
- \PPCN ()
-
- /* Set TAR to LFM-1 */
- TARS = LFM_ - 1
-
- /* Set PL1 to desired value */
- SPL1 = PL1V
- PL1V = TDPP (Arg0)
-
- /* Set PL1 CLAMP bit */
- PL1C = 1
-
- Release (CTCM)
- Return (1)
- }
-
- /* Disable Controllable TDP */
- Method (CTLD, 0, Serialized)
- {
- If (Acquire (CTCM, 100)) {
- Return (0)
- }
-
- Store ("Disable PL1 Limit", Debug)
-
- /* Clear PL1 CLAMP bit */
- PL1C = 0
-
- /* Set PL1 to normal value */
- PL1V = SPL1
-
- /* Set TAR to 0 */
- TARS = 0
-
- /* Set _PPC to 0 */
- PPCM = 0
- \PPCN ()
-
- Release (CTCM)
- Return (1)
- }
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
+ #include "ctdp.asl"
+#endif
}
// Current Resource Settings
@@ -440,7 +229,7 @@
PMIN = Local0
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
- PLEN = PMAX - PMIN + 1
+ PLEN = (PMAX - PMIN) + 1
Return (MCRS)
}
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 41f18be..391d837 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -2,7 +2,13 @@
#include <arch/bootblock.h>
#include <device/pci_ops.h>
-#include "haswell.h"
+
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
+#include <northbridge/intel/haswell/haswell.h>
+
+#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL)
+#include <northbridge/intel/broadwell/broadwell.h>
+#endif
void bootblock_early_northbridge_init(void)
{
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 68072ff..42379d6 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -4,18 +4,18 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <console/console.h>
#include <bootmode.h>
+#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <drivers/intel/gma/i915_reg.h>
-#include <drivers/intel/gma/i915.h>
-#include <drivers/intel/gma/libgfxinit.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <drivers/intel/gma/opregion.h>
#include <string.h>
+#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <drivers/intel/gma/libgfxinit.h>
+#include <drivers/intel/gma/opregion.h>
+#include <cpu/intel/haswell/haswell.h>
#include <types.h>
#include "chip.h"
@@ -507,8 +507,8 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
- .acpi_fill_ssdt = gma_generate_ssdt,
.ops_pci = &pci_dev_ops_pci,
+ .acpi_fill_ssdt = gma_generate_ssdt,
};
static const unsigned short pci_device_ids[] = {
@@ -527,7 +527,7 @@
0,
};
-static const struct pci_driver pch_lpc __pci_driver = {
+static const struct pci_driver gma_driver __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bd44168..db4d4d1 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -12,9 +12,14 @@
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
-#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#define DEFAULT_MCHBAR 0xfed10000 /* 32 KB */
+#define MCH_BASE_SIZE 0x8000
+
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DMI_BASE_SIZE 0x1000
+
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+#define EP_BASE_SIZE 0x1000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL
#define GFXVT_BASE_SIZE 0x1000
@@ -22,6 +27,10 @@
#define VTVC0_BASE_ADDRESS 0xfed91000ULL
#define VTVC0_BASE_SIZE 0x1000
+#define EDRAM_BASE_SIZE 0x4000
+
+#define GDXC_BASE_SIZE 0x1000
+
#include <southbridge/intel/lynxpoint/pch.h>
/* Everything below this line is ignored in the DSDT */
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index de2ce06..00151db 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -6,11 +6,21 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
+
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
#include <southbridge/intel/lynxpoint/hda_verb.h>
+#define HDA_VENDEV_ID 0x80862807
+
+#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL)
+#include <soc/intel/common/hda_verb.h>
+#include <southbridge/intel/wildcatpoint/ramstage.h>
+#include <northbridge/intel/broadwell/igd.h>
+#define HDA_VENDEV_ID 0x80862808
+#endif
static const u32 minihd_verb_table[] = {
/* coreboot specific header */
- 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */
+ HDA_VENDEV_ID, /* Codec Vendor / Device ID: Intel Haswell/Broadwell Mini-HD */
0x80860101, /* Subsystem ID */
4, /* Number of jacks */
@@ -82,6 +92,12 @@
minihd_verb_table);
}
}
+
+#if CONFIG(NORTHBRIDGE_INTEL_BROADWELL)
+ /* Set EM4/EM5 registers */
+ write32(base + 0x0100c, igd_get_reg_em4());
+ write32(base + 0x01010, igd_get_reg_em5());
+#endif
}
static struct device_operations minihd_ops = {
@@ -92,6 +108,7 @@
.ops_pci = &pci_dev_ops_pci,
};
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL)
static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 };
static const struct pci_driver haswell_minihd __pci_driver = {
@@ -99,3 +116,18 @@
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
+
+#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL)
+static const unsigned short pci_device_ids[] = {
+ 0x0a0c, /* Haswell */
+ 0x160c, /* Broadwell */
+ 0
+};
+
+static const struct pci_driver minihd_driver __pci_driver = {
+ .ops = &minihd_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
+#endif
+
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index ef7742e..cb9fe50 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -16,41 +16,6 @@
#include "chip.h"
#include "haswell.h"
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 pciexbar_reg, mask;
-
- *base = 0;
- *len = 0;
-
- pciexbar_reg = pci_read_config32(dev, index);
-
- if (!(pciexbar_reg & (1 << 0)))
- return 0;
-
- switch ((pciexbar_reg >> 1) & 3) {
- case 0: /* 256MB */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
- *base = pciexbar_reg & mask;
- *len = 256 * 1024 * 1024;
- return 1;
- case 1: /* 128M */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
- mask |= (1 << 27);
- *base = pciexbar_reg & mask;
- *len = 128 * 1024 * 1024;
- return 1;
- case 2: /* 64M */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
- mask |= (1 << 27) | (1 << 26);
- *base = pciexbar_reg & mask;
- *len = 64 * 1024 * 1024;
- return 1;
- }
-
- return 0;
-}
-
static const char *northbridge_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -79,196 +44,8 @@
.write_acpi_tables = northbridge_write_acpi_tables,
};
-static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 bar = pci_read_config32(dev, index);
-
- /* If not enabled don't report it */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit */
- *base = bar & ~1;
-
- return 1;
-}
-
-/*
- * There are special BARs that actually are programmed in the MCHBAR. These Intel special
- * features, but they do consume resources that need to be accounted for.
- */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
-{
- u32 bar = MCHBAR32(index);
-
- /* If not enabled don't report it */
- if (!(bar & 0x1))
- return 0;
-
- /* Knock down the enable bit */
- *base = bar & ~1;
-
- return 1;
-}
-
-struct fixed_mmio_descriptor {
- unsigned int index;
- u32 size;
- int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
- const char *description;
-};
-
-#define SIZE_KB(x) ((x) * 1024)
-struct fixed_mmio_descriptor mc_fixed_resources[] = {
- { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" },
- { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" },
- { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" },
- { EPBAR, SIZE_KB(4), get_bar, "EPBAR" },
- { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" },
- { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" },
-};
-#undef SIZE_KB
-
-/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
-static void mc_add_fixed_mmio_resources(struct device *dev)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
- u32 base;
- u32 size;
- struct resource *resource;
- unsigned int index;
-
- size = mc_fixed_resources[i].size;
- index = mc_fixed_resources[i].index;
- if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
- continue;
-
- resource = new_resource(dev, mc_fixed_resources[i].index);
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
-
- resource->base = base;
- resource->size = size;
- printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
- __func__, mc_fixed_resources[i].description, index,
- (unsigned long)base, (unsigned long)(base + size - 1));
- }
-}
-
-/* Host Memory Map:
- *
- * +--------------------------+ TOUUD
- * | |
- * +--------------------------+ 4GiB
- * | PCI Address Space |
- * +--------------------------+ TOLUD (also maps into MC address space)
- * | iGD |
- * +--------------------------+ BDSM
- * | GTT |
- * +--------------------------+ BGSM
- * | TSEG |
- * +--------------------------+ TSEGMB
- * | Usage DRAM |
- * +--------------------------+ 0
- *
- * Some of the base registers above can be equal, making the size of the regions within 0.
- * This is because the memory controller internally subtracts the base registers from each
- * other to determine sizes of the regions. In other words, the memory map regions are always
- * in a fixed order, no matter what sizes they have.
- */
-
-struct map_entry {
- int reg;
- int is_64_bit;
- int is_limit;
- const char *description;
-};
-
-static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
-{
- uint64_t value;
- uint64_t mask;
-
- /* All registers have a 1MiB granularity */
- mask = ((1ULL << 20) - 1);
- mask = ~mask;
-
- value = 0;
-
- if (entry->is_64_bit) {
- value = pci_read_config32(dev, entry->reg + 4);
- value <<= 32;
- }
-
- value |= pci_read_config32(dev, entry->reg);
- value &= mask;
-
- if (entry->is_limit)
- value |= ~mask;
-
- *result = value;
-}
-
-#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
- { \
- .reg = reg_, \
- .is_64_bit = is_64_, \
- .is_limit = is_limit_, \
- .description = desc_, \
- }
-
-#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
-#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
-
-enum {
- TOM_REG,
- TOUUD_REG,
- MESEG_BASE_REG,
- MESEG_LIMIT_REG,
- REMAP_BASE_REG,
- REMAP_LIMIT_REG,
- TOLUD_REG,
- BGSM_REG,
- BDSM_REG,
- TSEG_REG,
- /* Must be last */
- NUM_MAP_ENTRIES,
-};
-
-static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
- [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
- [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
- [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
- [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
- [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
- [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
- [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
- [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
- [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
- [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
-};
-
-static void mc_read_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
- read_map_entry(dev, &memory_map[i], &values[i]);
- }
-}
-
-static void mc_report_map_entries(struct device *dev, uint64_t *values)
-{
- int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
- printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
- memory_map[i].description, values[i]);
- }
- /* One can validate the BDSM and BGSM against the GGC */
- printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
-}
+/* FIXME: For verification purposes only */
+#include <northbridge/intel/haswell/northbridge_common.c>
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{
@@ -277,8 +54,8 @@
uint64_t mc_values[NUM_MAP_ENTRIES];
/* Read in the MAP registers and report their values */
- mc_read_map_entries(dev, &mc_values[0]);
- mc_report_map_entries(dev, &mc_values[0]);
+ mc_read_map_entries(dev, mc_values);
+ mc_report_map_entries(dev, mc_values);
/*
* These are the host memory ranges that should be added:
@@ -357,27 +134,6 @@
*resource_cnt = index;
}
-static void mc_read_resources(struct device *dev)
-{
- int index = 0;
- const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
-
- /* Read standard PCI resources */
- pci_dev_read_resources(dev);
-
- /* Add all fixed MMIO resources */
- mc_add_fixed_mmio_resources(dev);
-
- /* Add VT-d MMIO resources, if capable */
- if (vtd_capable) {
- mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
- mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
- }
-
- /* Calculate and add DRAM resources */
- mc_add_dram_resources(dev, &index);
-}
-
/*
* The Mini-HD audio device is disabled whenever the IGD is. This is because it provides
* audio over the integrated graphics port(s), which requires the IGD to be functional.
@@ -422,7 +178,7 @@
{
u8 bios_reset_cpl, pair;
- /* Enable Power Aware Interrupt Routing. */
+ /* Enable Power Aware Interrupt Routing */
pair = MCHBAR8(INTRDIRCTL);
pair &= ~0x7; /* Clear 2:0 */
pair |= 0x4; /* Fixed Priority */
@@ -439,7 +195,7 @@
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
- /* Configure turbo power limits 1ms after reset complete bit. */
+ /* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
set_power_limits(28);
diff --git a/src/northbridge/intel/haswell/northbridge_common.c b/src/northbridge/intel/haswell/northbridge_common.c
new file mode 100644
index 0000000..21a49ab
--- /dev/null
+++ b/src/northbridge/intel/haswell/northbridge_common.c
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is being included from other C files! */
+
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
+{
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ pciexbar_reg = pci_read_config32(dev, index);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: /* 256MB */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) |
+ (1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) |
+ (1 << 27) | (1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
+{
+ u32 bar = pci_read_config32(dev, index);
+
+ /* If not enabled don't report it */
+ if (!(bar & 1))
+ return 0;
+
+ /* Knock down the enable bit */
+ *base = bar & ~1;
+
+ return 1;
+}
+
+/*
+ * There are special BARs that actually are programmed in the MCHBAR. These Intel special
+ * features, but they do consume resources that need to be accounted for.
+ */
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
+{
+ u32 bar = MCHBAR32(index);
+
+ /* If not enabled don't report it */
+ if (!(bar & 1))
+ return 0;
+
+ /* Knock down the enable bit */
+ *base = bar & ~1;
+
+ return 1;
+}
+
+struct fixed_mmio_descriptor {
+ unsigned int index;
+ u32 size;
+ int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
+ const char *description;
+};
+
+struct fixed_mmio_descriptor mc_fixed_resources[] = {
+ { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
+ { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
+ { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
+ { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
+ { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
+ { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
+};
+
+/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
+static void mc_add_fixed_mmio_resources(struct device *dev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
+ u32 base;
+ u32 size;
+ struct resource *resource;
+ unsigned int index;
+
+ size = mc_fixed_resources[i].size;
+ index = mc_fixed_resources[i].index;
+ if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
+ continue;
+
+ resource = new_resource(dev, mc_fixed_resources[i].index);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+
+ resource->base = base;
+ resource->size = size;
+ printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
+ __func__, mc_fixed_resources[i].description, index,
+ (unsigned long)base, (unsigned long)(base + size - 1));
+ }
+}
+
+/*
+ * Host Memory Map:
+ *
+ * +--------------------------+ TOUUD
+ * | |
+ * +--------------------------+ 4GiB
+ * | PCI Address Space |
+ * +--------------------------+ TOLUD (also maps into MC address space)
+ * | iGD |
+ * +--------------------------+ BDSM
+ * | GTT |
+ * +--------------------------+ BGSM
+ * | TSEG |
+ * +--------------------------+ TSEGMB
+ * | Usage DRAM |
+ * +--------------------------+ 0
+ *
+ * Some of the base registers above can be equal, making the size of the regions within 0.
+ * This is because the memory controller internally subtracts the base registers from each
+ * other to determine sizes of the regions. In other words, the memory map regions are always
+ * in a fixed order, no matter what sizes they have.
+ */
+
+struct map_entry {
+ int reg;
+ int is_64_bit;
+ int is_limit;
+ const char *description;
+};
+
+static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
+{
+ uint64_t value;
+ uint64_t mask;
+
+ /* All registers have a 1MiB granularity */
+ mask = ((1ULL << 20) - 1);
+ mask = ~mask;
+
+ value = 0;
+
+ if (entry->is_64_bit) {
+ value = pci_read_config32(dev, entry->reg + 4);
+ value <<= 32;
+ }
+
+ value |= pci_read_config32(dev, entry->reg);
+ value &= mask;
+
+ if (entry->is_limit)
+ value |= ~mask;
+
+ *result = value;
+}
+
+#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
+ { \
+ .reg = reg_, \
+ .is_64_bit = is_64_, \
+ .is_limit = is_limit_, \
+ .description = desc_, \
+ }
+
+#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
+
+enum {
+ TOM_REG,
+ TOUUD_REG,
+ MESEG_BASE_REG,
+ MESEG_LIMIT_REG,
+ REMAP_BASE_REG,
+ REMAP_LIMIT_REG,
+ TOLUD_REG,
+ BGSM_REG,
+ BDSM_REG,
+ TSEG_REG,
+ /* Must be last */
+ NUM_MAP_ENTRIES,
+};
+
+static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
+ [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
+ [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+ [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
+ [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
+ [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
+ [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
+ [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+ [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+ [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+ [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
+};
+
+static void mc_read_map_entries(struct device *dev, uint64_t *values)
+{
+ int i;
+ for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ read_map_entry(dev, &memory_map[i], &values[i]);
+ }
+}
+
+static void mc_report_map_entries(struct device *dev, uint64_t *values)
+{
+ int i;
+ for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
+ memory_map[i].description, values[i]);
+ }
+ /* One can validate the BDSM and BGSM against the GGC */
+ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
+}
+
+static void mc_add_dram_resources(struct device *dev, int *resource_cnt);
+
+static void mc_read_resources(struct device *dev)
+{
+ int index = 0;
+ const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+
+ /* Read standard PCI resources */
+ pci_dev_read_resources(dev);
+
+ /* Add all fixed MMIO resources */
+ mc_add_fixed_mmio_resources(dev);
+
+ /* Add VT-d MMIO resources, if capable */
+ if (vtd_capable) {
+ mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
+ mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
+ }
+
+ /* Calculate and add DRAM resources */
+ mc_add_dram_resources(dev, &index);
+}
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 8ea4175..d3c078f 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -22,7 +22,7 @@
if (cpuidr.eax < 0x80000004) {
strcpy(cpu_string, "Platform info not available");
} else {
- u32 *p = (u32*) cpu_string;
+ u32 *p = (u32 *)cpu_string;
for (i = 2; i <= 4; i++) {
cpuidr = cpuid(index + i);
*p++ = cpuidr.eax;
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 0f59d70..1b6f0b2 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -9,23 +9,16 @@
*/
static void enable_spi_prefetch(void)
{
- u8 reg8;
- pci_devfn_t dev;
-
- dev = PCI_DEV(0, 0x1f, 0);
-
- reg8 = pci_read_config8(dev, 0xdc);
+ u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
}
static void map_rcba(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-
- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}
static void enable_port80_on_lpc(void)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 291a554..cf2a5f7 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -189,6 +189,7 @@
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
+#define PCH_DEV_LPC PCH_LPC_DEV
#define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0
diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c
index 55bb1c3..1e27ed6 100644
--- a/src/southbridge/intel/wildcatpoint/bootblock.c
+++ b/src/southbridge/intel/wildcatpoint/bootblock.c
@@ -25,7 +25,7 @@
static void map_rcba(void)
{
- pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+ pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}
static void enable_port80_on_lpc(void)
@@ -43,18 +43,18 @@
u8 ssfc;
/* Observe SPI Descriptor Component Section 0 */
- SPIBAR32(SPIBAR_FDOC) = 0x1000;
+ SPIBAR32(FDOC) = 0x1000;
/* Extract the Write/Erase SPI Frequency from descriptor */
- fdod = SPIBAR32(SPIBAR_FDOD);
+ fdod = SPIBAR32(FDOD);
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
- ssfc = SPIBAR8(SPIBAR_SSFC + 2);
+ ssfc = SPIBAR8(SSFC + 2);
ssfc &= ~7;
ssfc |= fdod;
- SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
+ SPIBAR8(SSFC + 2) = ssfc;
}
const struct reg_script pch_early_init_script[] = {
diff --git a/src/southbridge/intel/wildcatpoint/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h
index 241569e..37e62bb 100644
--- a/src/southbridge/intel/wildcatpoint/iomap.h
+++ b/src/southbridge/intel/wildcatpoint/iomap.h
@@ -9,6 +9,9 @@
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
+/* Haswell uses this name */
+#define DEFAULT_MCHBAR MCH_BASE_ADDRESS
+
#define DMI_BASE_ADDRESS 0xfed18000
#define DMI_BASE_SIZE 0x1000
@@ -24,6 +27,9 @@
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x4000
+/* Lynxpoint uses this name */
+#define DEFAULT_RCBA RCBA_BASE_ADDRESS
+
#define HPET_BASE_ADDRESS 0xfed00000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL
diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c
index efee415..f449c69 100644
--- a/src/southbridge/intel/wildcatpoint/pch.c
+++ b/src/southbridge/intel/wildcatpoint/pch.c
@@ -48,15 +48,15 @@
{
u32 fdoc;
- fdoc = SPIBAR32(SPIBAR_FDOC);
+ fdoc = SPIBAR32(FDOC);
fdoc &= ~0x00007ffc;
- SPIBAR32(SPIBAR_FDOC) = fdoc;
+ SPIBAR32(FDOC) = fdoc;
fdoc |= 0x00004000;
fdoc |= id * 4;
- SPIBAR32(SPIBAR_FDOC) = fdoc;
+ SPIBAR32(FDOC) = fdoc;
- return SPIBAR32(SPIBAR_FDOD);
+ return SPIBAR32(FDOD);
}
#ifndef __SIMPLE_DEVICE__
diff --git a/src/southbridge/intel/wildcatpoint/spi.h b/src/southbridge/intel/wildcatpoint/spi.h
index 726b37e..8851f65 100644
--- a/src/southbridge/intel/wildcatpoint/spi.h
+++ b/src/southbridge/intel/wildcatpoint/spi.h
@@ -13,9 +13,9 @@
#define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET)
/* Registers within the SPIBAR */
-#define SPIBAR_SSFC 0x91
-#define SPIBAR_FDOC 0xb0
-#define SPIBAR_FDOD 0xb4
+#define SSFC 0x91
+#define FDOC 0xb0
+#define FDOD 0xb4
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
--
To view, visit https://review.coreboot.org/c/coreboot/+/42626
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d
Gerrit-Change-Number: 42626
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
3
11
Change in coreboot[master]: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
by Arthur Heymans (Code Review) 30 Oct '20
by Arthur Heymans (Code Review) 30 Oct '20
30 Oct '20
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35872 )
Change subject: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
......................................................................
{soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
The last argument for acpi_fill_mcfg is the last PCI bus, not the
total number of busses.
Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/stoneyridge/northbridge.c
M src/southbridge/amd/pi/hudson/lpc.c
3 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35872/1
diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c
index 36135f9..756537b 100644
--- a/src/soc/amd/picasso/northbridge.c
+++ b/src/soc/amd/picasso/northbridge.c
@@ -167,7 +167,7 @@
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
- CONFIG_MMCONF_BUS_NUMBER);
+ CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 044a1b0..2304e73 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -183,7 +183,7 @@
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
- CONFIG_MMCONF_BUS_NUMBER);
+ CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index 02123a1..cf73a8c 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -336,7 +336,7 @@
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
- CONFIG_MMCONF_BUS_NUMBER);
+ CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35872
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Gerrit-Change-Number: 35872
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
5
9
Change in coreboot[master]: [WIP]amdfwtool: Take a config file instead of command line parameters
by Bao Zheng (Code Review) 30 Oct '20
by Bao Zheng (Code Review) 30 Oct '20
30 Oct '20
Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42859
to review the following change.
Change subject: [WIP]amdfwtool: Take a config file instead of command line parameters
......................................................................
[WIP]amdfwtool: Take a config file instead of command line parameters
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M Makefile.inc
M src/soc/amd/picasso/Makefile.inc
A src/soc/amd/picasso/fw.cfg
M util/amdfwtool/Makefile
A util/amdfwtool/Makefile.inc
M util/amdfwtool/amdfwtool.c
A util/amdfwtool/amdfwtool.h
A util/amdfwtool/amdfwtool.sh
A util/amdfwtool/data_parse.c
A util/amdfwtool/sample.txt
10 files changed, 899 insertions(+), 142 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42859/1
diff --git a/Makefile.inc b/Makefile.inc
index bbb6685..0e10136 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -81,7 +81,7 @@
subdirs-y += src/superio
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
subdirs-y += src/cpu src/vendorcode
-subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen
+subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
subdirs-y += util/futility util/marvell util/bincfg util/supermicro
subdirs-y += $(wildcard src/arch/*)
subdirs-y += src/mainboard/$(MAINBOARDDIR)
@@ -566,9 +566,9 @@
cp -a $(top)/util/ifdtool/ifdtool $@
AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
-$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c
- @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
- $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $<
+#$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c
+# @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
+# $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $<
APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
@@ -666,7 +666,7 @@
include util/crossgcc/Makefile.inc
.PHONY: tools
-tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(objutil)/amdfwtool/amdfwtool $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo
###########################################################################
# Common recipes for all stages
@@ -1094,7 +1094,6 @@
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
-
@printf " CBFS $(subst $(obj)/,,$(@))\n"
# The full ROM may be larger than the CBFS part, so create an empty
# file (filled with \377 = 0xff) and copy the CBFS image over it.
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 39269e9..20fb5c2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -378,14 +378,6 @@
rm -f $@
@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
$(AMDFWTOOL) \
- $(OPT_AMD_PUBKEY_FILE) \
- $(OPT_PSPBTLDR_FILE) \
- $(OPT_PSPSCUREOS_FILE) \
- $(OPT_PSP_SEC_DBG_KEY_FILE) \
- $(OPT_SMUFW1_SUB2_FILE) \
- $(OPT_SMUFW2_SUB2_FILE) \
- $(OPT_SMUFW1_SUB1_FILE) \
- $(OPT_SMUFW2_SUB1_FILE) \
$(OPT_PSP_APCB_FILES) \
$(OPT_APOB_ADDR) \
--apob-nv-size $(shell printf "0x%x" \
@@ -398,38 +390,18 @@
$(OPT_PSP_BIOSBIN_DEST) \
$(OPT_PSP_BIOSBIN_SIZE) \
$(OPT_PSP_SOFTFUSE) \
- $(OPT_PSP_PMUI_FILE1) \
- $(OPT_PSP_PMUI_FILE2) \
- $(OPT_PSP_PMUI_FILE3) \
- $(OPT_PSP_PMUI_FILE4) \
- $(OPT_PSP_PMUD_FILE1) \
- $(OPT_PSP_PMUD_FILE2) \
- $(OPT_PSP_PMUD_FILE3) \
- $(OPT_PSP_PMUD_FILE4) \
- $(OPT_MP2CFG_FILE) \
- $(OPT_ABL0_FILE) \
- $(OPT_ABL1_FILE) \
- $(OPT_ABL2_FILE) \
- $(OPT_ABL3_FILE) \
- $(OPT_ABL4_FILE) \
- $(OPT_ABL5_FILE) \
- $(OPT_ABL6_FILE) \
- $(OPT_ABL7_FILE) \
$(OPT_WHITELIST_FILE) \
- $(OPT_SECG1_FILE) \
- $(OPT_SECG2_FILE) \
- $(OPT_MP2FW1_FILE) \
- $(OPT_MP2FW2_FILE) \
- $(OPT_DRIVERS_FILE) \
- $(OPT_PSP_S0I3_FILE) \
- $(OPT_IKEK_FILE) \
$(OPT_SEC_DEBUG_FILE) \
+ --config $(FIRMWARE_LOCATE)/fw.cfg \
--combo-capable \
$(OPT_TOKEN_UNLOCK) \
--flashsize $(CONFIG_ROM_SIZE) \
--location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \
--output $@
+# --config /home/baozheng/x86/coreboot-gerrit/src/soc/amd/picasso/fw.cfg \
+
+
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
rm -f $@
@printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg
new file mode 100644
index 0000000..f5b9d13
--- /dev/null
+++ b/src/soc/amd/picasso/fw.cfg
@@ -0,0 +1,46 @@
+# sample PSP fw config file
+# Move to amd_blob
+# type file
+AMD_PUBKEY_FILE AmdPubKeyRV.bin
+PSPBTLDR_FILE PspBootLoader_prod_RV.sbin
+#PUBSIGNEDKEY_FILE RtmPubSignedRV.key
+PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin
+PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin
+PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin
+PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin
+PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin
+#PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin
+#PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin
+PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin
+PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin
+PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin
+PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin
+PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin
+PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin
+PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin
+PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin
+PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin
+#PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin
+PSP_IKEK_FILE PspIkekRV.bin
+PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin
+PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin
+#PSP_MP2FW1_FILE MP2I2CFWRV2.sbin
+#PSP_MP2FW2_FILE MP2I2CFWPCO.sbin
+#PSP_MP2CFG_FILE MP2FWConfig.sbin
+PSP_DRIVERS_FILE drv_sys_prod_RV.sbin
+#PSP_SOFTFUSE 0x0000000010000001
+#PSP_S0I3_FILE dr_agesa_prod_RV.sbin
+#PSP_APOBNV_BASE
+#PSP_APOBNV_SIZE
+#
+## BDT
+#PSP_APCB0_FILE apcb.bin
+PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin
+PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin
+PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin
+PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin
+PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin
+PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin
+PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin
+#PSP_MP2CFG_FILE MP2FWConfig.sbin
diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile
index e9fd91b..9f7a01b 100644
--- a/util/amdfwtool/Makefile
+++ b/util/amdfwtool/Makefile
@@ -2,15 +2,47 @@
#
# All rights reserved.
#
-# SPDX-License-Identifier: BSD-3-Clause
-
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# * Neither the name of Advanced Micro Devices, Inc. nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
#*****************************************************************************
HOSTCC ?= cc
-amdfwtool_exe : amdfwtool.c
- $(HOSTCC) amdfwtool.c -o amdfwtool
+SRC = amdfwtool.c data_parse.c
+OBJ = $(SRC:%.c=%.o)
+TARGET = amdfwtool
+CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare
-amdfwtool : amdfwtool_exe
+
+$(TARGET): $(OBJ)
+ $(CC) $(OBJ) $(LDFLAGS) -o $@
+
+%.o: %.c $(HEADER)
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+amdfwtool_exe : $(TARGET)
+# $(HOSTCC) amdfwtool.c -o amdfwtool
+#
+#amdfwtool : amdfwtool_exe
clean:
- @rm -f amdfwtool.o amdfwtool amdfwtool.exe
+ rm -f $(TARGET) $(OBJ)
diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc
new file mode 100644
index 0000000..36ff207d
--- /dev/null
+++ b/util/amdfwtool/Makefile.inc
@@ -0,0 +1,52 @@
+#*****************************************************************************
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# * Neither the name of Advanced Micro Devices, Inc. nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#*****************************************************************************
+#HOSTCC ?= cc
+
+amdfwtoolobj = amdfwtool.o data_parse.o
+
+#TARGET = $(objutil)/amdfwtool/amdfwtool
+AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare
+
+
+#$(TARGET): $(OBJ)
+# $(CC) $(OBJ) $(LDFLAGS) -o $@
+
+$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER)
+ printf " AMDFWTOOL\n"
+ $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+#amdfwtool_exe : $(TARGET)
+# $(HOSTCC) amdfwtool.c -o amdfwtool
+#
+#amdfwtool : amdfwtool_exe
+
+#clean:
+# rm -f $(TARGET) $(OBJ)
+$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj))
+ printf " AMDFWTOOL\n"
+ $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index a5e5110..eb0cae8 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -56,6 +56,9 @@
#include <string.h>
#include <stdlib.h>
#include <getopt.h>
+#include <libgen.h>
+
+#include "amdfwtool.h"
#ifndef CONFIG_ROM_SIZE
#define CONFIG_ROM_SIZE 0x400000
@@ -98,13 +101,6 @@
*/
#define PSP_COMBO 0
-#if defined(__GLIBC__)
-typedef unsigned long long int uint64_t;
-typedef unsigned int uint32_t;
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-#endif
-
/*
* Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
* The checksum field of the passed PDU does not need to be reset to zero.
@@ -216,92 +212,11 @@
printf("-R | --sharedmem Location of PSP/FW shared memory\n");
printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n");
printf("-h | --help show this help\n");
+ printf("-C | --config config file\n");
}
-typedef enum _amd_bios_type {
- AMD_BIOS_APCB = 0x60,
- AMD_BIOS_APOB = 0x61,
- AMD_BIOS_BIN = 0x62,
- AMD_BIOS_APOB_NV = 0x63,
- AMD_BIOS_PMUI = 0x64,
- AMD_BIOS_PMUD = 0x65,
- AMD_BIOS_UCODE = 0x66,
- AMD_BIOS_APCB_BK = 0x68,
- AMD_BIOS_MP2_CFG = 0x6a,
- AMD_BIOS_PSP_SHARED_MEM = 0x6b,
- AMD_BIOS_L2_PTR = 0x70,
- AMD_BIOS_INVALID,
-} amd_bios_type;
-#define BDT_LVL1 0x1
-#define BDT_LVL2 0x2
-#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
-typedef struct _amd_bios_entry {
- amd_bios_type type;
- int region_type;
- int reset;
- int copy;
- int ro;
- int zlib;
- int inst;
- int subpr;
- uint64_t src;
- uint64_t dest;
- size_t size;
- char *filename;
- int level;
-} amd_bios_entry;
-
-typedef enum _amd_fw_type {
- AMD_FW_PSP_PUBKEY = 0,
- AMD_FW_PSP_BOOTLOADER = 1,
- AMD_FW_PSP_SMU_FIRMWARE = 8,
- AMD_FW_PSP_RECOVERY = 3,
- AMD_FW_PSP_RTM_PUBKEY = 5,
- AMD_FW_PSP_SECURED_OS = 2,
- AMD_FW_PSP_NVRAM = 4,
- AMD_FW_PSP_SECURED_DEBUG = 9,
- AMD_FW_PSP_TRUSTLETS = 12,
- AMD_FW_PSP_TRUSTLETKEY = 13,
- AMD_FW_PSP_SMU_FIRMWARE2 = 18,
- AMD_PSP_FUSE_CHAIN = 11,
- AMD_FW_PSP_SMUSCS = 95,
- AMD_DEBUG_UNLOCK = 0x13,
- AMD_WRAPPED_IKEK = 0x21,
- AMD_TOKEN_UNLOCK = 0x22,
- AMD_SEC_GASKET = 0x24,
- AMD_MP2_FW = 0x25,
- AMD_DRIVER_ENTRIES = 0x28,
- AMD_S0I3_DRIVER = 0x2d,
- AMD_ABL0 = 0x30,
- AMD_ABL1 = 0x31,
- AMD_ABL2 = 0x32,
- AMD_ABL3 = 0x33,
- AMD_ABL4 = 0x34,
- AMD_ABL5 = 0x35,
- AMD_ABL6 = 0x36,
- AMD_ABL7 = 0x37,
- AMD_FW_PSP_WHITELIST = 0x3a,
- AMD_FW_L2_PTR = 0x40,
- AMD_FW_PSP_VERSTAGE = 0x52,
- AMD_FW_IMC,
- AMD_FW_GEC,
- AMD_FW_XHCI,
- AMD_FW_INVALID,
-} amd_fw_type;
-
-#define PSP_LVL1 0x1
-#define PSP_LVL2 0x2
-#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
-typedef struct _amd_fw_entry {
- amd_fw_type type;
- uint8_t subprog;
- char *filename;
- int level;
- uint64_t other;
-} amd_fw_entry;
-
-static amd_fw_entry amd_psp_fw_table[] = {
+/* static */ amd_fw_entry amd_psp_fw_table[] = {
{ .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH },
{ .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH },
{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH },
@@ -343,14 +258,14 @@
{ .type = AMD_FW_INVALID },
};
-static amd_fw_entry amd_fw_table[] = {
+amd_fw_entry amd_fw_table[] = {
{ .type = AMD_FW_XHCI },
{ .type = AMD_FW_IMC },
{ .type = AMD_FW_GEC },
{ .type = AMD_FW_INVALID },
};
-static amd_bios_entry amd_bios_table[] = {
+amd_bios_entry amd_bios_table[] = {
{ .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
@@ -658,6 +573,28 @@
}
}
+static void dump_psp_firmwares(amd_fw_entry *fw_table)
+{
+ amd_fw_entry *index;
+
+ for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
+ printf("type=%x\n", index->type);
+ if (index->filename)
+ printf (" filename=%s\n", index->filename);
+ }
+}
+
+static void dump_bdt_firmwares(amd_bios_entry *fw_table)
+{
+ amd_bios_entry *index;
+
+ for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) {
+ printf("type=%x\n", index->type);
+ if (index->filename)
+ printf (" filename=%s\n", index->filename);
+ }
+}
+
static void integrate_psp_firmwares(context *ctx,
psp_directory_table *pspdir,
psp_directory_table *pspdir2,
@@ -1039,7 +976,7 @@
fill_dir_header(biosdir, count, cookie);
}
// Unused values: CDE
-static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:";
+static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C";
static struct option long_options[] = {
{"xhci", required_argument, 0, 'x' },
@@ -1087,6 +1024,7 @@
{"apob-nv-base", required_argument, 0, 'F' },
{"apob-nv-size", required_argument, 0, 'H' },
/* other */
+ {"config", required_argument, 0, 'C' },
{"output", required_argument, 0, 'o' },
{"flashsize", required_argument, 0, 'f' },
{"location", required_argument, 0, 'l' },
@@ -1097,7 +1035,7 @@
{NULL, 0, 0, 0 }
};
-static void register_fw_fuse(char *str)
+void register_fw_fuse(char *str)
{
int i;
@@ -1145,6 +1083,40 @@
}
}
+static int register_fw_fuses(int fd, char *dir)
+{
+ struct stat fd_stat;
+ unsigned char *config_file;
+
+// fd = open(, O_RDONLY);
+// if (fd < 0) {
+// printf("Error opening file: %s: %s\n",
+// src_file, strerror(errno));
+// return -1;
+// }
+
+ if (fstat(fd, &fd_stat)) {
+ printf("fstat error 1: %s\n", strerror(errno));
+ close(fd);
+ return -2;
+ }
+
+ //if (fd_stat.st_size > room) {
+ // printf("Error: %s will not fit. Exiting.\n", src_file);
+ // close(fd);
+ // return -3;
+ //}
+
+ config_file = malloc (fd_stat.st_size+1);
+ read(fd, config_file, (size_t)fd_stat.st_size);
+
+ config_file[fd_stat.st_size+1] = '\0';
+
+ process_config(config_file, dir);
+ printf("fuse written=[%s,%d] %x\n", __func__, __LINE__, amd_psp_fw_table[16].other);
+}
+
+
static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[])
{
int i;
@@ -1188,8 +1160,8 @@
psp_directory_table *pspdir;
int comboable = 0;
int fuse_defined = 0;
- int targetfd;
- char *output = NULL;
+ int targetfd, configfd;
+ char *output = NULL, *config = NULL;
context ctx = {
.rom_size = CONFIG_ROM_SIZE,
};
@@ -1427,6 +1399,9 @@
sub = instance = 0;
break;
+ case 'C':
+ config = optarg;
+ break;
case 'h':
usage();
return 0;
@@ -1434,9 +1409,29 @@
break;
}
}
+ #if 1
+ if (!config) {
+ printf("Error: config file is not specified.\n\n");
+ retval = 1;
+ }
- if (!fuse_defined)
- register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
+ configfd = open(config, O_RDONLY);
+
+ if (configfd >=0) {
+ printf("%s opened\n", config);
+ register_fw_fuses(configfd, dirname(config));
+ } else {
+ printf("open failed\n");
+ }
+
+
+ dump_psp_firmwares(amd_psp_fw_table);
+ dump_bdt_firmwares(amd_bios_table);
+ printf("close config file\n");
+ close (configfd);
+#endif
+ //if (!fuse_defined)
+ // register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
if (!output) {
printf("Error: Output value is not specified.\n\n");
@@ -1571,6 +1566,7 @@
amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir);
}
+ /* TODO:Free the filename. */
targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
if (targetfd >= 0) {
write(targetfd, amd_romsig, ctx.current - romsig_offset);
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
new file mode 100644
index 0000000..fda41b2
--- /dev/null
+++ b/util/amdfwtool/amdfwtool.h
@@ -0,0 +1,98 @@
+#ifndef _AMD_FW_TOOL_H_
+#define _AMD_FW_TOOL_H_
+#if defined(__GLIBC__)
+typedef unsigned long long int uint64_t;
+typedef unsigned int uint32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+#endif
+
+
+typedef enum _amd_fw_type {
+ AMD_FW_PSP_PUBKEY = 0,
+ AMD_FW_PSP_BOOTLOADER = 1,
+ AMD_FW_PSP_SMU_FIRMWARE = 8,
+ AMD_FW_PSP_RECOVERY = 3,
+ AMD_FW_PSP_RTM_PUBKEY = 5,
+ AMD_FW_PSP_SECURED_OS = 2,
+ AMD_FW_PSP_NVRAM = 4,
+ AMD_FW_PSP_SECURED_DEBUG = 9,
+ AMD_FW_PSP_TRUSTLETS = 12,
+ AMD_FW_PSP_TRUSTLETKEY = 13,
+ AMD_FW_PSP_SMU_FIRMWARE2 = 18,
+ AMD_PSP_FUSE_CHAIN = 11,
+ AMD_FW_PSP_SMUSCS = 95,
+ AMD_DEBUG_UNLOCK = 0x13,
+ AMD_WRAPPED_IKEK = 0x21,
+ AMD_TOKEN_UNLOCK = 0x22,
+ AMD_SEC_GASKET = 0x24,
+ AMD_MP2_FW = 0x25,
+ AMD_DRIVER_ENTRIES = 0x28,
+ AMD_S0I3_DRIVER = 0x2d,
+ AMD_ABL0 = 0x30,
+ AMD_ABL1 = 0x31,
+ AMD_ABL2 = 0x32,
+ AMD_ABL3 = 0x33,
+ AMD_ABL4 = 0x34,
+ AMD_ABL5 = 0x35,
+ AMD_ABL6 = 0x36,
+ AMD_ABL7 = 0x37,
+ AMD_FW_PSP_WHITELIST = 0x3a,
+ AMD_FW_L2_PTR = 0x40,
+ AMD_FW_PSP_VERSTAGE = 0x52,
+ AMD_FW_IMC,
+ AMD_FW_GEC,
+ AMD_FW_XHCI,
+ AMD_FW_INVALID,
+} amd_fw_type;
+
+typedef enum _amd_bios_type {
+ AMD_BIOS_APCB = 0x60,
+ AMD_BIOS_APOB = 0x61,
+ AMD_BIOS_BIN = 0x62,
+ AMD_BIOS_APOB_NV = 0x63,
+ AMD_BIOS_PMUI = 0x64,
+ AMD_BIOS_PMUD = 0x65,
+ AMD_BIOS_UCODE = 0x66,
+ AMD_BIOS_APCB_BK = 0x68,
+ AMD_BIOS_MP2_CFG = 0x6a,
+ AMD_BIOS_PSP_SHARED_MEM = 0x6b,
+ AMD_BIOS_L2_PTR = 0x70,
+ AMD_BIOS_INVALID,
+} amd_bios_type;
+
+
+#define BDT_LVL1 0x1
+#define BDT_LVL2 0x2
+#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
+typedef struct _amd_bios_entry {
+ amd_bios_type type;
+ char *filename;
+ int subpr;
+ int region_type;
+ int reset;
+ int copy;
+ int ro;
+ int zlib;
+ int inst;
+ uint64_t src;
+ uint64_t dest;
+ size_t size;
+ int level;
+} amd_bios_entry;
+
+
+#define PSP_LVL1 0x1
+#define PSP_LVL2 0x2
+#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
+typedef struct _amd_fw_entry {
+ amd_fw_type type;
+ char *filename;
+ uint8_t subprog;
+ int level;
+ uint64_t other;
+} amd_fw_entry;
+
+void register_fw_fuse(char *str);
+
+#endif
diff --git a/util/amdfwtool/amdfwtool.sh b/util/amdfwtool/amdfwtool.sh
new file mode 100644
index 0000000..50006f8
--- /dev/null
+++ b/util/amdfwtool/amdfwtool.sh
@@ -0,0 +1,60 @@
+#!/bin/sh
+
+# --pubkey ../../3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin \
+# --bootloader /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspBootLoader_prod_RV.sbin \
+# --rtmpubkey /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RtmPubSignedRV.key \
+# --secureos /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//psp_os_combined_prod_RV.sbin \
+# --securedebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RavenSecureDebug_PublicKey.bin \
+
+# --trustlets /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//dr_ftpm_prod_RV.csbin \
+# --subprogram 2 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwarePCO.csbin \
+# --subprogram 2 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2PCO.csbin \
+# --subprogram 1 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwareRV2.csbin \
+# --subprogram 1 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2RV2.csbin \
+
+# --soft-fuse 0x0000000010000001 \
+# --subprogram 0 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Imem.csbin \
+# --subprogram 0 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Imem.csbin \
+# --subprogram 1 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Imem.csbin \
+# --subprogram 1 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Imem.csbin \
+# --subprogram 0 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin \
+# --subprogram 0 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Dmem.csbin \
+# --subprogram 1 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin \
+# --subprogram 1 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin \
+# --mp2-config /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2FWConfig.sbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader0_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader1_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader2_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader3_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader4_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader5_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader6_prod_RV.csbin \
+# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader7_prod_RV.csbin \
+# --subprog 1 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_RV2_FP5_AM4.sbin \
+# --subprog 2 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_PCO_FP5_AM4.sbin \
+# --subprog 1 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWRV2.sbin \
+# --subprog 2 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWPCO.sbin \
+# --drv-entry-pts /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//drv_sys_prod_RV.sbin \
+# --ikek /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspIkekRV.bin \
+# --secdebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//secure_unlock_prod_RV.sbin \
+
+./amdfwtool \
+ --instance 0 --apcb ../../3rdparty/blobs/mainboard/amd/mandolin/apcb.bin \
+ \
+ \
+ \
+ \
+ --apob-base 0x9f00000 \
+ \
+ --apob-nv-size 0x1000 \
+ --bios-bin amd_biospsp.img \
+ --bios-bin-dest 8078000 \
+ --bios-uncomp-size 0x8000 \
+ \
+ \
+ --combo-capable \
+ --token-unlock \
+ --flashsize 0x00800000 \
+ --location 0xff820000 \
+ --config sample.txt \
+ --output amdfw.rom
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
new file mode 100644
index 0000000..03f1a7f
--- /dev/null
+++ b/util/amdfwtool/data_parse.c
@@ -0,0 +1,457 @@
+#include <stdio.h>
+#include <regex.h>
+#include <string.h>
+
+#include "amdfwtool.h"
+
+/* TODO: a empty line does not matched. */
+static const char blank_or_comment_regex[] =
+ /* a blank line */
+ "(^[[:space:]]*$)" "|" /* or ... */
+ /* a line consisting of: optional whitespace followed by */
+ "(^[[:space:]]*"
+ /* a '#' character and optionally, additional characters */
+ "#.*$)";
+static regex_t blank_or_comment_expr;
+
+static const char entries_line_regex[] =
+ /* optional whitespace */
+ "^[[:space:]]*"
+ /* followed by a chunk of nonwhitespace for macro field */
+ "([^[:space:]]+)"
+ /* followed by one or more whitespace characters */
+ "[[:space:]]+"
+ /* followed by a chunk of nonwhitespace for filename field */
+ "([^[:space:]]+)"
+ /* followed by optional whitespace */
+ "[[:space:]]*$";
+static regex_t entries_line_expr;
+
+static const char entries_subprog_line_regex[] =
+ /* optional whitespace */
+ "^[[:space:]]*"
+ /* followed by a chunk of nonwhitespace for macro field */
+ "([^[:space:]]+)"
+ /* followed by one or more whitespace characters */
+ "[[:space:]]+"
+ /* followed by a chunk of nonwhitespace for filename field */
+ "([^[:space:]]+)"
+ /* followed by one or more whitespace characters */
+ "[[:space:]]+"
+ /* followed by a chunk of nonwhitespace for filename field */
+ "([^[:space:]]+)"
+ /* followed by optional whitespace */
+ "[[:space:]]*$";
+static regex_t entries_subprog_line_expr;
+
+void compile_reg_expr(int cflags, const char *expr, regex_t *reg)
+{
+ static const size_t ERROR_BUF_SIZE = 256;
+ char error_msg[ERROR_BUF_SIZE];
+ int result;
+
+ if ((result = regcomp(reg, expr, cflags)) != 0) {
+ regerror(result, reg, error_msg, ERROR_BUF_SIZE);
+ printf("%s\n", error_msg);
+ exit(1);
+ }
+}
+
+extern amd_fw_entry amd_psp_fw_table[];
+extern amd_bios_entry amd_bios_table[];
+void find_register_fw_filename(char *fw_name, char *filename, uint8_t subprog)
+{
+ unsigned int fw_type, fw_invalid, fw, entry_size;
+ void *tableptr;
+ uint8_t /* subprog = 0, */instance = 0;
+
+ printf("fw_name=%s, fn=%s, subprog=%d\n", fw_name, filename, subprog);
+ if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) {
+ fw_type = AMD_FW_PSP_BOOTLOADER;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+// printf("fw_type=%x, size=%x\n", fw_type, entry_size);
+ } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) {
+ fw_type = AMD_FW_PSP_PUBKEY;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+// printf("fw_type=%x, size=%x\n", fw_type, entry_size);
+ } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) {
+ fw_type = AMD_FW_PSP_RTM_PUBKEY;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SMU_FIRMWARE;
+ subprog = 1;
+ instance = 0;
+ fw_invalid = AMD_FW_INVALID;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SMU_FIRMWARE;
+ subprog = 2;
+ instance = 0;
+ fw_invalid = AMD_FW_INVALID;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 1;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 2;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SECURED_DEBUG;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) {
+ fw_type = AMD_ABL0;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) {
+ fw_type = AMD_ABL1;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) {
+ fw_type = AMD_ABL2;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) {
+ fw_type = AMD_ABL3;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) {
+ fw_type = AMD_ABL4;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) {
+ fw_type = AMD_ABL5;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) {
+ fw_type = AMD_ABL6;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) {
+ fw_type = AMD_ABL7;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSPSCUREOS_FILE") == 0) {
+ fw_type = AMD_FW_PSP_SECURED_OS;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) {
+ fw_type = AMD_FW_PSP_TRUSTLETS;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) {
+ fw_type = AMD_DEBUG_UNLOCK;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) {
+ fw_type = AMD_WRAPPED_IKEK;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) {
+ fw_type = AMD_SEC_GASKET;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 1;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) {
+ fw_type = AMD_SEC_GASKET;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 2;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) {
+ fw_type = AMD_MP2_FW;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 1;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) {
+ fw_type = AMD_MP2_FW;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 2;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) {
+ fw_type = AMD_DRIVER_ENTRIES;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) {
+ fw_type = AMD_S0I3_DRIVER;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else if (strcmp(fw_name, "PSP_WHITELIST_FILE") == 0) {
+ fw_type = AMD_FW_PSP_WHITELIST;
+ fw_invalid = AMD_FW_INVALID;
+ subprog = 0;
+ instance = 0;
+ tableptr = (void *)amd_psp_fw_table;
+ entry_size = sizeof (amd_fw_entry);
+ } else {
+ fw_type = AMD_FW_INVALID;
+// return ;
+ /* TODO: Add more */
+ }
+
+// printf("fw_type=%x, size=%x\n", fw_type, entry_size);
+ printf("Search and fill the filename\n");
+ /* Search and fill the filename */
+ while (*(unsigned int *)tableptr != fw_invalid) {
+ if (*(unsigned int *)tableptr == fw_type &&
+ ((amd_bios_entry *)tableptr)->subpr == subprog) {
+ printf("type=%d,", *(unsigned int *)tableptr);
+ printf("found, fn=%s\n", filename);
+ ((amd_fw_entry *)tableptr)->filename = filename;
+ break;
+ } else {
+// printf("not found type=%d\n", *(unsigned int *)tableptr);
+ }
+ tableptr += entry_size;
+ }
+ printf("\n");
+ printf("Search and fill the filename 2\n\n");
+ #if 1
+ if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) {
+ fw_type = AMD_BIOS_PMUI;
+ subprog = 0;
+ instance = 1;
+ } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) {
+ fw_type = AMD_BIOS_PMUI;
+ subprog = 0;
+ instance = 4;
+ } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) {
+ fw_type = AMD_BIOS_PMUI;
+ subprog = 1;
+ instance = 1;
+ } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) {
+ fw_type = AMD_BIOS_PMUI;
+ subprog = 1;
+ instance = 4;
+ } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) {
+ fw_type = AMD_BIOS_PMUD;
+ subprog = 0;
+ instance = 1;
+ } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) {
+ fw_type = AMD_BIOS_PMUD;
+ subprog = 0;
+ instance = 4;
+ } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) {
+ fw_type = AMD_BIOS_PMUD;
+ subprog = 1;
+ instance = 1;
+ } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) {
+ fw_type = AMD_BIOS_PMUD;
+ subprog = 1;
+ instance = 4;
+ } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) {
+ fw_type = AMD_BIOS_MP2_CFG;
+ subprog = 0;
+ instance = 0;
+ } else {
+ fw_type = AMD_BIOS_INVALID;
+ }
+ tableptr = (void *)amd_bios_table;
+ if (fw_type != AMD_BIOS_INVALID) {
+ while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) {
+ //printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst);
+ if (*(unsigned int *)tableptr == fw_type &&
+ ((amd_bios_entry *)tableptr)->subpr == subprog &&
+ ((amd_bios_entry *)tableptr)->inst == instance) {
+ ((amd_bios_entry *)tableptr)->filename = filename;
+ //((amd_bios_entry *)tableptr)->subpr = subprog;
+ //((amd_bios_entry *)tableptr)->inst = instance;
+ printf("type=%x,", *(unsigned int *)tableptr);
+ printf("found, fn=%s\n", filename);
+ break;
+ }
+ tableptr += sizeof (amd_bios_entry);
+ }
+ }
+
+ printf("Search and fill the filename 3\n\n");
+ if (strcmp(fw_name, "PSP_SOFTFUSE") == 0) {
+ fw_type = AMD_PSP_FUSE_CHAIN;
+ } else {
+ fw_type = AMD_BIOS_INVALID;
+ }
+ /* char *filename */
+ printf("Search and fill the filename 3.1\n\n");
+ tableptr = (void *)amd_psp_fw_table;
+ if (fw_type != AMD_BIOS_INVALID) {
+ while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) {
+ printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst);
+ if (*(unsigned int *)tableptr == fw_type) {
+ //((amd_bios_entry *)tableptr)->filename = filename;
+ //((amd_bios_entry *)tableptr)->subpr = subprog;
+ ((amd_fw_entry *)tableptr)->other = strtoull(filename, NULL, 16);
+ printf("type=%x,", *(unsigned int *)tableptr);
+ printf("found, fuse=%llx\n", ((amd_fw_entry *)tableptr)->other);
+ break;
+ }
+ tableptr += sizeof (amd_fw_entry);
+ }
+ }
+ printf("fuse written=[] %x\n", amd_psp_fw_table[16].other);
+
+ printf("Search and fill the filename 3.9\n\n");
+
+#endif
+
+}
+
+unsigned int read_line(char **config, char **oneline)
+{
+ char *ptr = *config;
+ char *line_start;
+ int num;
+
+// printf("read_line %c\n", **config);
+ if (*ptr == NULL) return -1;
+
+ line_start = ptr;
+ while (*ptr != '\n' && *ptr != NULL) {
+ ptr ++;
+ }
+
+ num = ptr - line_start;
+ *oneline = malloc(num+1);
+
+ memcpy (*oneline, line_start, num);
+ *(*oneline + num) = '\0';
+ ptr ++; /* skip enter. */
+ //*oneline = ptr;
+// printf("readline = %s\n", *oneline);
+ *config = ptr;
+ return 0;
+}
+#define N_MATCHES 4
+void process_config(char *config, char *dir)
+{
+// char line [ /* LINE_BUF_SIZE */128];
+ char *oneline, *current, *path_filename;
+ regmatch_t match[N_MATCHES];
+ uint8_t subprog = 0;
+
+ compile_reg_expr(REG_EXTENDED | REG_NEWLINE, blank_or_comment_regex, &blank_or_comment_expr);
+ compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_line_regex, &entries_line_expr);
+ compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_subprog_line_regex, &entries_subprog_line_expr);
+
+ /* TODO: temp */
+ //strcpy (line, "PSPBTLDR_FILE PspBootLoader_prod_RV.sbin\n\0");
+// strcpy (line, "AMD_PUBKEY_FILE AmdPubKeyRV.bin\n\0");
+
+ /* Get a line */
+ current = config;
+ while (read_line(¤t, &oneline) != -1) {
+ /* get line */
+ /* blank comment */
+// printf("%d\n", __LINE__);
+ if (!regexec(&blank_or_comment_expr, oneline, 0, NULL, 0)){
+ printf("skip comment and blank\n");
+ continue;
+ }
+
+// printf("%d\n", __LINE__);
+ if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) {
+ printf("matched entry\n");
+ printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo);
+ printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so);
+ oneline[match[1].rm_eo] = '\0';
+ oneline[match[2].rm_eo] = '\0';
+ } else if (regexec(&entries_subprog_line_expr, oneline, 4, match, 0) == 0) {
+ printf("matched subprog entry\n");
+ printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo, match[3].rm_eo);
+ printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so, match[3].rm_so);
+ oneline[match[1].rm_eo] = '\0';
+ oneline[match[2].rm_eo] = '\0';
+ oneline[match[3].rm_eo] = '\0';
+ subprog = oneline[match[3].rm_so] - '0';
+ } else {
+ printf("no match\n");
+ continue;
+ }
+// printf("%d\n", __LINE__);
+// printf("%d\n", __LINE__);
+
+// printf("%s, %s\n", &(oneline[match[1].rm_so]), &(oneline[match[2].rm_so]));
+ path_filename = malloc(256);
+ strcpy(path_filename, dir);
+ strcat(path_filename, "/");
+ strcat(path_filename, &(oneline[match[2].rm_so]));
+ find_register_fw_filename(&(oneline[match[1].rm_so]), path_filename, subprog);
+
+ }
+
+ printf("fuse written=[] %x\n", amd_psp_fw_table[16].other);
+
+}
diff --git a/util/amdfwtool/sample.txt b/util/amdfwtool/sample.txt
new file mode 100644
index 0000000..8c3edcc
--- /dev/null
+++ b/util/amdfwtool/sample.txt
@@ -0,0 +1,45 @@
+# sample
+# PSP
+# type file subprog
+AMD_PUBKEY_FILE AmdPubKeyRV.bin
+PSPBTLDR_FILE PspBootLoader_prod_RV.sbin
+PUBSIGNEDKEY_FILE RtmPubSignedRV.key
+PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin
+PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin
+PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin
+PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin
+PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin
+PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin
+PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin
+PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin
+PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin
+PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin
+PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin
+PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin
+PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin
+PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin
+PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin
+PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin
+PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin
+PSP_IKEK_FILE PspIkekRV.bin
+PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin
+PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin
+PSP_MP2FW1_FILE MP2I2CFWRV2.sbin
+PSP_MP2FW2_FILE MP2I2CFWPCO.sbin
+PSP_MP2CFG_FILE MP2FWConfig.sbin
+PSP_DRIVERS_FILE drv_sys_prod_RV.sbin
+PSP_SOFTFUSE 0x0000000010000001
+PSP_S0I3_FILE dr_agesa_prod_RV.sbin
+#PSP_APOBNV_BASE
+#PSP_APOBNV_SIZE
+#
+## BDT
+#PSP_APCB0_FILE apcb.bin
+PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin
+PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin
+PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin
+PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin
+PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin
+PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin
+PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin
--
To view, visit https://review.coreboot.org/c/coreboot/+/42859
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Gerrit-Change-Number: 42859
Gerrit-PatchSet: 1
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Zheng Bao
Gerrit-MessageType: newchange
6
158
Change in coreboot[master]: cbfs: Hook up to new CBFS implmentation
by Julius Werner (Code Review) 30 Oct '20
by Julius Werner (Code Review) 30 Oct '20
30 Oct '20
Hello Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38422
to review the following change.
Change subject: cbfs: Hook up to new CBFS implmentation
......................................................................
cbfs: Hook up to new CBFS implmentation
This patch hooks coreboot up to the new commonlib/bsd CBFS
implementation. This is intended as the "minimum viable patch" that
makes the new implementation useable with the smallest amount of changes
-- that is why some of this may look a bit roundabout (returning the
whole metadata for a file but then just using that to fill out the rdevs
of the existing struct cbfsf). Future changes will migrate the higher
level CBFS APIs one-by-one to use the new implementation directly
(rather than translated into the results of the old one), at which point
this will become more efficient.
Change-Id: I4d112d1239475920de2d872dac179c245275038d
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/commonlib/Makefile.inc
A src/include/cbfs_glue.h
M src/lib/cbfs.c
3 files changed, 63 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38422/1
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index 5bd6cf9..b2225cb 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -30,6 +30,13 @@
smm-y += cbfs.c
postcar-y += cbfs.c
+bootblock-y += bsd/cbfs_private.c
+verstage-y += bsd/cbfs_private.c
+romstage-y += bsd/cbfs_private.c
+postcar-y += bsd/cbfs_private.c
+ramstage-y += bsd/cbfs_private.c
+smm-y += bsd/cbfs_private.c
+
decompressor-y += bsd/lz4_wrapper.c
bootblock-y += bsd/lz4_wrapper.c
verstage-y += bsd/lz4_wrapper.c
diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h
new file mode 100644
index 0000000..10f4187
--- /dev/null
+++ b/src/include/cbfs_glue.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _CBFS_GLUE_H_
+#define _CBFS_GLUE_H_
+
+#include <commonlib/region.h>
+#include <console/console.h>
+
+#define ENABLE_HASHING 0
+
+#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__)
+#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__)
+#if CONFIG(DEBUG_CBFS)
+#define DEBUG(...) printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__)
+#else
+#define DEBUG(...)
+#endif
+
+typedef const struct region_device *cbfs_dev_t;
+
+static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size)
+{
+ return rdev_readat(dev, buffer, offset, size);
+}
+
+static inline size_t cbfs_dev_size(cbfs_dev_t dev)
+{
+ return region_device_sz(dev);
+}
+
+#endif /* _CBFS_GLUE_H_ */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index c712f76..d6fb99c 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -20,6 +20,7 @@
#include <stdlib.h>
#include <boot_device.h>
#include <cbfs.h>
+#include <commonlib/bsd/cbfs_private.h>
#include <commonlib/bsd/compression.h>
#include <endian.h>
#include <lib.h>
@@ -29,14 +30,6 @@
#include <security/vboot/vboot_crtm.h>
#include <security/vboot/vboot_common.h>
-#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x)
-#define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
-#if CONFIG(DEBUG_CBFS)
-#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
-#else
-#define DEBUG(x...)
-#endif
-
int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
{
struct region_device rdev;
@@ -44,28 +37,35 @@
if (cbfs_boot_region_device(&rdev))
return -1;
- int ret = cbfs_locate(fh, &rdev, name, type);
+ union cbfs_mdata mdata;
+ size_t data_offset;
+ cb_err_t err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL);
- if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) {
+ if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) {
+ printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n",
+ name);
+ if (fmap_locate_area_as_rdev("COREBOOT", &rdev))
+ return -1;
+ err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL);
+ }
+ if (err)
+ return -1;
- /*
- * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the
- * active RW region, the RO (COREBOOT) region will be used to locate the file.
- *
- * This functionality makes it possible to avoid duplicate files in the RO
- * and RW partitions while maintaining updateability.
- *
- * Files can be added to the RO_REGION_ONLY config option to use this feature.
- */
- printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name);
- ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type);
+ size_t msize = be32toh(mdata.h.offset);
+ if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) ||
+ rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len)))
+ return -1;
+ if (type) {
+ if (!*type)
+ *type = be32toh(mdata.h.type);
+ else if (*type != be32toh(mdata.h.type))
+ return -1;
}
- if (!ret)
- if (vboot_measure_cbfs_hook(fh, name))
- return -1;
+ if (vboot_measure_cbfs_hook(fh, name))
+ return -1;
- return ret;
+ return 0;
}
void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
--
To view, visit https://review.coreboot.org/c/coreboot/+/38422
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4d112d1239475920de2d872dac179c245275038d
Gerrit-Change-Number: 38422
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
5
19
Change in coreboot[master]: commonlib/bsd: Add new CBFS core implementation
by Julius Werner (Code Review) 30 Oct '20
by Julius Werner (Code Review) 30 Oct '20
30 Oct '20
Hello Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38421
to review the following change.
Change subject: commonlib/bsd: Add new CBFS core implementation
......................................................................
commonlib/bsd: Add new CBFS core implementation
This patch adds a new CBFS implementation that is intended to replace
the existing commonlib/cbfs.c. The new implementation is designed to
meet a bunch of current and future goals that in aggregate make it
easier to start from scratch than to adapt the exisiting implementation:
1. Be BSD-licensed so it can evetually be shared with libpayload.
2. Allow generating/verifying a master hash for future CBFS per-file
verification (see [1][2]).
3. Be very careful about reading (not mmaping) all data only once, to be
suitable for eventual TOCTOU-safe verification.
4. Make it possibly to efficiently implement all current and future
firmware use cases (both with and without verification).
The main primitive is the cbfs_walk() function which will traverse a
CBFS and call a callback for every file. cbfs_lookup() uses this to
implement the most common use case of finding a file so that it can be
read. A host application using this code (e.g. coreboot, libpayload,
cbfstool) will need to provide a <cbfs_glue.h> header to provide the
glue to access the respective CBFS storage backend implementation.
This patch merely adds the code, the next patch will integrate it into
coreboot.
[1]: https://www.youtube.com/watch?v=Hs_EhewBgtM
[2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_i…
Change-Id: Ica64c1751fa37686814c0247460c399261d5814c
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M MAINTAINERS
A src/commonlib/bsd/cbfs_private.c
M src/commonlib/bsd/include/commonlib/bsd/cb_err.h
A src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
5 files changed, 284 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38421/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 77769c0..b5cad10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -489,8 +489,13 @@
F: src/device/oprom/
CBFS
-F: src/include/cbfs.h
-F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
+M: Julius Werner <jwerner(a)chromium.org>
+F: src/include/cbfs*
+F: src/commonlib/bsd/include/commonlib/bsd/cbfs*
+F: src/commonlib/bsd/cbfs*
+F: src/lib/cbfs.c
+
+CBFSTOOL
F: util/cbfstool/
CBMEM
diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c
new file mode 100644
index 0000000..4dd14cb
--- /dev/null
+++ b/src/commonlib/bsd/cbfs_private.c
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
+
+#include <commonlib/bsd/cbfs_private.h>
+#include <assert.h>
+
+static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer)
+{
+ DEBUG("Looking for next file @%#zx...\n", *offset);
+ *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT);
+ while (*offset + sizeof(*buffer) < cbfs_dev_size(dev)) {
+ if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer))
+ return CB_CBFS_IO;
+
+ if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0)
+ return CB_SUCCESS;
+
+ *offset += CBFS_ALIGNMENT;
+ }
+
+ DEBUG("End of CBFS reached\n");
+ return CB_CBFS_NOT_FOUND;
+}
+
+cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
+ union cbfs_mdata *mdata, bool do_hash,
+ void *arg),
+ void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags flags)
+{
+ bool do_hash = ENABLE_HASHING && master_hash;
+ struct vb2_digest_context dc;
+ vb2_error_t vbrv;
+
+ assert(ENABLE_HASHING || (!master_hash && !(flags & CBFS_WALK_WRITEBACK_HASH)));
+ if (do_hash && (vbrv = vb2_digest_init(&dc, master_hash->algo))) {
+ ERROR("Master hash algo %d digest init error: %#x\n", master_hash->algo, vbrv);
+ return CB_ERR_ARG;
+ }
+
+ size_t offset = 0;
+ cb_err_t ret_header;
+ cb_err_t ret_walker = CB_CBFS_NOT_FOUND;
+ union cbfs_mdata mdata;
+ while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) {
+ const uint32_t attr_offset = be32toh(mdata.h.attributes_offset);
+ const uint32_t data_offset = be32toh(mdata.h.offset);
+ const uint32_t data_length = be32toh(mdata.h.len);
+ const uint32_t type = be32toh(mdata.h.type);
+ const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2);
+
+ DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n",
+ offset, be32toh(mdata.h.type), attr_offset, data_offset, data_length);
+ if (data_offset > sizeof(mdata)) {
+ ERROR("File metadata @%#zx too large\n", offset);
+ goto next_file;
+ }
+ if (offset + data_offset >= cbfs_dev_size(dev)) {
+ ERROR("Device ends in middle of metadata @%#zx\n", offset);
+ goto next_file;
+ }
+
+ if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY))
+ goto next_file;
+
+ /* When hashing we need to read everything. Otherwise skip the attributes.
+ attr_offset may be 0, which means there are no attributes. */
+ ssize_t todo;
+ if (do_hash || attr_offset == 0)
+ todo = data_offset - sizeof(mdata.h);
+ else
+ todo = attr_offset - sizeof(mdata.h);
+ if (todo <= 0 || data_offset < attr_offset) {
+ ERROR("Corrupt file header @%#zx\n", offset);
+ goto next_file;
+ }
+
+ /* Read the rest of the metadata (filename, and possibly attributes). */
+ if (cbfs_dev_read(dev, (uint8_t *)&mdata + sizeof(mdata.h),
+ offset + sizeof(mdata.h), todo) != todo)
+ return CB_CBFS_IO;
+ DEBUG("File name: '%s'\n", mdata.filename);
+
+ if (do_hash && !empty && vb2_digest_extend(&dc, (void *)&mdata, data_offset))
+ return CB_ERR;
+
+ if (ret_walker == CB_CBFS_NOT_FOUND)
+ ret_walker = walker(dev, offset, &mdata, do_hash, arg);
+
+ /* Return IO errors immediately. For others, finish the hash first if needed. */
+ if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash))
+ return ret_walker;
+
+next_file:
+ offset += data_offset + data_length;
+ }
+
+ if (ret_header != CB_CBFS_NOT_FOUND)
+ return ret_header;
+
+ if (do_hash) {
+ uint8_t real_hash[VB2_MAX_DIGEST_SIZE];
+ size_t hash_size = vb2_digest_size(master_hash->algo);
+ if (vb2_digest_finalize(&dc, real_hash, sizeof(real_hash)))
+ return CB_ERR;
+ if (flags & CBFS_WALK_WRITEBACK_HASH)
+ memcpy(master_hash->bytes.raw, real_hash, hash_size);
+ else if (memcmp(master_hash->bytes.raw, real_hash, hash_size) != 0)
+ return CB_CBFS_HASH;
+ }
+
+ return ret_walker;
+}
+
+cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src,
+ cbfs_dev_t dev, size_t offset, bool do_hash)
+{
+ const size_t attr_offset = be32toh(src->h.attributes_offset);
+
+ /* In the hashing case or when there are no attributes, we already have everything. */
+ if (do_hash || attr_offset == 0) {
+ memcpy(dst, src, be32toh(src->h.offset));
+ return CB_SUCCESS;
+ }
+
+ /* Otherwise we'll need to copy what we have and read in the rest. */
+ const size_t todo = be32toh(src->h.offset) - attr_offset;
+ memcpy(dst, src, attr_offset);
+ void *dst_attrs = (uint8_t *)dst + attr_offset;
+ if (cbfs_dev_read(dev, dst_attrs, offset + attr_offset, todo) != todo)
+ return CB_CBFS_IO;
+ return CB_SUCCESS;
+}
+
+uint32_t cbfs_filename_size(struct cbfs_file *h)
+{
+ uint32_t end_offset = be32toh(h->attributes_offset);
+ if (end_offset == 0)
+ end_offset = be32toh(h->offset);
+ return end_offset - sizeof(struct cbfs_file);
+}
+
+struct cbfs_lookup_args {
+ union cbfs_mdata *mdata_out;
+ const char *name;
+ size_t namesize;
+ size_t *data_offset_out;
+};
+
+static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, union cbfs_mdata *mdata,
+ bool do_hash, void *arg)
+{
+ struct cbfs_lookup_args *args = arg;
+ if (args->namesize > cbfs_filename_size(&mdata->h) ||
+ memcmp(args->name, mdata->filename, args->namesize) != 0)
+ return CB_CBFS_NOT_FOUND;
+
+ LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len));
+ if (cbfs_copy_fill_metadata(args->mdata_out, mdata, dev, offset, do_hash) != CB_SUCCESS)
+ return CB_CBFS_IO;
+
+ *args->data_offset_out = offset + be32toh(mdata->h.offset);
+ return CB_SUCCESS;
+}
+
+cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
+ size_t *data_offset_out, struct vb2_hash *master_hash)
+{
+ struct cbfs_lookup_args args = {
+ .mdata_out = mdata_out,
+ .name = name,
+ .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */
+ .data_offset_out = data_offset_out,
+ };
+ return cbfs_walk(dev, lookup_walker, &args, master_hash, 0);
+}
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
index ab419a7..ab422e1 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
@@ -34,6 +34,11 @@
CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave
device response, try again? */
CB_I2C_TIMEOUT = -303, /**< Transmission timed out */
+
+ /* CBFS errors */
+ CB_CBFS_IO = -400, /**< Underlying I/O error */
+ CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */
+ CB_CBFS_HASH = -402, /**< Master hash validation failed */
};
/* Don't typedef the enum directly, so the size is unambiguous for serialization. */
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
new file mode 100644
index 0000000..b4fc1c7
--- /dev/null
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
+
+#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_
+#define _COMMONLIB_BSD_CBFS_PRIVATE_H_
+
+#include <commonlib/bsd/cb_err.h>
+#include <commonlib/bsd/cbfs_serialized.h>
+#include <endian.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <vb2_sha.h>
+
+/*
+ * This file needs to be provided by the host application using this CBFS library. It must
+ * define the following type, macros and functions:
+ *
+ * cbfs_dev_t An opaque type representing a CBFS storage backend.
+ * ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise.
+ * ERROR(...) printf-style macro to print errors.
+ * LOG(...) printf-style macro to print normal-operation log messages.
+ * DEBUG(...) printf-style macro to print detailed debug output.
+ *
+ * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size);
+ * Read |size| bytes starting at |offset| from |dev| into |buffer|.
+ * Returns amount of bytes read on success and < 0 on error.
+ *
+ * size_t cbfs_dev_size(cbfs_dev_t dev);
+ * Return the total size in bytes of the CBFS storage (actual CBFS area).
+ */
+#include <cbfs_glue.h>
+
+/* Helper structure to allocate space for a blob of metadata on the stack. */
+#define CBFS_METADATA_MAX_SIZE 256
+union cbfs_mdata {
+ struct {
+ struct cbfs_file h;
+ char filename[];
+ };
+ uint8_t raw[CBFS_METADATA_MAX_SIZE];
+};
+
+/* Flags that modify behavior of cbfs_walk(). */
+enum cbfs_walk_flags {
+ /* Write the calculated hash back out to |master_hash->hash|, rather than comparing it.
+ |master_hash->algo| must still have been initialized by the caller. */
+ CBFS_WALK_WRITEBACK_HASH = (1 << 0),
+ /* Call |walker| for empty file entries. Otherwise, empty entries will be skipped.
+ Either way, empty entries are never included in master_hash calculation. */
+ CBFS_WALK_INCLUDE_EMPTY = (1 << 1),
+};
+
+/*
+ * Traverse a CBFS and call a |walker| callback function for every file. Can additionally
+ * calculate a master hash over the metadata of all files in the CBFS. If |master_hash| is NULL,
+ * hashing is disabled.
+ *
+ * |arg| and |dev| will be passed through to |walker| unmodified. |do_hash| is true iff
+ * hashing is enabled (master_hash != NULL). |offset| is the total offset in |dev| at which the
+ * current file metadata starts. |mdata| is a temporary buffer (only valid for the duration of
+ * this call to |walker|) containing already read metadata from the current file: if |do_hash|
+ * is true, all metadata in |mdata| (header, filename and attributes) will be valid, otherwise
+ * only the header and the filename (not attributes) will be valid. |walker| should call into
+ * cbfs_copy_fill_medadata() to copy the metadata of a file to a persistent buffer and
+ * automatically load remaining attributes from |dev| as needed based on |do_hash|.
+ *
+ * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further
+ * files. Any other return code will be used as the final return code for cbfs_walk(). It will
+ * return immediately unless it needs to calculate a hash in which case it will still traverse
+ * the remaining CBFS (but not call |walker| anymore).
+ */
+cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
+ union cbfs_mdata *mdata, bool do_hash,
+ void *arg),
+ void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags);
+
+
+/*
+ * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata
+ * of a file into a permanent buffer. Will copy the metadata from |src| into |dst| and load
+ * additional attributes from |dev| to copy behind that if |do_hash| is false. (|offset| is the
+ * offset of the whole file metadata, not just of the attributes.)
+ */
+cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src,
+ cbfs_dev_t dev, size_t offset, bool do_hash);
+
+/* Helper function to determine the size of the filename part in a CBFS header. The actual
+ filename is NUL-terminated and due to alignment likely a bit shorter than this. */
+uint32_t cbfs_filename_size(struct cbfs_file *h);
+
+/* Find a file named |name| in the CBFS on |dev| and copy its metadata (including attributes)
+ * into |mdata_out|. Pass out offset to the file data and verify |master_hash| (if provided). */
+cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
+ size_t *data_offset_out, struct vb2_hash *master_hash);
+
+#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
index d2fc626..556c8e4 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
@@ -4,6 +4,7 @@
#define _CBFS_SERIALIZED_H_
#include <stdint.h>
+#include <vb2_sha.h>
/** These are standard values for the known compression
algorithms that coreboot knows about for stages and
@@ -123,12 +124,11 @@
uint32_t decompressed_size;
} __packed;
+/* Actual size in CBFS may be larger/smaller than struct size! */
struct cbfs_file_attr_hash {
uint32_t tag;
uint32_t len;
- uint32_t hash_type;
- /* hash_data is len - sizeof(struct) bytes */
- uint8_t hash_data[];
+ struct vb2_hash hash;
} __packed;
struct cbfs_file_attr_position {
--
To view, visit https://review.coreboot.org/c/coreboot/+/38421
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica64c1751fa37686814c0247460c399261d5814c
Gerrit-Change-Number: 38421
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-MessageType: newchange
7
66
Change in coreboot[master]: temporarily silent GCC on none reliable macro
by HAOUAS Elyes (Code Review) 30 Oct '20
by HAOUAS Elyes (Code Review) 30 Oct '20
30 Oct '20
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42448 )
Change subject: temporarily silent GCC on none reliable macro
......................................................................
temporarily silent GCC on none reliable macro
GCC-10 highlighted a none reliable MCHBARx_AND_OR macro:
x4x:
src/northbridge/intel/x4x/x4x.h:79:16: error: overflow in conversion from 'int' to 'u8' {aka 'volatile unsigned char'} changes value from '(int)*(volatile u8 *)((unsigned int)((int)i * 1024) + 4275126888) & -256 | 74' to '74' [-Werror=overflow]
79 | (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
| ^
src/northbridge/intel/x4x/raminit_ddr23.c:627:3: note: in expansion of macro 'MCHBAR8_AND_OR'
627 | MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a);
| ^~~~~~~~~~~~~~
src/northbridge/intel/x4x/raminit_ddr23.c: In function 'prog_rcomp':
src/northbridge/intel/x4x/x4x.h:83:17: error: overflow in conversion from 'int' to 'u16' {aka 'volatile short unsigned int'} changes value from '(int)*(volatile u16 *)((unsigned int)((int)i * 1024) + 4275127072) & -65536 | 26214' to '26214' [-Werror=overflow]
83 | (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
| ^
and for pineview:
src/northbridge/intel/pineview/raminit.c: In function 'sdram_timings':
src/northbridge/intel/pineview/pineview.h:98:52: error: overflow in conversion from 'int' to 'u8' {aka 'volatile unsigned char'} changes value from '(int)*4275126567 & -256 | 64' to '64' [-Werror=overflow]
98 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
| ^
src/northbridge/intel/pineview/raminit.c:793:2: note: in expansion of macro 'MCHBAR8_AND_OR'
793 | MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40);
| ^~~~~~~~~~~~~~
Also initialize 'reply.command' to avoid this error:
src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma':
src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized]
1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7)))
| ~~~~~^~~~~~~~
cc1: all warnings being treated as errors
Change-Id: I07c1b3bd00de27c115994233086d32497b4c0925
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M Makefile.inc
M src/northbridge/intel/ironlake/raminit.c
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42448/1
diff --git a/Makefile.inc b/Makefile.inc
index 86335d9..4e515c4 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -412,6 +412,12 @@
CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
+
+# Disable 'overflow' waring for not reliable MCHBARx_AND_OR macro
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X)$(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE)$(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)
+CFLAGS_common += -Wno-overflow
+endif
+
ifeq ($(CONFIG_COMPILER_GCC),y)
# Don't add these GCC specific flags when running scan-build
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index e85163f..12162ff 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1775,7 +1775,7 @@
{
struct uma_reply {
u8 group_id;
- u8 command;
+ u8 command = 0;
u8 reserved;
u8 result;
u8 field2;
--
To view, visit https://review.coreboot.org/c/coreboot/+/42448
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I07c1b3bd00de27c115994233086d32497b4c0925
Gerrit-Change-Number: 42448
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-MessageType: newchange
3
20
Change in coreboot[master]: broadwell: update processor power limits configuration
by Sumeet R Pawnikar (Code Review) 25 Oct '20
by Sumeet R Pawnikar (Code Review) 25 Oct '20
25 Oct '20
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41234 )
Change subject: broadwell: update processor power limits configuration
......................................................................
broadwell: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Broadwell SoC based platforms.
BRANCH=None
BUG=None
TEST=Build for broadwell based platform
Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.h
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/include/soc/cpu.h
M src/soc/intel/broadwell/include/soc/msr.h
A src/soc/intel/broadwell/include/soc/soc_chip.h
M src/soc/intel/broadwell/systemagent.c
8 files changed, 33 insertions(+), 156 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41234/1
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 20219d3..67f7563 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -15,6 +15,7 @@
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT
+ select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
@@ -34,10 +35,12 @@
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CPU
+ select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select HAVE_SPI_CONSOLE_SUPPORT
- select CPU_INTEL_COMMON
select INTEL_GMA_ACPI
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 8afdba1..e44a1a1 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -25,6 +25,7 @@
#include <soc/pm.h>
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
+#include <intelblocks/cpulib.h>
/*
* List of supported C-states in this processor. Only the ULT parts support C8,
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 7351d70..c8df32d 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -5,6 +5,7 @@
#define _SOC_INTEL_BROADWELL_CHIP_H_
#include <drivers/intel/gma/i915.h>
+#include <intelblocks/cfg.h>
#include <stdint.h>
struct soc_intel_broadwell_config {
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 35df1b5..f5ec878 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -17,6 +17,7 @@
#include <cpu/x86/name.h>
#include <cpu/x86/smm.h>
#include <delay.h>
+#include <intelblocks/cpulib.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -26,64 +27,6 @@
#include <soc/intel/broadwell/chip.h>
#include <cpu/intel/common/common.h>
-/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
-static const u8 power_limit_time_sec_to_msr[] = {
- [0] = 0x00,
- [1] = 0x0a,
- [2] = 0x0b,
- [3] = 0x4b,
- [4] = 0x0c,
- [5] = 0x2c,
- [6] = 0x4c,
- [7] = 0x6c,
- [8] = 0x0d,
- [10] = 0x2d,
- [12] = 0x4d,
- [14] = 0x6d,
- [16] = 0x0e,
- [20] = 0x2e,
- [24] = 0x4e,
- [28] = 0x6e,
- [32] = 0x0f,
- [40] = 0x2f,
- [48] = 0x4f,
- [56] = 0x6f,
- [64] = 0x10,
- [80] = 0x30,
- [96] = 0x50,
- [112] = 0x70,
- [128] = 0x11,
-};
-
-/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
-static const u8 power_limit_time_msr_to_sec[] = {
- [0x00] = 0,
- [0x0a] = 1,
- [0x0b] = 2,
- [0x4b] = 3,
- [0x0c] = 4,
- [0x2c] = 5,
- [0x4c] = 6,
- [0x6c] = 7,
- [0x0d] = 8,
- [0x2d] = 10,
- [0x4d] = 12,
- [0x6d] = 14,
- [0x0e] = 16,
- [0x2e] = 20,
- [0x4e] = 24,
- [0x6e] = 28,
- [0x0f] = 32,
- [0x2f] = 40,
- [0x4f] = 48,
- [0x6f] = 56,
- [0x10] = 64,
- [0x30] = 80,
- [0x50] = 96,
- [0x70] = 112,
- [0x11] = 128,
-};
-
/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
* when a core is woken up. */
@@ -289,90 +232,6 @@
RCBA32(PMSYNC_CONFIG2) = pmsync2;
}
-int cpu_config_tdp_levels(void)
-{
- msr_t platform_info;
-
- /* Bits 34:33 indicate how many levels supported */
- platform_info = rdmsr(MSR_PLATFORM_INFO);
- return (platform_info.hi >> 1) & 3;
-}
-
-/*
- * Configure processor power limits if possible
- * This must be done AFTER set of BIOS_RESET_CPL
- */
-void set_power_limits(u8 power_limit_1_time)
-{
- msr_t msr = rdmsr(MSR_PLATFORM_INFO);
- msr_t limit;
- unsigned int power_unit;
- unsigned int tdp, min_power, max_power, max_time;
- u8 power_limit_1_val;
-
- if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
- power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
-
- if (!(msr.lo & PLATFORM_INFO_SET_TDP))
- return;
-
- /* Get units */
- msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
- power_unit = 2 << ((msr.lo & 0xf) - 1);
-
- /* Get power defaults for this SKU */
- msr = rdmsr(MSR_PKG_POWER_SKU);
- tdp = msr.lo & 0x7fff;
- min_power = (msr.lo >> 16) & 0x7fff;
- max_power = msr.hi & 0x7fff;
- max_time = (msr.hi >> 16) & 0x7f;
-
- printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
-
- if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
- power_limit_1_time = power_limit_time_msr_to_sec[max_time];
-
- if (min_power > 0 && tdp < min_power)
- tdp = min_power;
-
- if (max_power > 0 && tdp > max_power)
- tdp = max_power;
-
- power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
-
- /* Set long term power limit to TDP */
- limit.lo = 0;
- limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
- limit.lo |= PKG_POWER_LIMIT_EN;
- limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
- PKG_POWER_LIMIT_TIME_SHIFT;
-
- /* Set short term power limit to 1.25 * TDP */
- limit.hi = 0;
- limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
- limit.hi |= PKG_POWER_LIMIT_EN;
- /* Power limit 2 time is only programmable on server SKU */
-
- wrmsr(MSR_PKG_POWER_LIMIT, limit);
-
- /* Set power limit values in MCHBAR as well */
- MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo;
- MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
-
- /* Set DDR RAPL power limit by copying from MMIO to MSR */
- msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
- msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
- wrmsr(MSR_DDR_RAPL_LIMIT, msr);
-
- /* Use nominal TDP values for CPUs with configurable TDP */
- if (cpu_config_tdp_levels()) {
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- limit.hi = 0;
- limit.lo = msr.lo & 0xff;
- wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
- }
-}
-
static void configure_c_states(void)
{
msr_t msr;
diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h
index 93d8a01..90ea613 100644
--- a/src/soc/intel/broadwell/include/soc/cpu.h
+++ b/src/soc/intel/broadwell/include/soc/cpu.h
@@ -38,10 +38,6 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
-/* Configure power limits for turbo mode */
-void set_power_limits(u8 power_limit_1_time);
-int cpu_config_tdp_levels(void);
-
/* CPU identification */
u32 cpu_family_model(void);
u32 cpu_stepping(void);
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 7328f19..ab97b90 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -4,6 +4,8 @@
#ifndef _BROADWELL_MSR_H_
#define _BROADWELL_MSR_H_
+#include <intelblocks/msr.h>
+
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
@@ -46,14 +48,6 @@
#define IRTL_RESPONSE_MASK (0x3ff)
#define MSR_COUNTER_24_MHZ 0x637
-/* long duration in low dword, short duration in high dword */
-#define MSR_PKG_POWER_LIMIT 0x610
-#define PKG_POWER_LIMIT_MASK 0x7fff
-#define PKG_POWER_LIMIT_EN (1 << 15)
-#define PKG_POWER_LIMIT_CLAMP (1 << 16)
-#define PKG_POWER_LIMIT_TIME_SHIFT 17
-#define PKG_POWER_LIMIT_TIME_MASK 0x7f
-
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
#define MSR_PKG_POWER_SKU_UNIT 0x606
diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h
new file mode 100644
index 0000000..ff77168
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/soc_chip.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_BROADWELL_SOC_CHIP_H_
+#define _SOC_BROADWELL_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index ac1008b..5adb731 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -9,6 +9,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/power_limit.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
@@ -405,6 +406,7 @@
static void systemagent_init(struct device *dev)
{
+ struct soc_power_limits_config *config;
u8 bios_reset_cpl, pair;
/* Enable Power Aware Interrupt Routing */
@@ -424,7 +426,8 @@
/* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
- set_power_limits(28);
+ config = config_of_soc();
+ set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config);
}
static struct device_operations systemagent_ops = {
--
To view, visit https://review.coreboot.org/c/coreboot/+/41234
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Gerrit-Change-Number: 41234
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-MessageType: newchange
4
5