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Change in coreboot[master]: cpu/intel/broadwell: Add Kconfig
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41931 ) Change subject: cpu/intel/broadwell: Add Kconfig ...................................................................... cpu/intel/broadwell: Add Kconfig Move the CPU-related Kconfig settings from soc to the cpu scope. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 43 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..b609422 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -14,6 +14,7 @@ source "src/cpu/intel/model_f3x/Kconfig" source "src/cpu/intel/model_f4x/Kconfig" source "src/cpu/intel/haswell/Kconfig" +source "src/cpu/intel/broadwell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" source "src/cpu/intel/socket_BGA956/Kconfig" diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 21dc291..95e4b11 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,7 +13,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell +subdirs-$(CONFIG_CPU_INTEL_BROADWELL) += broadwell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/broadwell/Kconfig b/src/cpu/intel/broadwell/Kconfig new file mode 100644 index 0000000..5889646 --- /dev/null +++ b/src/cpu/intel/broadwell/Kconfig @@ -0,0 +1,40 @@ +config CPU_INTEL_BROADWELL + bool + help + Intel Broadwell and Haswell ULT CPU support. + +if CPU_INTEL_BROADWELL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select NO_FIXED_XIP_ROM_SIZE + select PARALLEL_MP + select SMP + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select TSC_SYNC_MFENCE + select UDELAY_TSC + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config IED_REGION_SIZE + hex + default 0x400000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +endif diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bdbdda4..2048d97 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,14 +8,9 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -25,14 +20,10 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE - select PARALLEL_MP select REG_SCRIPT select RTC - select SMP select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -40,11 +31,6 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE - select UDELAY_TSC config PCIEXP_ASPM bool @@ -90,18 +76,6 @@ hex default 0xf0000000 -config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406" -- To view, visit https://review.coreboot.org/c/coreboot/+/41931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Gerrit-Change-Number: 41931 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/broadwell: Add Kconfig
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41932 ) Change subject: northbridge/intel/broadwell: Add Kconfig ...................................................................... northbridge/intel/broadwell: Add Kconfig Move the northbridge Kconfig settings to the corresponding scope. Also, correct `initialse` to `initialize`, as fixed on Haswell. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/broadwell/Kconfig M src/northbridge/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/Kconfig 3 files changed, 121 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41932/1 diff --git a/src/northbridge/intel/broadwell/Kconfig b/src/northbridge/intel/broadwell/Kconfig new file mode 100644 index 0000000..3207a04 --- /dev/null +++ b/src/northbridge/intel/broadwell/Kconfig @@ -0,0 +1,119 @@ +config NORTHBRIDGE_INTEL_BROADWELL + def_bool n + select CACHE_MRC_SETTINGS + select CPU_INTEL_BROADWELL + select INTEL_GMA_ACPI + select MRC_SETTINGS_PROTECT + +if NORTHBRIDGE_INTEL_BROADWELL + +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialize memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DCACHE_RAM_BASE + hex + default 0xff7c0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x30000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config HAVE_MRC + bool "Add a Memory Reference Code binary" + help + Select this option to add a Memory Reference Code binary to + the resulting coreboot image. + + Note: Without this binary coreboot will not work + +if HAVE_MRC + +config MRC_FILE + string "Intel Memory Reference Code path and filename" + depends on HAVE_MRC + default "mrc.bin" + help + The filename of the file to use as Memory Reference Code binary. + +config MRC_BIN_ADDRESS + hex + default 0xfffa0000 + +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + +endif # HAVE_MRC + +config PRE_GRAPHICS_DELAY + int "Graphics initialization delay in ms" + default 0 + help + On some systems, coreboot boots so fast that connected monitors + (mostly TVs) won't be able to wake up fast enough to talk to the + VBIOS. On those systems we need to wait for a bit before executing + the VBIOS. + +config HAVE_REFCODE_BLOB + depends on ARCH_X86 + bool "An external reference code blob should be put into cbfs." + default n + help + The reference code blob will be placed into cbfs. + +if HAVE_REFCODE_BLOB + +config REFCODE_BLOB_FILE + string "Path and filename to reference code blob." + default "refcode.elf" + help + The path and filename to the file to be added to cbfs. + +endif # HAVE_REFCODE_BLOB + +endif diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 77e96ce..cbcc631 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_BROADWELL),y) bootblock-y += bootblock.c diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2048d97..e61bee8 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -9,8 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES - select CACHE_MRC_SETTINGS - select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -18,8 +16,7 @@ select HAVE_USBDEBUG select IOAPIC select INTEL_DESCRIPTOR_MODE_CAPABLE - select INTEL_GMA_ACPI - select MRC_SETTINGS_PROTECT + select NORTHBRIDGE_INTEL_BROADWELL select REG_SCRIPT select RTC select SOC_INTEL_COMMON @@ -52,98 +49,6 @@ bool default y -config BROADWELL_VBOOT_IN_BOOTBLOCK - depends on VBOOT - bool "Start verstage in bootblock" - default y - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - help - Broadwell can either start verstage in a separate stage - right after the bootblock has run or it can start it - after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which - needs to be located at a fixed offset. Therefore even with - a separate verstage starting after the bootblock that same - binary is used meaning a jump is made from RW to the RO region - and back to the RW region after the binary is done. - -config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config VGA_BIOS_ID - string - default "8086,0406" - -config DCACHE_RAM_BASE - hex - default 0xff7c0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE - must add up to a power of 2. - -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x30000 - help - The amount of cache-as-ram region required by the reference code. - -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - -config HAVE_MRC - bool "Add a Memory Reference Code binary" - help - Select this option to add a Memory Reference Code binary to - the resulting coreboot image. - - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel Memory Reference Code path and filename" - depends on HAVE_MRC - default "mrc.bin" - help - The filename of the file to use as Memory Reference Code binary. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -# The UEFI System Agent binary needs to be at a fixed offset in the flash -# and can therefore only reside in the COREBOOT fmap region -config RO_REGION_ONLY - string - depends on VBOOT - default "mrc.bin" - -endif # HAVE_MRC - -config PRE_GRAPHICS_DELAY - int "Graphics initialization delay in ms" - default 0 - help - On some systems, coreboot boots so fast that connected monitors - (mostly TVs) won't be able to wake up fast enough to talk to the - VBIOS. On those systems we need to wait for a bit before executing - the VBIOS. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n @@ -170,21 +75,4 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Gerrit-Change-Number: 41932 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/intel/wildcatpoint: Add Kconfig
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41933 ) Change subject: southbridge/intel/wildcatpoint: Add Kconfig ...................................................................... southbridge/intel/wildcatpoint: Add Kconfig Move the southbridge Kconfig settings to the corresponding scope. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I96424fa6b2521487a29fd624a394a21bc6e663b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig A src/southbridge/intel/wildcatpoint/Kconfig M src/southbridge/intel/wildcatpoint/Makefile.inc 3 files changed, 80 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41933/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index e61bee8..2556ee2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -1,78 +1,6 @@ config SOC_INTEL_BROADWELL bool + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT help Intel Broadwell and Haswell ULT support. - -if SOC_INTEL_BROADWELL - -config SOC_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select BOOT_DEVICE_SUPPORTS_WRITES - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select HAVE_SMI_HANDLER - select HAVE_SPI_CONSOLE_SUPPORT - select HAVE_USBDEBUG - select IOAPIC - select INTEL_DESCRIPTOR_MODE_CAPABLE - select NORTHBRIDGE_INTEL_BROADWELL - select REG_SCRIPT - select RTC - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SPI_FLASH - -config PCIEXP_ASPM - bool - default y - -config PCIEXP_AER - bool - default y - -config PCIEXP_COMMON_CLOCK - bool - default y - -config PCIEXP_CLK_PM - bool - default y - -config PCIEXP_L1_SUB_STATE - bool - default y - -config INTEL_PCH_UART_CONSOLE - bool "Use Serial IO UART for console" - default n - select DRIVERS_UART_8250MEM - -config INTEL_PCH_UART_CONSOLE_NUMBER - hex "Serial IO UART number to use for console" - default 0x0 - depends on INTEL_PCH_UART_CONSOLE - -config TTYS0_BASE - hex - default 0xd6000000 - depends on INTEL_PCH_UART_CONSOLE - -config EHCI_BAR - hex - default 0xd8000000 - -config SERIRQ_CONTINUOUS_MODE - bool - default y - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -endif diff --git a/src/southbridge/intel/wildcatpoint/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig new file mode 100644 index 0000000..6f8c29a --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/Kconfig @@ -0,0 +1,77 @@ +config SOUTHBRIDGE_INTEL_WILDCATPOINT + bool + help + Intel Wildcat Point and Lynx Point ULT PCH support. + +if SOUTHBRIDGE_INTEL_WILDCATPOINT + +config SOUTH_BRIDGE_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select BOOT_DEVICE_SUPPORTS_WRITES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_USBDEBUG + select IOAPIC + select INTEL_DESCRIPTOR_MODE_CAPABLE + select REG_SCRIPT + select RTC + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SPI_FLASH + +config PCIEXP_ASPM + bool + default y + +config PCIEXP_AER + bool + default y + +config PCIEXP_COMMON_CLOCK + bool + default y + +config PCIEXP_CLK_PM + bool + default y + +config PCIEXP_L1_SUB_STATE + bool + default y + +config INTEL_PCH_UART_CONSOLE + bool "Use Serial IO UART for console" + default n + select DRIVERS_UART_8250MEM + +config INTEL_PCH_UART_CONSOLE_NUMBER + hex "Serial IO UART number to use for console" + default 0x0 + depends on INTEL_PCH_UART_CONSOLE + +config TTYS0_BASE + hex + default 0xd6000000 + depends on INTEL_PCH_UART_CONSOLE + +config EHCI_BAR + hex + default 0xd8000000 + +config SERIRQ_CONTINUOUS_MODE + bool + default y + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +endif diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc index f1761f2..49a2094 100644 --- a/src/southbridge/intel/wildcatpoint/Makefile.inc +++ b/src/southbridge/intel/wildcatpoint/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y) romstage-y += early_pch.c romstage-y += early_smbus.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96424fa6b2521487a29fd624a394a21bc6e663b0 Gerrit-Change-Number: 41933 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/broadwell: Add ACPI
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41934 ) Change subject: northbridge/intel/broadwell: Add ACPI ...................................................................... northbridge/intel/broadwell: Add ACPI Move ACPI ASL files from the soc namespace to the northbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I8f6d8036dc2e875312c8f9b3604548e54ce66239 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/northbridge/intel/broadwell/acpi/broadwell.asl R src/northbridge/intel/broadwell/acpi/ctdp.asl R src/northbridge/intel/broadwell/acpi/pci_irqs.asl 7 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41934/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index c0f4d9f..0fa2d17 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 7770198..ad5ca61 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -25,7 +25,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index f9d4fe8..6453d7a 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -25,7 +25,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 5053a7d..68e97c3 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -21,7 +21,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/systemagent.asl rename to src/northbridge/intel/broadwell/acpi/broadwell.asl diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/northbridge/intel/broadwell/acpi/ctdp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ctdp.asl rename to src/northbridge/intel/broadwell/acpi/ctdp.asl diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/northbridge/intel/broadwell/acpi/pci_irqs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pci_irqs.asl rename to src/northbridge/intel/broadwell/acpi/pci_irqs.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/41934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f6d8036dc2e875312c8f9b3604548e54ce66239 Gerrit-Change-Number: 41934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/intel/wildcatpoint: Add ACPI
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41935 ) Change subject: southbridge/intel/wildcatpoint: Add ACPI ...................................................................... southbridge/intel/wildcatpoint: Add ACPI Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 0fa2d17..315b558 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -10,13 +10,13 @@ 0x20110725 // OEM revision ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl> // Thermal handler #include "acpi/thermal.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -25,7 +25,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index ad5ca61..396f105 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ #include <variant/acpi/thermal.asl> // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 6453d7a..119ab89 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 68e97c3..e0a07a9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -10,10 +10,10 @@ 0x20160115 /* OEM revision */ ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl> /* Global NVS and variables */ - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -22,7 +22,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/southbridge/intel/wildcatpoint/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/southbridge/intel/wildcatpoint/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/southbridge/intel/wildcatpoint/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/southbridge/intel/wildcatpoint/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/southbridge/intel/wildcatpoint/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/southbridge/intel/wildcatpoint/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/southbridge/intel/wildcatpoint/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/southbridge/intel/wildcatpoint/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/southbridge/intel/wildcatpoint/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/southbridge/intel/wildcatpoint/acpi/platform.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/platform.asl rename to src/southbridge/intel/wildcatpoint/acpi/platform.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/southbridge/intel/wildcatpoint/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/southbridge/intel/wildcatpoint/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/southbridge/intel/wildcatpoint/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/southbridge/intel/wildcatpoint/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/southbridge/intel/wildcatpoint/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/southbridge/intel/wildcatpoint/acpi/xhci.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/41935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Gerrit-Change-Number: 41935 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: cpu/intel/broadwell: Add header files
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41936 ) Change subject: cpu/intel/broadwell: Add header files ...................................................................... cpu/intel/broadwell: Add header files Relocate CPU-related headers from soc to cpu namespace. Note that the code in soc/intel/common expects to find the `soc/msr.h` header. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Ia9e860fbb02e2fd3c894236abbb784c21f231bbf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c A src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/cpu_info.c M src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/broadwell/tsc_freq.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/report_platform.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/msr.h M src/southbridge/intel/wildcatpoint/pcie.c M src/southbridge/intel/wildcatpoint/xhci.c 14 files changed, 122 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/41936/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index 316b85a..db5a232 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -16,10 +16,9 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 79f859b..3b041fe 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -7,7 +7,7 @@ #include <cpu/x86/mtrr.h> #include <halt.h> #include <soc/rcba.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <delay.h> static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/broadwell/broadwell.h b/src/cpu/intel/broadwell/broadwell.h new file mode 100644 index 0000000..5654e0a --- /dev/null +++ b/src/cpu/intel/broadwell/broadwell.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_CPU_H_ +#define _BROADWELL_CPU_H_ + +#include <device/device.h> + +/* CPU types */ +#define HASWELL_FAMILY_ULT 0x40650 +#define BROADWELL_FAMILY_ULT 0x306d0 + +/* Supported CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT 0x40651 +#define CPUID_HASWELL_HALO 0x40661 +#define CPUID_BROADWELL_C0 0x306d2 +#define CPUID_BROADWELL_D0 0x306d3 +#define CPUID_BROADWELL_E0 0x306d4 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + +/* Latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* MSR definitions */ +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) + +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 + +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_VR_MISC_CONFIG 0x603 +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_VR_MISC_CONFIG2 0x636 +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP1_POWER_LIMIT 0x640 + +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c + +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bits */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + +/* CPU identification */ +u32 cpu_family_model(void); +u32 cpu_stepping(void); +int cpu_is_ult(void); + +#endif diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index 7364876..ad1ce6d 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -3,8 +3,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/romstage.h> u32 cpu_family_model(void) diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index 1923301..cbb96bc 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -17,8 +17,7 @@ #include <cpu/x86/smm.h> #include <delay.h> #include <intelblocks/cpulib.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> diff --git a/src/cpu/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c index 5542f17..f4a8dad 100644 --- a/src/cpu/intel/broadwell/cpu_info.c +++ b/src/cpu/intel/broadwell/cpu_info.c @@ -2,8 +2,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/systemagent.h> u32 cpu_family_model(void) diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index 660a688..3f334d7 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -14,8 +14,7 @@ #include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> diff --git a/src/cpu/intel/broadwell/tsc_freq.c b/src/cpu/intel/broadwell/tsc_freq.c index 4a8a343..c467328 100644 --- a/src/cpu/intel/broadwell/tsc_freq.c +++ b/src/cpu/intel/broadwell/tsc_freq.c @@ -2,8 +2,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> unsigned long tsc_freq_mhz(void) { diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 41167b1..5f6673f 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -15,7 +15,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 1029395..88228f9 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -6,7 +6,7 @@ #include <device/pci.h> #include <string.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736..e69de29 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_CPU_H_ -#define _BROADWELL_CPU_H_ - -#include <device/device.h> - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* CPU identification */ -u32 cpu_family_model(void); -u32 cpu_stepping(void); -int cpu_is_ult(void); - -#endif diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 1e47b44..af717a2 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -1,73 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_MSR_H_ -#define _BROADWELL_MSR_H_ - #include <intelblocks/msr.h> - -#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_POWER_CTL 0x1fc -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -#define MSR_VR_CURRENT_CONFIG 0x601 -#define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 -#define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) - -#endif diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 9eb14d9..2ec714f 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -14,7 +14,7 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <delay.h> /* Low Power variant has 6 root ports. */ diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index 319c9b1..7541fef 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -9,7 +9,7 @@ #include <device/pci_ops.h> #include <soc/ramstage.h> #include <soc/xhci.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/41936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e860fbb02e2fd3c894236abbb784c21f231bbf Gerrit-Change-Number: 41936 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: northbridge/intel/broadwell: Add header files
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41937 ) Change subject: northbridge/intel/broadwell: Add header files ...................................................................... northbridge/intel/broadwell: Add header files Relocate northbridge-related headers from soc to the northbridge scope. Note that code in soc/intel/common expects to find `soc/systemagent.h`. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/broadwell_early_init.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/cpu_info.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c M src/northbridge/intel/broadwell/bootblock.c A src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c R src/northbridge/intel/broadwell/igd.h M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c R src/northbridge/intel/broadwell/pei_data.h R src/northbridge/intel/broadwell/pei_wrapper.h M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c R src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/power_state.c 55 files changed, 215 insertions(+), 205 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41937/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index db5a232..c052034 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -21,7 +21,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <intelblocks/cpulib.h> diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index ad1ce6d..4fd23f6 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index cbb96bc..f8189dd 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -21,7 +21,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> diff --git a/src/cpu/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c index f4a8dad..975a104 100644 --- a/src/cpu/intel/broadwell/cpu_info.c +++ b/src/cpu/intel/broadwell/cpu_info.c @@ -3,7 +3,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 54d6134..03a7e96 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -12,9 +12,9 @@ #include <timestamp.h> #include <soc/gpio.h> #include <soc/me.h> -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <soc/spi.h> void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index 3f334d7..ea38d15 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -16,7 +16,7 @@ #include <smp/node.h> #include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index ed17800..1540299 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/spd.h> #include "variant.h" diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 095096b..9853aa2 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -4,7 +4,7 @@ #define VARIANT_H #include <device/device.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 026853f..823c968 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 4dd1de6..fa15b34 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <variant/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index acf2a2d..bc345da 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -3,7 +3,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/pm.h> #include <smbios.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index bbc7125..e88972e 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 0daf308..7cf7e66 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index e8b3174..98424d8 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -3,7 +3,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/pm.h> #include <smbios.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 9bcf92b..eef54d4 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -3,8 +3,8 @@ #include <stdint.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 4684d86..213d4a5 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 12f4e86..baa0d52 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -4,7 +4,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <smbios.h> #include <variant/board_version.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 1f03aed..0b30542 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -3,9 +3,9 @@ #include <bootmode.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 911cf60..342f311 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <mainboard/google/jecht/spd/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index dc13022..6af5d83 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index 92101bd..bcf091a 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9e22250..9fc63cf 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> void mainboard_pre_raminit(struct romstage_params *rp) { diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 8fc2f9e..41447c9 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> void mainboard_pre_raminit(struct romstage_params *rp) { diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index 1e5d9d9..6fe5584 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index c3580b3..2a61fe6 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index ef55699..be389b7 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -3,7 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h new file mode 100644 index 0000000..8d71103 --- /dev/null +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ +#define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ + +#include <soc/iomap.h> + +#define SA_IGD_OPROM_VENDEV 0x80860406 + +#define IGD_HASWELL_ULT_GT1 0x0a06 +#define IGD_HASWELL_ULT_GT2 0x0a16 +#define IGD_HASWELL_ULT_GT3 0x0a26 +#define IGD_HASWELL_ULX_GT1 0x0a0e +#define IGD_HASWELL_ULX_GT2 0x0a1e +#define IGD_BROADWELL_U_GT1 0x1606 +#define IGD_BROADWELL_U_GT2 0x1616 +#define IGD_BROADWELL_U_GT3_15W 0x1626 +#define IGD_BROADWELL_U_GT3_28W 0x162b +#define IGD_BROADWELL_Y_GT2 0x161e +#define IGD_BROADWELL_H_GT2 0x1612 +#define IGD_BROADWELL_H_GT3 0x1622 + +#define MCH_BROADWELL_ID_U_Y 0x1604 +#define MCH_BROADWELL_REV_D0 0x06 +#define MCH_BROADWELL_REV_E0 0x08 +#define MCH_BROADWELL_REV_F0 0x09 + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define GGC 0x50 /* GMCH Graphics Control */ +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D1F0EN (1 << 3) +#define DEVEN_D1F1EN (1 << 2) +#define DEVEN_D1F2EN (1 << 1) +#define DEVEN_D0EN (1 << 0) +#define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ +#define REMAPBASE 0x90 /* Remap base. */ +#define REMAPLIMIT 0x98 /* Remap limit. */ +#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ +#define SKPAD 0xdc /* Scratchpad Data */ + +/* MCHBAR */ + +#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) + +#define MCHBAR_PEI_VERSION 0x5034 +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define MCH_PAIR 0x5418 +#define GDXCBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +/* PCODE MMIO communications live in the MCHBAR. */ +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 +/* Errors are returned back in bits 7:0. */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 +/* Data is passed through bits 31:0 of the data register. */ +#define BIOS_MAILBOX_DATA 0x5da0 + +/* System Agent identification */ +u8 systemagent_revision(void); + +uintptr_t sa_get_tolud_base(void); +uintptr_t sa_get_gsm_base(void); + +#endif diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c index 35ce010..d258694 100644 --- a/src/northbridge/intel/broadwell/finalize.c +++ b/src/northbridge/intel/broadwell/finalize.c @@ -11,7 +11,7 @@ #include <soc/me.h> #include <soc/rcba.h> #include <soc/spi.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/common/spi.h> const struct reg_script system_agent_finalize_script[] = { diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 5f6673f..3e47b53 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -18,10 +18,10 @@ #include <cpu/intel/broadwell/broadwell.h> #include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <security/vboot/vbnv.h> -#include <soc/igd.h> +#include <northbridge/intel/broadwell/igd.h> #include <types.h> #define GT_RETRY 1000 diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/northbridge/intel/broadwell/igd.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/igd.h rename to src/northbridge/intel/broadwell/igd.h diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c index bada5fd..c062d7d 100644 --- a/src/northbridge/intel/broadwell/memmap.c +++ b/src/northbridge/intel/broadwell/memmap.c @@ -7,7 +7,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <stdint.h> static uintptr_t dpr_region_start(void) diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index b91d73d..db15dbb 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -8,7 +8,7 @@ #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> -#include <soc/igd.h> +#include <northbridge/intel/broadwell/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index efc91fd..41fc475 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -2,8 +2,8 @@ #include <console/streams.h> #include <soc/iomap.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> static void ABI_X86 send_to_console(unsigned char b) { diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/northbridge/intel/broadwell/pei_data.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pei_data.h rename to src/northbridge/intel/broadwell/pei_data.h diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/pei_wrapper.h similarity index 94% rename from src/soc/intel/broadwell/include/soc/pei_wrapper.h rename to src/northbridge/intel/broadwell/pei_wrapper.h index 81e1bd5..44c23d0 100644 --- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h +++ b/src/northbridge/intel/broadwell/pei_wrapper.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_PEI_WRAPPER_H_ #define _BROADWELL_PEI_WRAPPER_H_ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data); diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index 8c194fc..dca56b6 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -15,11 +15,11 @@ #endif #include <vendorcode/google/chromeos/chromeos.h> #include <soc/iomap.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> #include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> /* * Find PEI executable in coreboot filesystem and execute it. diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 5e5bc49..5ba43cd 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -9,8 +9,8 @@ #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> #include <soc/pm.h> #include <soc/ramstage.h> diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 88228f9..1012ce2 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -9,8 +9,8 @@ #include <cpu/intel/broadwell/broadwell.h> #include <soc/pch.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> static struct { u32 cpuid; diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index 6f6db62..efc26d9 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -6,8 +6,8 @@ #include <reg_script.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> static const struct reg_script systemagent_early_init_script[] = { REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1), diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/northbridge/intel/broadwell/romstage.h similarity index 93% rename from src/soc/intel/broadwell/include/soc/romstage.h rename to src/northbridge/intel/broadwell/romstage.h index 2c7b0a4..275938a 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/northbridge/intel/broadwell/romstage.h @@ -4,7 +4,7 @@ #define _BROADWELL_ROMSTAGE_H_ #include <stdint.h> -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> struct chipset_power_state; struct romstage_params { diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index b75c4fe..15110da 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -14,7 +14,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> u8 systemagent_revision(void) { diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index c2c5cc8..5c93352 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -5,125 +5,6 @@ #include <soc/iomap.h> -#define SA_IGD_OPROM_VENDEV 0x80860406 - -#define IGD_HASWELL_ULT_GT1 0x0a06 -#define IGD_HASWELL_ULT_GT2 0x0a16 -#define IGD_HASWELL_ULT_GT3 0x0a26 -#define IGD_HASWELL_ULX_GT1 0x0a0e -#define IGD_HASWELL_ULX_GT2 0x0a1e -#define IGD_BROADWELL_U_GT1 0x1606 -#define IGD_BROADWELL_U_GT2 0x1616 -#define IGD_BROADWELL_U_GT3_15W 0x1626 -#define IGD_BROADWELL_U_GT3_28W 0x162b -#define IGD_BROADWELL_Y_GT2 0x161e -#define IGD_BROADWELL_H_GT2 0x1612 -#define IGD_BROADWELL_H_GT3 0x1622 - -#define MCH_BROADWELL_ID_U_Y 0x1604 -#define MCH_BROADWELL_REV_D0 0x06 -#define MCH_BROADWELL_REV_E0 0x08 -#define MCH_BROADWELL_REV_F0 0x09 - -/* Device 0:0.0 PCI configuration space */ - -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define GGC 0x50 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) -#define DPR 0x5c -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2) - -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define SKPAD 0xdc /* Scratchpad Data */ - -/* MCHBAR */ - -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 -#define GFXVTBAR 0x5400 -#define EDRAMBAR 0x5408 -#define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 -#define GDXCBAR 0x5420 - -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 -#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - -/* System Agent identification */ -u8 systemagent_revision(void); - -uintptr_t sa_get_tolud_base(void); -uintptr_t sa_get_gsm_base(void); - #endif diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index c7b3e67..61af770 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -9,7 +9,7 @@ #include <soc/spi.h> #include <reg_script.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> /* * Enable Prefetching and Caching. diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index 9afb4e4..9b73760 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,7 +11,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/rcba.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h> diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index a000255..5da5f4e 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -6,7 +6,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/smbus.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> static const struct reg_script smbus_init_script[] = { /* Set SMBUS I/O base address */ diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index 8128458..b9263b4 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -13,7 +13,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> static struct chipset_power_state power_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/41937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708 Gerrit-Change-Number: 41937 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 14

Change in coreboot[master]: southbridge/intel/wildcatpoint: Add header files
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41938 ) Change subject: southbridge/intel/wildcatpoint: Add header files ...................................................................... southbridge/intel/wildcatpoint: Add header files Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 115 files changed, 280 insertions(+), 279 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index c052034..bd4eb63 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -15,14 +15,14 @@ #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <intelblocks/cpulib.h> /* diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 3b041fe..3290eee 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -6,7 +6,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <halt.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h> diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c index 16afcce..443faf4 100644 --- a/src/cpu/intel/broadwell/chip.c +++ b/src/cpu/intel/broadwell/chip.c @@ -2,10 +2,10 @@ #include <device/device.h> #include <device/pci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index f8189dd..f8132b5 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -18,11 +18,11 @@ #include <delay.h> #include <intelblocks/cpulib.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/common/common.h> /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 03a7e96..35bb592 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -10,12 +10,12 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> -#include <soc/gpio.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <northbridge/intel/broadwell/pei_data.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/spi.h> void fill_postcar_frame(struct postcar_frame *pcf) { diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index ea38d15..dd96030 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -15,7 +15,7 @@ #include <console/console.h> #include <smp/node.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index befe84e..616b51a 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -2,8 +2,8 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h> void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2827cb1..dbcb25e 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -2,7 +2,7 @@ #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index edbd9b6..eff3905 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -4,12 +4,12 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "ec.h" #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/auron_paine/gpio.c b/src/mainboard/google/auron/variants/auron_paine/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_paine/gpio.c +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/gpio.c b/src/mainboard/google/auron/variants/auron_yuna/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/gpio.c +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/buddy/gpio.c b/src/mainboard/google/auron/variants/buddy/gpio.c index fcb63a4..8e09897 100644 --- a/src/mainboard/google/auron/variants/buddy/gpio.c +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 823c968..5719a58 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 81bb828..7e5c1fe 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -8,7 +8,7 @@ #include <console/console.h> #include <device/device.h> #include <smbios.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/gandof/gpio.c b/src/mainboard/google/auron/variants/gandof/gpio.c index 5b7ed82..051d921 100644 --- a/src/mainboard/google/auron/variants/gandof/gpio.c +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index bc345da..98f489e 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/lulu/gpio.c b/src/mainboard/google/auron/variants/lulu/gpio.c index b049bde..aaf865c 100644 --- a/src/mainboard/google/auron/variants/lulu/gpio.c +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index e88972e..447d0a0 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 7cf7e66..d4ed494 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 98424d8..2d60232 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/samus/gpio.c b/src/mainboard/google/auron/variants/samus/gpio.c index 12e9e64..1416c46 100644 --- a/src/mainboard/google/auron/variants/samus/gpio.c +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index eef54d4..bd34d90 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -2,7 +2,7 @@ #include <stdint.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 213d4a5..5c45ca9 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index baa0d52..2a04a83 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <smbios.h> #include <variant/board_version.h> diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 50bd1e0..bcf6127 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h> void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 86d1e79..23298e7 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -5,8 +5,8 @@ #include <device/device.h> #include <vendorcode/google/chromeos/chromeos.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/sata.h> #include "onboard.h" #define GPIO_SPI_WP 58 diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 3d19f99..b31683f 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include "onboard.h" static unsigned int search(char *p, u8 *a, unsigned int lengthp, diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 7072f8b..f407bcf 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -3,11 +3,11 @@ #include <acpi/acpi.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "onboard.h" int mainboard_io_trap_handler(int smif) diff --git a/src/mainboard/google/jecht/variants/guado/gpio.c b/src/mainboard/google/jecht/variants/guado/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/guado/gpio.c +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/jecht/gpio.c b/src/mainboard/google/jecht/variants/jecht/gpio.c index 92470cd..4aee5df 100644 --- a/src/mainboard/google/jecht/variants/jecht/gpio.c +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/rikku/gpio.c b/src/mainboard/google/jecht/variants/rikku/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/rikku/gpio.c +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/tidus/gpio.c b/src/mainboard/google/jecht/variants/tidus/gpio.c index 805b617..9c3d934 100644 --- a/src/mainboard/google/jecht/variants/tidus/gpio.c +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 6af5d83..35dc2e7 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 960dbde..b601ea3 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 459560c..c4470c6 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -3,7 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> /* Compile-time settings for recovery mode. */ diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 77231e2..b85eba74 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c index c779ef0..868e58e 100644 --- a/src/mainboard/intel/wtm2/gpio.c +++ b/src/mainboard/intel/wtm2/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index bcf091a..8795cf3 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9fc63cf..cc8e8e4 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> #include <northbridge/intel/broadwell/romstage.h> diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 8383f63..8b719bd 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,8 +2,8 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index b756fb9..10c9b78 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 57afe56..555b069 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl index 258e6e7..12296cb 100644 --- a/src/northbridge/intel/broadwell/acpi/broadwell.asl +++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index be389b7..89ff992 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -2,7 +2,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 8d71103..5f4ad6c 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -3,7 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ #define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define SA_IGD_OPROM_VENDEV 0x80860406 diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c index d258694..ccd3e74 100644 --- a/src/northbridge/intel/broadwell/finalize.c +++ b/src/northbridge/intel/broadwell/finalize.c @@ -6,11 +6,11 @@ #include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> -#include <soc/pci_devs.h> -#include <soc/lpc.h> -#include <soc/me.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/common/spi.h> diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 3e47b53..6c0da56 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -16,10 +16,10 @@ #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <security/vboot/vbnv.h> #include <northbridge/intel/broadwell/igd.h> #include <types.h> diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c index c062d7d..ca8b105 100644 --- a/src/northbridge/intel/broadwell/memmap.c +++ b/src/northbridge/intel/broadwell/memmap.c @@ -6,7 +6,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> #include <stdint.h> diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index db15dbb..7a93b9a 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/igd.h> static const u32 minihd_verb_table[] = { diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index 41fc475..56166eb 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/streams.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index dca56b6..d40c2a3 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -14,10 +14,10 @@ #include <ec/google/chromeec/ec_commands.h> #endif #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 5ba43cd..13be8b6 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -11,8 +11,8 @@ #include <stage_cache.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> static pei_wrapper_entry_t load_refcode_from_cache(void) { diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 1012ce2..3ac4ece 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -7,8 +7,8 @@ #include <string.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index efc26d9..064c203 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -4,8 +4,8 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index 15110da..67d78cf 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -10,10 +10,10 @@ #include <device/pci_ids.h> #include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> u8 systemagent_revision(void) diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index e69de29..0000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 8772a02..56dd799 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -1,56 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_NVS_H_ -#define _BROADWELL_NVS_H_ - -#include <commonlib/helpers.h> -#include <soc/device_nvs.h> -#include <vendorcode/google/chromeos/gnvs.h> - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u8 pcnt; /* 0x0b - Processor Count */ - u8 ppcm; /* 0x0c - Max PPC State */ - u8 tmps; /* 0x0d - Temperature Sensor ID */ - u8 tlvl; /* 0x0e - Throttle Level Limit */ - u8 flvl; /* 0x0f - Current FAN Level */ - u8 tcrt; /* 0x10 - Critical Threshold */ - u8 tpsv; /* 0x11 - Passive Threshold */ - u8 tmax; /* 0x12 - CPU Tj_max */ - u8 s5u0; /* 0x13 - Enable USB in S5 */ - u8 s3u0; /* 0x14 - Enable USB in S3 */ - u8 s33g; /* 0x15 - Enable 3G in S3 */ - u8 lids; /* 0x16 - LID State */ - u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ - u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ - u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - - u8 unused2[76]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; - - /* Device specific (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif +#include <southbridge/intel/wildcatpoint/nvs.h> diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 5c93352..8b6d4f3 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_SYSTEMAGENT_H_ #define _BROADWELL_SYSTEMAGENT_H_ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h similarity index 91% rename from src/soc/intel/broadwell/include/soc/acpi.h rename to src/southbridge/intel/wildcatpoint/acpi.h index 66ad450..618b627 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/southbridge/intel/wildcatpoint/acpi.h @@ -4,7 +4,7 @@ #define _BROADWELL_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/nvs.h> /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/southbridge/intel/wildcatpoint/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl index 07db9f7..540d262 100644 --- a/src/southbridge/intel/wildcatpoint/acpi/pch.asl +++ b/src/southbridge/intel/wildcatpoint/acpi/pch.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/iomap.h> - Scope (\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. diff --git a/src/southbridge/intel/wildcatpoint/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c index b8699a2..925b1b7 100644 --- a/src/southbridge/intel/wildcatpoint/adsp.c +++ b/src/southbridge/intel/wildcatpoint/adsp.c @@ -7,14 +7,14 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <soc/adsp.h> -#include <soc/device_nvs.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/adsp.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static void adsp_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/southbridge/intel/wildcatpoint/adsp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/adsp.h rename to src/southbridge/intel/wildcatpoint/adsp.h diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 61af770..572ea09 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -2,13 +2,13 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <reg_script.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> /* diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/southbridge/intel/wildcatpoint/device_nvs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/device_nvs.h rename to src/southbridge/intel/wildcatpoint/device_nvs.h diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index 9b73760..e8cb8aa 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -5,15 +5,15 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/smbus.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> const struct reg_script pch_interrupt_init_script[] = { /* diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index 5da5f4e..6f4d226 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -3,9 +3,9 @@ #include <device/pci_def.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <northbridge/intel/broadwell/romstage.h> static const struct reg_script smbus_init_script[] = { diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c index 5b977dd..81ad62d 100644 --- a/src/southbridge/intel/wildcatpoint/ehci.c +++ b/src/southbridge/intel/wildcatpoint/ehci.c @@ -5,8 +5,8 @@ #include <device/pci_ids.h> #include <device/pci_ehci.h> #include <device/pci_ops.h> -#include <soc/ehci.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/ehci.h> +#include <southbridge/intel/wildcatpoint/pch.h> static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/southbridge/intel/wildcatpoint/ehci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/ehci.h rename to src/southbridge/intel/wildcatpoint/ehci.h diff --git a/src/southbridge/intel/wildcatpoint/elog.c b/src/southbridge/intel/wildcatpoint/elog.c index f918958..6e39cd0 100644 --- a/src/southbridge/intel/wildcatpoint/elog.c +++ b/src/southbridge/intel/wildcatpoint/elog.c @@ -5,8 +5,8 @@ #include <console/console.h> #include <stdint.h> #include <elog.h> -#include <soc/lpc.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pm.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c index ff1f019..62a7335 100644 --- a/src/southbridge/intel/wildcatpoint/gpio.c +++ b/src/southbridge/intel/wildcatpoint/gpio.c @@ -4,9 +4,9 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pm.h> /* * This function will return a number that indicates which PIRQ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/southbridge/intel/wildcatpoint/gpio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/gpio.h rename to src/southbridge/intel/wildcatpoint/gpio.h diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c index 1640825..0dbe6cd 100644 --- a/src/southbridge/intel/wildcatpoint/hda.c +++ b/src/southbridge/intel/wildcatpoint/hda.c @@ -8,9 +8,9 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> static void codecs_init(u8 *base, u32 codec_mask) { diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c index 76a3e58..3332e26 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ b/src/southbridge/intel/wildcatpoint/iobp.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #define IOBP_RETRY 1000 diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/southbridge/intel/wildcatpoint/iobp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iobp.h rename to src/southbridge/intel/wildcatpoint/iobp.h diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iomap.h rename to src/southbridge/intel/wildcatpoint/iomap.h diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index 5cfeb5f..b7f1fe3 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -15,17 +15,17 @@ #include <cbmem.h> #include <reg_script.h> #include <string.h> -#include <soc/gpio.h> -#include <soc/iobp.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/southbridge/intel/wildcatpoint/lpc.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/lpc.h rename to src/southbridge/intel/wildcatpoint/lpc.h diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c index 7449902..3b1998e 100644 --- a/src/southbridge/intel/wildcatpoint/me.c +++ b/src/southbridge/intel/wildcatpoint/me.c @@ -20,13 +20,13 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <soc/me.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/southbridge/intel/wildcatpoint/me.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/me.h rename to src/southbridge/intel/wildcatpoint/me.h diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c index 11b21ac..d11b26c 100644 --- a/src/southbridge/intel/wildcatpoint/me_status.c +++ b/src/southbridge/intel/wildcatpoint/me_status.c @@ -4,8 +4,8 @@ #include <console/console.h> #include <device/pci.h> #include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <delay.h> #define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \ diff --git a/src/southbridge/intel/wildcatpoint/nvs.h b/src/southbridge/intel/wildcatpoint/nvs.h new file mode 100644 index 0000000..b5fca62 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/nvs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_NVS_H_ +#define _BROADWELL_NVS_H_ + +#include <commonlib/helpers.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u8 pcnt; /* 0x0b - Processor Count */ + u8 ppcm; /* 0x0c - Max PPC State */ + u8 tmps; /* 0x0d - Temperature Sensor ID */ + u8 tlvl; /* 0x0e - Throttle Level Limit */ + u8 flvl; /* 0x0f - Current FAN Level */ + u8 tcrt; /* 0x10 - Critical Threshold */ + u8 tpsv; /* 0x11 - Passive Threshold */ + u8 tmax; /* 0x12 - CPU Tj_max */ + u8 s5u0; /* 0x13 - Enable USB in S5 */ + u8 s3u0; /* 0x14 - Enable USB in S3 */ + u8 s33g; /* 0x15 - Enable 3G in S3 */ + u8 lids; /* 0x16 - LID State */ + u8 pwrs; /* 0x17 - AC Power State */ + u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ + u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ + u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ + u8 unused1[132]; /* 0x30 - 0xb3 - unused */ + + u8 unused2[76]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; + + /* Device specific (0x1000) */ + device_nvs_t dev; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +void acpi_create_gnvs(global_nvs_t *gnvs); + +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); + +#endif diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index 479323d..1ac2967 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -5,13 +5,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/spi.h> u8 pch_revision(void) { diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/southbridge/intel/wildcatpoint/pch.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pch.h rename to src/southbridge/intel/wildcatpoint/pch.h diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/southbridge/intel/wildcatpoint/pci_devs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pci_devs.h rename to src/southbridge/intel/wildcatpoint/pci_devs.h diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 2ec714f..4515ffb 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -7,13 +7,13 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/lpc.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h> diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/southbridge/intel/wildcatpoint/pm.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pm.h rename to src/southbridge/intel/wildcatpoint/pm.h diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c index 502a046..b66fb87 100644 --- a/src/southbridge/intel/wildcatpoint/pmutil.c +++ b/src/southbridge/intel/wildcatpoint/pmutil.c @@ -13,11 +13,11 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <security/vboot/vbnv.h> /* Print status bits with descriptive names */ diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index b9263b4..8522caa 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -9,10 +9,10 @@ #include <device/pci_def.h> #include <reg_script.h> #include <string.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> static struct chipset_power_state power_state; diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c index 39550b7..8859261 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.c +++ b/src/southbridge/intel/wildcatpoint/ramstage.c @@ -4,10 +4,10 @@ #include <cbmem.h> #include <device/device.h> #include <string.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <soc/intel/common/acpi.h> #include <assert.h> diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h similarity index 89% rename from src/soc/intel/broadwell/include/soc/ramstage.h rename to src/southbridge/intel/wildcatpoint/ramstage.h index 18a23e1..b50cd19 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/southbridge/intel/wildcatpoint/ramstage.h @@ -4,7 +4,7 @@ #define _BROADWELL_RAMSTAGE_H_ #include <device/device.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/southbridge/intel/wildcatpoint/rcba.h similarity index 98% rename from src/soc/intel/broadwell/include/soc/rcba.h rename to src/southbridge/intel/wildcatpoint/rcba.h index 3bacb9d..9d06992 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/southbridge/intel/wildcatpoint/rcba.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) #define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) diff --git a/src/southbridge/intel/wildcatpoint/sata.c b/src/southbridge/intel/wildcatpoint/sata.c index 5ddccc5..502d586 100644 --- a/src/southbridge/intel/wildcatpoint/sata.c +++ b/src/southbridge/intel/wildcatpoint/sata.c @@ -7,11 +7,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/sata.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static inline u32 sir_read(struct device *dev, int idx) { diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/southbridge/intel/wildcatpoint/sata.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/sata.h rename to src/southbridge/intel/wildcatpoint/sata.h diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c index 20a5d9a..3dbbc6e 100644 --- a/src/southbridge/intel/wildcatpoint/serialio.c +++ b/src/southbridge/intel/wildcatpoint/serialio.c @@ -7,14 +7,14 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> /* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/southbridge/intel/wildcatpoint/serialio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/serialio.h rename to src/southbridge/intel/wildcatpoint/serialio.h diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c index 562db4e..b8177e5 100644 --- a/src/southbridge/intel/wildcatpoint/smbus.c +++ b/src/southbridge/intel/wildcatpoint/smbus.c @@ -7,9 +7,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <device/smbus_host.h> static void pch_smbus_init(struct device *dev) diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/southbridge/intel/wildcatpoint/smbus.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/smbus.h rename to src/southbridge/intel/wildcatpoint/smbus.h diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c index 1d3860a..1dc8b59 100644 --- a/src/southbridge/intel/wildcatpoint/smi.c +++ b/src/southbridge/intel/wildcatpoint/smi.c @@ -6,9 +6,9 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <soc/iomap.h> -#include <soc/pch.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pm.h> void smm_southbridge_clear_state(void) { diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c index 85d6ae0..98e26ca 100644 --- a/src/southbridge/intel/wildcatpoint/smihandler.c +++ b/src/southbridge/intel/wildcatpoint/smihandler.c @@ -14,12 +14,12 @@ #include <elog.h> #include <halt.h> #include <option.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h> diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h similarity index 80% rename from src/soc/intel/broadwell/include/soc/soc_chip.h rename to src/southbridge/intel/wildcatpoint/soc_chip.h index bbd556e..c59f562 100644 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_ -#include "../../chip.h" +#include <soc/intel/broadwell/chip.h> #endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/southbridge/intel/wildcatpoint/spi.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/spi.h rename to src/southbridge/intel/wildcatpoint/spi.h diff --git a/src/southbridge/intel/wildcatpoint/uart.c b/src/southbridge/intel/wildcatpoint/uart.c index 6b0da2d..8d3e7a7 100644 --- a/src/southbridge/intel/wildcatpoint/uart.c +++ b/src/southbridge/intel/wildcatpoint/uart.c @@ -4,8 +4,8 @@ #include <reg_script.h> #include <stdint.h> #include <uart8250.h> -#include <soc/iobp.h> -#include <soc/serialio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/serialio.h> const struct reg_script uart_init[] = { /* Set MMIO BAR */ diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index 7541fef..cef2bed 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -7,8 +7,8 @@ #include <acpi/acpi.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <cpu/intel/broadwell/broadwell.h> #ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/southbridge/intel/wildcatpoint/xhci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/xhci.h rename to src/southbridge/intel/wildcatpoint/xhci.h -- To view, visit https://review.coreboot.org/c/coreboot/+/41938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Gerrit-Change-Number: 41938 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: soc/intel/broadwell: Move include folder to northbridge
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41939 ) Change subject: soc/intel/broadwell: Move include folder to northbridge ...................................................................... soc/intel/broadwell: Move include folder to northbridge Since we process soc files before southbridge files, the cppflags override does not work as intended if placed in the southbridge. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Iaa773923e37536d92cf54825db3291af2b3d9b54 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/broadwell/Makefile.inc R src/northbridge/intel/broadwell/include/soc/msr.h R src/northbridge/intel/broadwell/include/soc/nvs.h R src/northbridge/intel/broadwell/include/soc/systemagent.h D src/soc/intel/broadwell/Makefile.inc 5 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/41939/1 diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index cbcc631..51cf4a8 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_BROADWELL),y) +CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include + bootblock-y += bootblock.c ramstage-y += finalize.c diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/northbridge/intel/broadwell/include/soc/msr.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/msr.h rename to src/northbridge/intel/broadwell/include/soc/msr.h diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/northbridge/intel/broadwell/include/soc/nvs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/nvs.h rename to src/northbridge/intel/broadwell/include/soc/nvs.h diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/northbridge/intel/broadwell/include/soc/systemagent.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/systemagent.h rename to src/northbridge/intel/broadwell/include/soc/systemagent.h diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc deleted file mode 100644 index dada3d1..0000000 --- a/src/soc/intel/broadwell/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) - -CPPFLAGS_common += -Isrc/soc/intel/broadwell/include - -endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa773923e37536d92cf54825db3291af2b3d9b54 Gerrit-Change-Number: 41939 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: soc/intel/broadwell: Move chip.h to northbridge
by Angel Pons (Code Review) 30 Oct '20

30 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41941 ) Change subject: soc/intel/broadwell: Move chip.h to northbridge ...................................................................... soc/intel/broadwell: Move chip.h to northbridge We need to update the name of the config struct to make sconfig happy, but this means the resulting binaries are no longer reproducible... But now, soc/intel/broadwell is finally no more. Now we need to clean up the mess that was left after scattering everything into three parts... Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb R src/northbridge/intel/broadwell/chip.h M src/northbridge/intel/broadwell/igd.c M src/southbridge/intel/wildcatpoint/soc_chip.h 15 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/41941/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a84aa98..4bcf672 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131..ed33680 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280..e04744d 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5..6236e43 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96ca..dd61c18 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 19d0c48..bb8df2d 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Disable eDP Hotplug register "gpu_dp_d_hotplug" = "0x00" diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04..3b79ea3 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 13b9e5e..543570e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..11ae807 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Port 0 is HDD # Port 3 is M.2 NGFF diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..d526ac7 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Port 0 is HDD # Port 1 is M.2 NGFF diff --git a/src/soc/intel/broadwell/chip.h b/src/northbridge/intel/broadwell/chip.h similarity index 96% rename from src/soc/intel/broadwell/chip.h rename to src/northbridge/intel/broadwell/chip.h index 45f91d8..9a62630 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/northbridge/intel/broadwell/chip.h @@ -7,7 +7,7 @@ #include <intelblocks/cfg.h> #include <stdint.h> -struct soc_intel_broadwell_config { +struct northbridge_intel_broadwell_config { /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -155,6 +155,6 @@ int tcc_offset; }; -typedef struct soc_intel_broadwell_config config_t; +typedef struct northbridge_intel_broadwell_config config_t; #endif diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 6c0da56..b032782 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -575,7 +575,7 @@ static void gma_generate_ssdt(const struct device *dev) { - const struct soc_intel_broadwell_config *chip = dev->chip_info; + const struct northbridge_intel_broadwell_config *chip = dev->chip_info; drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } diff --git a/src/southbridge/intel/wildcatpoint/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h index c59f562..4f8d4af 100644 --- a/src/southbridge/intel/wildcatpoint/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_ -#include <soc/intel/broadwell/chip.h> +#include <northbridge/intel/broadwell/chip.h> #endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Gerrit-Change-Number: 41941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020