coreboot-gerrit June 2020

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30872 ) Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... Patch Set 10: (4 comments) https://review.coreboot.org/c/coreboot/+/30872/5/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/30872/5/src/arch/x86/car.ld@90 PS5, Line 90: _xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1); > > The references are in couple cache_as_ram. […] Ack https://review.coreboot.org/c/coreboot/+/30872/5/src/arch/x86/car.ld@92 PS5, Line 92: /* Use CACHE_ROM_SIZE instead ? */ > > <commonlib/helpers.h> from <cpu/x86/mtrr. […] Done https://review.coreboot.org/c/coreboot/+/30872/7/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/30872/7/src/arch/x86/car.ld@3 PS7, Line 3: #include <cpu/x86/mtrr.h> > What did we need this #include for again? LOG2CEIL is a linker thing. CACHE_ROM_SIZE https://review.coreboot.org/c/coreboot/+/30872/9/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/30872/9/src/arch/x86/car.ld@83 PS9, Line 83: _car_mtrr_start = _car_region_start; > And we'd expose this value for which stages? Presumably these would only need to be exposed in C_ENV […] We dropped C_ENVIRONMENT_BOOTBLOCK already. -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 18:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30872 to look at the new patch set (#10). Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... arch/x86: Add symbols for CAR MTRRs in linker script This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Also, linker scripts have LOG2CEIL which comes in handy to enforce MTRR alignments. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30872/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: console: Update for vboot before bootblock
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c@70 PS6, Line 70: CONFIG(EARLY_PCI_BRIDGE) > Looking at the other comments around it seems that you don't want to use coreboot's […] CB:42227 TBH.. I would just ignore the fact that you could select EARLY_PCI_BRIDGE as I assume you have SoC UARTs wired for closed-case debugging. If I read it correctly you wiil roll out custom PSP kernels for Chromebooks. I don't know how much of a chance you are leaving for any community initiated ports as PSP blobs do not transfer from one SKU to another due to signage. This is all speculation, little public information released... -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 17:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Karthik Ramasubramanian (Code Review) 10 Jun '20

10 Jun '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/41062/14/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41062/14/src/soc/intel/jasperlake/… PS14, Line 162: /* FiVR */ Is this configuration required even if FIVR is not used/enabled. Can you please mention why? -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 14 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 17:51:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Support adding camera power resource
by Matt Delco (Code Review) 10 Jun '20

10 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: Support adding camera power resource ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/41624/16/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/41624/16/src/drivers/intel/mipi_ca… PS16, Line 185: const char *pr3; IMO coreboot should be like other firmwares and not have a PR3 (or at least have a non-empty PR3) since it 1) tells the OS to leave the camera on in D3 and 2) inconsistently doesn't have a PR1 or PR2 for D1 and D2. A prior example and debate (which I don't plan to re-hash here, so mostly food for thought): https://review.coreboot.org/c/coreboot/+/28073 -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 16 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 17:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: templates: remove Dedede and Volteer Makefile.inc
by Paul Fagerburg (Code Review) 10 Jun '20

10 Jun '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42204 ) Change subject: templates: remove Dedede and Volteer Makefile.inc ...................................................................... templates: remove Dedede and Volteer Makefile.inc Because we don't need SPD_SOURCES for Dedede and Volteer-derived variants, there is no reason to have a Makefile.inc now as part of the templates. BUG=b:158492307 BRANCH=None TEST=Create new variant of volteer, waddledee, and waddledoo, and verify that we can still build the coreboot image. Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a --- D util/mainboard/google/volteer/template/Makefile.inc D util/mainboard/google/waddledee/template/Makefile.inc D util/mainboard/google/waddledoo/template/Makefile.inc 3 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42204/1 diff --git a/util/mainboard/google/volteer/template/Makefile.inc b/util/mainboard/google/volteer/template/Makefile.inc deleted file mode 100644 index 61b23ed..0000000 --- a/util/mainboard/google/volteer/template/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = diff --git a/util/mainboard/google/waddledee/template/Makefile.inc b/util/mainboard/google/waddledee/template/Makefile.inc deleted file mode 100644 index 6861194..0000000 --- a/util/mainboard/google/waddledee/template/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -SPD_SOURCES += empty #0b0000 diff --git a/util/mainboard/google/waddledoo/template/Makefile.inc b/util/mainboard/google/waddledoo/template/Makefile.inc deleted file mode 100644 index fd8d126..0000000 --- a/util/mainboard/google/waddledoo/template/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -SPD_SOURCES = empty #0b0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/42204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a Gerrit-Change-Number: 42204 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: _WIP_ src/amd/picasso: Update PCI bridge devices
by Marshall Dawson (Code Review) 10 Jun '20

10 Jun '20

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34425 ) Change subject: _WIP_ src/amd/picasso: Update PCI bridge devices ...................................................................... Abandoned See CB:41546 and CB:41542 -- To view, visit https://review.coreboot.org/c/coreboot/+/34425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Gerrit-Change-Number: 34425 Gerrit-PatchSet: 15 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: Add _L61 method for Thunderbolt Hot Plug event
by John Zhao (Code Review) 10 Jun '20

10 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42149 ) Change subject: Add _L61 method for Thunderbolt Hot Plug event ...................................................................... Add _L61 method for Thunderbolt Hot Plug event This change adds _L61 method for Thunderbolt Hot Plug event in the GPE scope. _L61 method invokes sub-method HPEV to support Hot Plug wake event from Thunderbolt PCIe root ports. _L61 intercepts Presence Detect Changed interrupt and make sure the L0s is disabled on empty slots prior booting to OS. BUG=b:156435065 TEST=Verified multiple hot plug successfully with Lenovo dock. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 214 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42149/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index abdcb51..72b5079 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -38,7 +38,7 @@ Method (BASE, 1) { Local0 = Arg0 & 0x7 /* Function number */ - Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ Local2 = (Local0 << 12) + (Local1 << 15) Local3 = \_SB.PCI0.GPCB() + Local2 Return (Local3) @@ -128,6 +128,106 @@ } } +Scope (_GPE) +{ + Method (_L61, 0, NotSerialized) + { + /* + * Delay for 100ms to meet the timing requirements of the PCI Express Base + * Specification, Revision 1.0A, Section 6.6 ("...software must wait at least + * 100ms from the end of reset of one or more device before it is permitted + * to issue Configuration Requests to those devices"). + */ + Sleep (100) + + If (CondRefOf (\_SB.PCI0.TXHC)) + { + \_SB.PCI0.TRP0.HPEV() + \_SB.PCI0.TRP1.HPEV() + \_SB.PCI0.TRP2.HPEV() + \_SB.PCI0.TRP3.HPEV() + } + + /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) + { + If (\_SB.PCI0.TRP0.PDCX) + { + /* Clear all status bits */ + \_SB.PCI0.TRP0.PDCX = 1 + \_SB.PCI0.TRP0.HPSX = 1 + /* + * Intercept Presence Detect Changed interrupt and make sure + * the L0s is disabled on empty slots prior booting to OS. + */ + If (!\_SB.PCI0.TRP0.PDSX) { + /* + * The PCIe slot is empty, so disable L0s on hot unplug. + */ + \_SB.PCI0.TRP0.L0SE = 0 + } + /* Performs proper notification to the OS. */ + Notify (\_SB.PCI0.TRP0, 0) + } + Else { + /* False event. Clear Hot-Plug status, then exit. */ + \_SB.PCI0.TRP0.HPSX = 1 + } + } + + /* Check Root Port 1 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) + { + If (\_SB.PCI0.TRP1.PDCX) + { + \_SB.PCI0.TRP1.PDCX = 1 + \_SB.PCI0.TRP1.HPSX = 1 + If (!\_SB.PCI0.TRP1.PDSX) { + \_SB.PCI0.TRP1.L0SE = 0 + } + Notify (\_SB.PCI0.TRP1, 0) + } + Else { + \_SB.PCI0.TRP1.HPSX = 1 + } + } + + /* Check Root Port 2 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) + { + If (\_SB.PCI0.TRP2.PDCX) + { + \_SB.PCI0.TRP2.PDCX = 1 + \_SB.PCI0.TRP2.HPSX = 1 + If (!\_SB.PCI0.TRP2.PDSX) { + \_SB.PCI0.TRP2.L0SE = 0 + } + Notify (\_SB.PCI0.TRP2, 0) + } + Else { + \_SB.PCI0.TRP2.HPSX = 1 + } + } + + /* Check Root Port 3 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) + { + If (\_SB.PCI0.TRP3.PDCX) + { + \_SB.PCI0.TRP3.PDCX = 1 + \_SB.PCI0.TRP3.HPSX = 1 + If (!\_SB.PCI0.TRP3.PDSX) { + \_SB.PCI0.TRP3.L0SE = 0 + } + Notify (\_SB.PCI0.TRP3, 0) + } + Else { + \_SB.PCI0.TRP3.HPSX = 1 + } + } + } +} + Scope (\_SB.PCI0) { /* @@ -320,48 +420,48 @@ { If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { Printf("TDM0 does not exist.") - } - - If (\_SB.PCI0.TDM0.STAT == 0) { - /* DMA0 is in D3Cold early. */ - \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ - - Printf("Bring TBT RPs out of D3Code.") - If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { - /* RP0 D3 cold exit. */ - \_SB.PCI0.TRP0.D3CX() - } - If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { - /* RP1 D3 cold exit. */ - \_SB.PCI0.TRP1.D3CX() - } - - /* - * Need to send Connect-Topology command when TBT host - * controller back to D0 from D3. - */ - If (\_SB.PCI0.TDM0.ALCT == 1) { - If (CTP0 == 1) { - /* - * Send Connect-Topology command if there is - * device present on PCIe RP. - */ - \_SB.PCI0.TDM0.CNTP() - - /* Indicate to wait Connect-Topology command. */ - \_SB.PCI0.TDM0.WACT = 1 - - /* Clear the connect states. */ - CTP0 = 0 - } - /* Disallow to send Connect-Topology command. */ - \_SB.PCI0.TDM0.ALCT = 0 - } } Else { - Printf("Drop TG0N due to it is already exit D3 cold.") + If (\_SB.PCI0.TDM0.STAT == 0) { + /* DMA0 is in D3Cold early. */ + \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ + + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* RP0 D3 cold exit. */ + \_SB.PCI0.TRP0.D3CX() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* RP1 D3 cold exit. */ + \_SB.PCI0.TRP1.D3CX() + } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM0.ALCT == 1) { + If (CTP0 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM0.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM0.WACT = 1 + + /* Clear the connect states. */ + CTP0 = 0 + } + /* Disallow to send Connect-Topology command. */ + \_SB.PCI0.TDM0.ALCT = 0 + } + } Else { + Printf("Drop TG0N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) } - /* TBT RTD3 exit 10ms delay. */ - Sleep (10) } /* @@ -371,26 +471,25 @@ { If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { Printf("TDM0 does not exist.") - } + } Else { + If (\_SB.PCI0.TDM0.STAT == 1) { + /* DMA0 is not in D3Cold now. */ + \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ - If (\_SB.PCI0.TDM0.STAT == 1) { - /* DMA0 is not in D3Cold now. */ - \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ - - Printf("Push TBT RPs to D3Cold together") - If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { - If (\_SB.PCI0.TRP0.PDSX == 1) { - CTP0 = 1 + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP0.PDSX == 1) { + CTP0 = 1 + } + /* Put RP0 to D3 cold. */ + \_SB.PCI0.TRP0.D3CE() } - /* Put RP0 to D3 cold. */ - \_SB.PCI0.TRP0.D3CE() - } - If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { - If (\_SB.PCI0.TRP1.PDSX == 1) { - CTP0 = 1 + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP1.PDSX == 1) { + CTP0 = 1 + } + /* Put RP1 to D3 cold. */ + \_SB.PCI0.TRP1.D3CE() } - /* Put RP1 to D3 cold. */ - \_SB.PCI0.TRP1.D3CE() } } } @@ -402,48 +501,48 @@ { If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { Printf("TDM1 does not exist.") - } - - If (\_SB.PCI0.TDM1.STAT == 0) { - /* DMA1 is in D3Cold early. */ - \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ - - Printf("Bring TBT RPs out of D3Code.") - If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { - /* RP2 D3 cold exit. */ - \_SB.PCI0.TRP2.D3CX() - } - If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { - /* RP3 D3 cold exit. */ - \_SB.PCI0.TRP3.D3CX() - } - - /* - * Need to send Connect-Topology command when TBT host - * controller back to D0 from D3. - */ - If (\_SB.PCI0.TDM1.ALCT == 1) { - If (CTP1 == 1) { - /* - * Send Connect-Topology command if there is - * device present on PCIe RP. - */ - \_SB.PCI0.TDM1.CNTP() - - /* Indicate to wait Connect-Topology command. */ - \_SB.PCI0.TDM1.WACT = 1 - - /* Clear the connect states. */ - CTP1 = 0 - } - /* Disallow to send Connect-Topology cmd. */ - \_SB.PCI0.TDM1.ALCT = 0 - } } Else { - Printf("Drop TG1N due to it is already exit D3 cold.") + If (\_SB.PCI0.TDM1.STAT == 0) { + /* DMA1 is in D3Cold early. */ + \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ + + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* RP2 D3 cold exit. */ + \_SB.PCI0.TRP2.D3CX() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* RP3 D3 cold exit. */ + \_SB.PCI0.TRP3.D3CX() + } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM1.ALCT == 1) { + If (CTP1 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM1.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM1.WACT = 1 + + /* Clear the connect states. */ + CTP1 = 0 + } + /* Disallow to send Connect-Topology cmd. */ + \_SB.PCI0.TDM1.ALCT = 0 + } + } Else { + Printf("Drop TG1N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) } - /* TBT RTD3 exit 10ms delay. */ - Sleep (10) } /* @@ -453,26 +552,25 @@ { If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { Printf("TDM1 does not exist.") - } + } Else { + If (\_SB.PCI0.TDM1.STAT == 1) { + /* DMA1 is not in D3Cold now */ + \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ - If (\_SB.PCI0.TDM1.STAT == 1) { - /* DMA1 is not in D3Cold now */ - \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ - - Printf("Push TBT RPs to D3Cold together") - If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { - If (\_SB.PCI0.TRP2.PDSX == 1) { - CTP1 = 1 + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP2.PDSX == 1) { + CTP1 = 1 + } + /* Put RP2 to D3 cold. */ + \_SB.PCI0.TRP2.D3CE() } - /* Put RP2 to D3 cold. */ - \_SB.PCI0.TRP2.D3CE() - } - If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { - If (\_SB.PCI0.TRP3.PDSX == 1) { - CTP1 = 1 + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP3.PDSX == 1) { + CTP1 = 1 + } + /* Put RP3 to D3 cold */ + \_SB.PCI0.TRP3.D3CE() } - /* Put RP3 to D3 cold */ - \_SB.PCI0.TRP3.D3CE() } } } @@ -536,7 +634,7 @@ } If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { - Printf("Error: Error: Timeout occurred.") + Printf("Error: Timeout occurred.") } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/42149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8 Gerrit-Change-Number: 42149 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: _WIP_ soc/amd/picasso: Update all remaining pci_devs
by Marshall Dawson (Code Review) 10 Jun '20

10 Jun '20

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34429 to review the following change. Change subject: _WIP_ soc/amd/picasso: Update all remaining pci_devs ...................................................................... _WIP_ soc/amd/picasso: Update all remaining pci_devs Unlike older products, many of the Family 17h PCI devices are not on bus 0, and therefore cannot be located using pcidev_on_root(). The PPR (PID #55570, NDA required) shows Bus A and Bus B devices, where 0:8.1 and 0:8.2 are the bridges to them. Also, unlike older products, the bridges are not hidden for the purpose of making devices appear to be on bus 0. Rework pci_devs.h and other files to account for the new topology. Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/pci_devs.h 1 file changed, 32 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34429/1 diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 28fa99f..de5e446 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -84,7 +84,6 @@ #define PCIE8_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) #define SOC_PCIE8_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) - /* Data Fabric functions */ #define DF_DEV 0x18 @@ -116,29 +115,6 @@ #define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) #define SOC_DF_F6_DEVFN _SOC_DEV(DF_DEV, 6) -/* USB 3.1 */ -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVID 0x15e0 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) -#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) - -/* USB 3.1 */ -#define XHCI1_DEV 0x0 -#define XHCI1_FUNC 4 -#define XHCI1_DEVID 0x15e1 -#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) -#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 @@ -153,25 +129,48 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) +/* + * Bus A devices + */ + /* Internal Graphics */ -#define GFX_DEV 0x1 +#define GFX_DEV 0x0 #define GFX_FUNC 0 #define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) /* HD Audio 0 */ -#define HDA0_DEV 0x1 +#define HDA0_DEV 0x0 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 +#define HDA0_DEVID 0x15de #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* HD Audio 1 */ -#define HDA1_DEV 0x9 -#define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a -#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) -#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) + +/* + * Bus B devices + */ + +/* SATA */ +#define SATA_DEV 0x0 +#define SATA_FUNC 0 +#define AHCI_DEVID_MS 0x7901 +#define AHCI_DEVID_AMD 0x7904 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) #endif /* __PI_PICASSO_PCI_DEVS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Gerrit-Change-Number: 34429 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by Ravi kumar (Code Review) 10 Jun '20

10 Jun '20

Ravi kumar has uploaded a new patch set (#65) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... HACK trogdor: optimize coreboot.rom for T32 flash script HACK Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/security/vboot/Makefile.inc A util/qualcomm/optimize_coreboot 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36278/65 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 65 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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