coreboot-gerrit June 2020

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Change in coreboot[master]: util/abuild: Ensure .xcompile exists
by Patrick Georgi (Code Review) 10 Jun '20

10 Jun '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29483 ) Change subject: util/abuild: Ensure .xcompile exists ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Gerrit-Change-Number: 29483 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 21:26:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Picasso: Load x86 microcode from CBFS modules
by Bao Zheng (Code Review) 10 Jun '20

10 Jun '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41719 to review the following change. Change subject: Picasso: Load x86 microcode from CBFS modules ...................................................................... Picasso: Load x86 microcode from CBFS modules Combine the Ucode binaries for 3 revisions of CPU into one CBFS module. "Include external microcode binary" need to be seleceted. The size of each binary is hardcoded. Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/cpu.c A src/soc/amd/picasso/microcode_picasso.c A src/soc/amd/picasso/update_microcode.c 5 files changed, 194 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41719/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 27c0232..5c205e7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -60,6 +60,8 @@ select FSP_USES_CB_STACK select UDK_2017_BINDING select HAVE_CF9_RESET + select SUPPORT_CPU_UCODE_IN_CBFS + select MICROCODE_BLOB_UNDISCLOSED config AMD_FP5 def_bool y if !AMD_FT5 @@ -382,6 +384,9 @@ depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" +config CPU_UCODE_BINARIES + default "3rdparty/blobs/soc/amd/picasso/PSP/UcodePatch_PCO_B0.bin 3rdparty/blobs/soc/amd/picasso/PSP/UcodePatch_PCO_B1.bin 3rdparty/blobs/soc/amd/picasso/PSP/UcodePatch_RV2_A0.bin" + endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9dda834..f88695e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -81,6 +81,8 @@ ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c +ramstage-y += update_microcode.c +ramstage-y += microcode_picasso.c all-y += reset.c @@ -367,9 +369,6 @@ $(OPT_PSP_PMUD_FILE2) \ $(OPT_PSP_PMUD_FILE3) \ $(OPT_PSP_PMUD_FILE4) \ - $(OPT_PSP_UCODE_FILE1) \ - $(OPT_PSP_UCODE_FILE2) \ - $(OPT_PSP_UCODE_FILE3) \ $(OPT_MP2CFG_FILE) \ $(OPT_ABL0_FILE) \ $(OPT_ABL1_FILE) \ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 2325994..c0589f2 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -17,6 +17,7 @@ #include <soc/smi.h> #include <soc/iomap.h> #include <console/console.h> +#include <cpu/amd/microcode.h> /* * MP and SMM loading initialization. @@ -109,6 +110,8 @@ { check_mca(); setup_lapic(); + + update_microcode(cpuid_eax(1)); } static struct device_operations cpu_dev_ops = { @@ -117,6 +120,8 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x810f80 }, + { X86_VENDOR_AMD, 0x810f81 }, + { X86_VENDOR_AMD, 0x820f81 }, { X86_VENDOR_AMD, PICASSO_CPUID }, { X86_VENDOR_AMD, RAVEN2_CPUID }, { 0, 0 }, diff --git a/src/soc/amd/picasso/microcode_picasso.c b/src/soc/amd/picasso/microcode_picasso.c new file mode 100644 index 0000000..fdc0bc6 --- /dev/null +++ b/src/soc/amd/picasso/microcode_picasso.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/microcode.h> +#include <cbfs.h> + +/* + * Values and header structure from: + * BKDG for AMD Family 16h Models 30h-3Fh Processors + * 52740 Rev 3.06 - March 18, 2016 + */ + +#define F16H_MPB_MAX_SIZE 3458 +#define F16H_MPB_DATA_OFFSET 32 + + /* + * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h + * Microcode Patch Block + * Microcode Header + * Microcode "Blob" + * ... + * ... + * (end of file) + * + * + * MICROCODE HEADER (offset 0 bytes from start of file) + * Total size = 32 bytes + * [0:3] Date code (32 bits) + * [4:7] Patch level (32 bits) + * [8:9] Microcode patch data ID (16 bits) + * [10:15] Reserved (48 bits) + * [16:19] Chipset 1 device ID (32 bits) + * [20:23] Chipset 2 device ID (32 bits) + * [24:25] Processor Revisions ID (16 bits) + * [26] Chipset 1 revision ID (8 bits) + * [27] Chipset 2 revision ID (8 bits) + * [28:31] Reserved (32 bits) + * + * MICROCODE BLOB (offset += 32) + * Total size = m bytes + * + */ + +struct microcode { + uint32_t date_code; + uint32_t patch_id; + + uint16_t mc_patch_data_id; + uint8_t reserved1[6]; + + uint32_t chipset1_dev_id; + uint32_t chipset2_dev_id; + + uint16_t processor_rev_id; + + uint8_t chipset1_rev_id; + uint8_t chipset2_rev_id; + + uint8_t reserved2[4]; + + uint8_t m_patch_data[F16H_MPB_MAX_SIZE-F16H_MPB_DATA_OFFSET]; + +}; + +static void apply_microcode_patch(const struct microcode *m) +{ + uint32_t new_patch_id; + msr_t msr; + + /* apply patch */ + msr.hi = 0; + msr.lo = (uint32_t)m; + + wrmsr(0xc0010020, msr); + + printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", + m->patch_id); + + /* patch authentication */ + msr = rdmsr(0x8b); + new_patch_id = msr.lo; + + printk(BIOS_DEBUG, "microcode: updated to patch id = 0x%08x %s\n", + new_patch_id, + (new_patch_id == m->patch_id) ? "success" : "fail"); +} + +static void amd_update_microcode(const void *ucode, size_t ucode_len, + uint32_t equivalent_processor_rev_id) +{ + const struct microcode *m; + const uint8_t *c = ucode; + + m = (struct microcode *)c; + + while ((uint32_t)m < (uint32_t)c + ucode_len) { + if (m->processor_rev_id == equivalent_processor_rev_id) + apply_microcode_patch(m); + m = (struct microcode *)((uint32_t)m + 3200); + } +} + +void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) +{ + const void *ucode; + size_t ucode_len; + + if (equivalent_processor_rev_id == 0) { + printk(BIOS_DEBUG, "microcode: rev id not found. " + "Skipping microcode patch!\n"); + return; + } + ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, + &ucode_len); + if (!ucode) { + printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. " + "Skipping updates.\n"); + return; + } + + #if 0 + if (ucode_len > F16H_MPB_MAX_SIZE || + ucode_len < F16H_MPB_DATA_OFFSET) { + printk(BIOS_DEBUG, "microcode file invalid. Skipping " + "updates.\n"); + return; + } + #endif + + amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); +} diff --git a/src/soc/amd/picasso/update_microcode.c b/src/soc/amd/picasso/update_microcode.c new file mode 100644 index 0000000..ab7da2c --- /dev/null +++ b/src/soc/amd/picasso/update_microcode.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <cpu/amd/microcode.h> + +struct id_mapping { + uint32_t orig_id; + uint16_t new_id; +}; + +static u16 get_equivalent_processor_rev_id(u32 orig_id) +{ + static const struct id_mapping id_mapping_table[] = { + /* Family 16h */ + + /* TODO This equivalent processor revisions ID needs verification */ + { 0x730f01, 0x7301 }, + { 0x810f81, 0x8181 }, + { 0x820f01, 0x8201 }, + //{ 0x810f81, 0x8180 }, + + /* Array terminator */ + { 0xffffff, 0x0000 }, + }; + + u32 new_id; + int i; + + new_id = 0; + + for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) { + if (id_mapping_table[i].orig_id == orig_id) { + new_id = id_mapping_table[i].new_id; + break; + } + } + + return new_id; +} + +void update_microcode(u32 cpu_deviceid) +{ + u32 equivalent_processor_rev_id = + get_equivalent_processor_rev_id(cpu_deviceid); + amd_update_microcode_from_cbfs(equivalent_processor_rev_id); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Gerrit-Change-Number: 41719 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao <zheng.bao(a)amd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by Paul Menzel (Code Review) 10 Jun '20

10 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... Patch Set 76: (1 comment) https://review.coreboot.org/c/coreboot/+/35508/76//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35508/76//COMMIT_MSG@7 PS76, Line 7: HACK trogdor: SoC makefile BLOB support HACK Please make it a statement by adding a verb (in imperative mood). -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 76 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jun 2020 20:05:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] arch/x86: Declare acpi_disable_sci_on_exit()
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36828 ) Change subject: [WIP] arch/x86: Declare acpi_disable_sci_on_exit() ...................................................................... [WIP] arch/x86: Declare acpi_disable_sci_on_exit() Change-Id: I9d9b2085c0f06235f1e7ea395c9df826c3988027 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/finalize.c M src/soc/amd/stoneyridge/finalize.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/denverton_ns/pmc.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 48 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36828/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c3e1b9c..0f0d19b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -62,6 +62,11 @@ return CONFIG(HAVE_SMI_HANDLER); } +static inline int acpi_disable_sci_on_exit(void) +{ + return CONFIG(HAVE_SMI_HANDLER); +} + /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; extern unsigned char _binary_smm_end[]; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 947337d..eb6dd3d 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -57,12 +57,10 @@ { finalize_cores(); - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - acpi_disable_sci(); - else - acpi_enable_sci(); - } + if (acpi_disable_sci_on_exit()) + acpi_disable_sci(); + else + acpi_enable_sci(); post_code(POST_OS_BOOT); } diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 947337d..eb6dd3d 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -57,12 +57,10 @@ { finalize_cores(); - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - acpi_disable_sci(); - else - acpi_enable_sci(); - } + if (acpi_disable_sci_on_exit()) + acpi_disable_sci(); + else + acpi_enable_sci(); post_code(POST_OS_BOOT); } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 3392614..0dbd91f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -424,7 +424,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1d2aa61..aebbead 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -106,7 +106,7 @@ void pmc_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b52087..75da082 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -38,7 +38,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 7759758..77d7159 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -338,12 +338,10 @@ static void lpc_final(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - } + if (acpi_disable_sci_on_exit()) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 6654830..9d093ec 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -354,12 +354,10 @@ static void lpc_final(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - } + if (acpi_disable_sci_on_exit()) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e7b7db8..b77a05b 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -418,7 +418,7 @@ static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 34250d39..30c0263 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -335,15 +335,13 @@ static void i82801gx_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 63d3ffe..3709f71 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -368,15 +368,13 @@ static void i82801ix_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a594452..a88b239 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -372,15 +372,13 @@ static void i82801jx_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..e20320e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -428,7 +428,7 @@ static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c8e91c3..63dcbc0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -490,7 +490,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d9b2085c0f06235f1e7ea395c9df826c3988027 Gerrit-Change-Number: 36828 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: cpu/intel/smm/srvstr: Clean up parallel SMM relocation
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41951 ) Change subject: cpu/intel/smm/srvstr: Clean up parallel SMM relocation ...................................................................... cpu/intel/smm/srvstr: Clean up parallel SMM relocation Change-Id: I65c078181970c5f391636b395483c7c7171e8897 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/smm/cpu_svrstr.c 1 file changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/41951/1 diff --git a/src/cpu/intel/smm/cpu_svrstr.c b/src/cpu/intel/smm/cpu_svrstr.c index 76c8a0f..f69aba3 100644 --- a/src/cpu/intel/smm/cpu_svrstr.c +++ b/src/cpu/intel/smm/cpu_svrstr.c @@ -20,7 +20,7 @@ * the saving state to each CPU's MSRs. At least one save state size * is required for the initial SMM entry for the BSP to determine if * parallel SMM relocation is even feasible. */ -static void per_cpu_smm_trigger(void) +static void per_cpu_smm_trigger_parallel(void) { /* * If smm_save_state_in_msrs is non-zero then parallel SMM relocation @@ -102,17 +102,21 @@ write_smm_msrs(cpu, relo_params); } -void select_mp_ops_em64t101_cpu_svrstr(struct mp_ops *mp_ops) +static int detect_cpu_svrstr(void) { msr_t smm_mca_cap; + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + return (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK); +} +void select_mp_ops_em64t101_cpu_svrstr(struct mp_ops *mp_ops) +{ select_mp_ops_em64t101(mp_ops); - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (!(smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK)) + if (!detect_cpu_svrstr()) return; printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); - mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger_parallel; mp_ops->relocation_handler = relocation_handler; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c078181970c5f391636b395483c7c7171e8897 Gerrit-Change-Number: 41951 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cpu/intel/car: Use symbols for CAR MTRR setup
by Aaron Durbin (Code Review) 10 Jun '20

10 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30873 ) Change subject: cpu/intel/car: Use symbols for CAR MTRR setup ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9 Gerrit-Change-Number: 30873 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Jun 2020 19:21:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ACPI: Move redundant FADT reserved entry
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42033 ) Change subject: ACPI: Move redundant FADT reserved entry ...................................................................... ACPI: Move redundant FADT reserved entry Change-Id: I35f66cdad6b8bedf4337aa8e5af7b0f1b53fe674 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 5 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42033/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 81a36fe..47f03c8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1240,13 +1240,16 @@ header->asl_compiler_revision = asl_revision; fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; + + fadt->dsdt = (unsigned long) dsdt; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; + /* should be 0 ACPI 3.0 */ + fadt->reserved = 0; + if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || CONFIG(SYSTEM_TYPE_LAPTOP)) fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 170f4b4..11211c2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -685,7 +685,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->reserved = 0; fadt->sci_int = 0x9; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4231cc7..23c391c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -505,7 +505,6 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->reserved = 0; fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7fd0954..c704015 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -516,7 +516,6 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->reserved = 0; fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index bdfd8e0..51db1f2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -579,7 +579,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->reserved = 0; fadt->sci_int = 0x9; -- To view, visit https://review.coreboot.org/c/coreboot/+/42033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f66cdad6b8bedf4337aa8e5af7b0f1b53fe674 Gerrit-Change-Number: 42033 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/xhci: Add an xhci driver to enumerate capabilities
by Raul Rangel (Code Review) 10 Jun '20

10 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41899 ) Change subject: device/xhci: Add an xhci driver to enumerate capabilities ...................................................................... device/xhci: Add an xhci driver to enumerate capabilities This will allow enumerating an xHCI controller to allow dynamically generating the ACPI device nodes. BUG=b:154756391 TEST=Boot trembyle and check the ACPI tables for XHCI nodes Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3065c3fffad01b5378a55cfe904f971079b13d0f --- M src/device/Makefile.inc A src/device/xhci.c A src/include/device/xhci.h 3 files changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/41899/1 diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2e62d42..7fc303b 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -62,3 +62,5 @@ ramstage-y += resource_allocator_common.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c + +ramstage-y += xhci.c diff --git a/src/device/xhci.c b/src/device/xhci.c new file mode 100644 index 0000000..6c3dcb9 --- /dev/null +++ b/src/device/xhci.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/xhci.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <arch/mmio.h> + +union xhci_ext_caps_header { + uint32_t val; + struct { + uint32_t cap_id : 8; + uint32_t next_ptr : 8; + uint32_t reserved : 16; + }; +}; + +enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)) +{ + struct resource *res; + uint8_t *bar; + uint32_t ext_caps_offset; + + if (!device || !callback) + return CB_ERR_ARG; + + res = find_resource(device, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "%s: Unable to find BAR resource for %s\n", __func__, + dev_path(device)); + return CB_ERR; + } + + if (res->limit > 0xFFFFFFFF) { + printk(BIOS_DEBUG, "%s: 64-bit BAR is not supported\n", __func__); + return CB_ERR; + } + + bar = (uint8_t *)(uintptr_t)res->base; + + ext_caps_offset = read16(bar + XHCI_HCCPARAMS1_XECP); + + /* Value is in units of words, so need to multiply by 4 to get the pointer value. */ + ext_caps_offset <<= 2; + + union xhci_ext_caps_header header; + struct xhci_ext_cap cap; + + while (ext_caps_offset) { + header.val = read32(bar + ext_caps_offset); + + cap.cap_id = header.cap_id; + + if (header.cap_id == XHCI_ECP_CAP_ID_SUPP) { + cap.supported_protocol.reg0 = header.val; + cap.supported_protocol.reg1 = read32(bar + ext_caps_offset + 0x4); + cap.supported_protocol.reg2 = read32(bar + ext_caps_offset + 0x8); + } + + callback(context, &cap); + + if (header.next_ptr) + ext_caps_offset += (header.next_ptr << 2); + else + ext_caps_offset = 0; + } + + return CB_SUCCESS; +} diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h new file mode 100644 index 0000000..e49c1cc --- /dev/null +++ b/src/include/device/xhci.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DEVICE_XHCI_H__ +#define __DEVICE_XHCI_H__ + +#include <stdint.h> +#include <device/device.h> +#include <commonlib/bsd/cb_err.h> + +#define XHCI_HCCPARAMS1_XECP 0x12 + +#define XHCI_ECP_CAP_ID_LEGACY 1 +#define XHCI_ECP_CAP_ID_SUPP 2 + +struct xhci_supported_protocol { + union { + uint32_t reg0; + struct { + uint32_t cap_id : 8; + uint32_t next_ptr : 8; + uint32_t minor_rev : 8; + uint32_t major_rev : 8; + }; + }; + union { + uint32_t reg1; + char name[4]; + }; + union { + uint32_t reg2; + struct { + uint32_t port_offset : 8; + uint32_t port_count : 8; + uint32_t reserved : 12; + uint32_t protocol_speed_id_count : 4; + }; + }; +}; + +struct xhci_ext_cap { + uint32_t cap_id; + union { + struct xhci_supported_protocol supported_protocol; + }; +}; + +/** + * Iterates over the xHCI Extended Capabilities List. + */ +enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)); + +#endif /* __DEVICE_XHCI_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3065c3fffad01b5378a55cfe904f971079b13d0f Gerrit-Change-Number: 41899 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: make VBOOT_LID_SWITCH depend on VBOOT
by Matt DeVillier (Code Review) 10 Jun '20

10 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42137 ) Change subject: mb/google/hatch: make VBOOT_LID_SWITCH depend on VBOOT ...................................................................... mb/google/hatch: make VBOOT_LID_SWITCH depend on VBOOT Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS case. Correct this so building without vboot/ChromeOS works properly Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42137/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 46aa4d1..2443114 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -3,7 +3,7 @@ def_bool n select BOARD_GOOGLE_HATCH_COMMON select SYSTEM_TYPE_LAPTOP - select VBOOT_LID_SWITCH + select VBOOT_LID_SWITCH if VBOOT config BOARD_GOOGLE_BASEBOARD_PUFF def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/42137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f Gerrit-Change-Number: 42137 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/common: Replace cse_bp with cse_lite in all console logs
by Sridhar Siricilla (Code Review) 10 Jun '20

10 Jun '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41972 ) Change subject: soc/intel/common: Replace cse_bp with cse_lite in all console logs ...................................................................... soc/intel/common: Replace cse_bp with cse_lite in all console logs Replace cse_bp with cse_lite in all serial console logs in the cse_lite.c TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3fc677c9ec1962199c91cc310d7695dded4e0ba0 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/41972/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1f9e2ce..6372248 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -222,19 +222,19 @@ }; if (!cse_is_bp_cmd_info_possible()) { - printk(BIOS_ERR, "cse_bp: CSE does not meet prerequisites\n"); + printk(BIOS_ERR, "cse_lite: CSE does not meet prerequisites\n"); return false; } size_t resp_size = sizeof(struct get_bp_info_rsp); if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size)) { - printk(BIOS_ERR, "cse_bp: Could not get partition info\n"); + printk(BIOS_ERR, "cse_lite: Could not get partition info\n"); return false; } if (bp_info_rsp->hdr.result) { - printk(BIOS_ERR, "cse_bp: Get partition info resp failed: %d\n", + printk(BIOS_ERR, "cse_lite: Get partition info resp failed: %d\n", bp_info_rsp->hdr.result); return false; } @@ -266,14 +266,14 @@ }; if (bp != RO && bp != RW) { - printk(BIOS_ERR, "cse_bp: Incorrect partition id(%d) is provided", bp); + printk(BIOS_ERR, "cse_lite: Incorrect partition id(%d) is provided", bp); return false; } - printk(BIOS_INFO, "cse_bp: Set Boot Partition Info Command (%s)\n", GET_BP_STR(bp)); + printk(BIOS_INFO, "cse_lite: Set Boot Partition Info Command (%s)\n", GET_BP_STR(bp)); if (!cse_is_bp_cmd_info_possible()) { - printk(BIOS_ERR, "cse_bp: CSE does not meet prerequisites\n"); + printk(BIOS_ERR, "cse_lite: CSE does not meet prerequisites\n"); return false; } @@ -284,7 +284,7 @@ return false; if (switch_resp.result) { - printk(BIOS_ERR, "cse_bp: Set Boot Partition Info Response Failed: %d\n", + printk(BIOS_ERR, "cse_lite: Set Boot Partition Info Response Failed: %d\n", switch_resp.result); return false; } @@ -302,7 +302,7 @@ do_global_reset(); - die("cse_bp: Failed to reset system\n"); + die("cse_lite: Failed to reset system\n"); /* Control never reaches here */ return false; @@ -317,7 +317,7 @@ if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || rw_bp->status == BP_STATUS_GENERAL_FAILURE) { - printk(BIOS_ERR, "cse_bp: RW BP (status:%u) is not valid\n", rw_bp->status); + printk(BIOS_ERR, "cse_lite: RW BP (status:%u) is not valid\n", rw_bp->status); return false; } return true; @@ -333,28 +333,28 @@ static struct get_bp_info_rsp cse_bp_info; if (vboot_recovery_mode_enabled()) { - printk(BIOS_DEBUG, "cse_bp: Skip switching to RW in the recovery path\n"); + printk(BIOS_DEBUG, "cse_lite: Skip switching to RW in the recovery path\n"); return; } /* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */ if (!cse_is_hfs3_fw_sku_lite()) { - printk(BIOS_ERR, "cse_bp: Not a CSE Lite SKU\n"); + printk(BIOS_ERR, "cse_lite: Not a CSE Lite SKU\n"); return; } if (!cse_get_bp_info(&cse_bp_info)) { - printk(BIOS_ERR, "cse_bp: Failed to get CSE boot partition info\n"); + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); cse_trigger_recovery(CSE_LITE_SKU_COMMUNICATION_ERROR); } if (!cse_is_rw_info_valid(&cse_bp_info.bp_info)) { - printk(BIOS_ERR, "cse_bp: CSE RW partition is not valid\n"); + printk(BIOS_ERR, "cse_lite: CSE RW partition is not valid\n"); cse_trigger_recovery(CSE_LITE_SKU_RW_JUMP_ERROR); } if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { - printk(BIOS_ERR, "cse_bp: Failed to switch to RW\n"); + printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n"); cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/41972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc677c9ec1962199c91cc310d7695dded4e0ba0 Gerrit-Change-Number: 41972 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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