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Change in ...coreboot[master]: drivers/spi: Instrument erase operation
by Paul Menzel (Code Review) 09 Jun '23

09 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31793 Change subject: drivers/spi: Instrument erase operation ...................................................................... drivers/spi: Instrument erase operation Verify console output contains the new string. BS: BS_DEV_INIT times (us): entry 0 run 72771 exit 0 Finalize devices... Devices finalized APIC 00: ** Enter AmdInitLate [00020004] SB800: sb_Late_Post AmdInitLate() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdInitLate [00020004] APIC 00: ** Enter AmdS3Save [0002000b] Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff1000 in 97754 usecs Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff0000 in 121777 usecs AmdS3Save() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdS3Save [0002000b] BS: BS_POST_DEVICE times (us): entry 0 run 3 exit 228371 Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/spi/spi_flash.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31793/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1f5227..7f64968 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -198,6 +198,9 @@ u32 start, end, erase_size; int ret = -1; u8 cmd[4]; + struct stopwatch sw; + + stopwatch_init(&sw); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -234,7 +237,8 @@ goto out; } - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x in %ld usecs\n", + len, start, stopwatch_duration_usecs(&sw)); out: return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/31793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Gerrit-Change-Number: 31793 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35029 ) Change subject: soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align ...................................................................... soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align This patch makes top_of_ram aligned in order to meet MTRR alignment requirments. Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 27 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35029/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9e2f2f8..d83da7f 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -133,6 +133,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps = pmc_get_power_state(); console_init(); @@ -155,12 +156,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index af65d38..0d8d4c8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -142,6 +142,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; console_init(); @@ -164,10 +165,12 @@ * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. + * This satisfies MTRR alignment requirements as well. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 4d0cc17..a083788 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -117,6 +117,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps = pmc_get_power_state(); console_init(); @@ -139,12 +140,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 1d925b3..0977614 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -145,6 +145,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps; console_init(); @@ -166,12 +167,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); if (CONFIG(HAVE_SMI_HANDLER)) { /* Cache the TSEG region. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff Gerrit-Change-Number: 35029 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/peppy: Add ALS as ACPI device Some of models of the C720 ca...
by Nicolò (Code Review) 09 Jun '23

09 Jun '23

Nicolò has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37994 ) Change subject: mb/google/peppy: Add ALS as ACPI device Some of models of the C720 can have an ISL29018 ambient light sensor on the mainboard, probably all the C720P have it. ...................................................................... mb/google/peppy: Add ALS as ACPI device Some of models of the C720 can have an ISL29018 ambient light sensor on the mainboard, probably all the C720P have it. This patch will provide a way for the kernel to access the ALS sensor even after the chromeos_laptop driver broke. Please note that this patch advertise the ALS as an ISL29023, this is due to the fact that the proximity function of the ISL2018 is available only if a properly IR LED is present with the sensor. The C720 doesn't have the IR LED circuit. More work will be required to properly set the _STA to help the kernel driver on probing of the device itself. Tested on 4.15+ Change-Id: I8ed5583afb2f866c1b21eb44f5188526cfb7ebd9 Signed-off-by: Nicolò Veronese <nicveronese(a)gmail.com> --- M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37994/1 diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index cc3e063..c3dfe5f 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -149,4 +149,37 @@ } } } + + Device (ALSD) + { + Name (_HID, "ISL29023") + Name (_DDN, "Renesas ALS") + Name (_UID, 6) + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1" // ResourceSource + ) + + // GPIO51 (ball R5) is PIRQT: PIRQL_GSI + PIRQL - PIRQT = PIRQW_GSI + // 27 + 3 - 11 = 35 + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_LIGHTSENSOR_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ed5583afb2f866c1b21eb44f5188526cfb7ebd9 Gerrit-Change-Number: 37994 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolò Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init: Refactor and comment staggered SMBASE calculation
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38783 ) Change subject: cpu/x86/mp_init: Refactor and comment staggered SMBASE calculation ...................................................................... cpu/x86/mp_init: Refactor and comment staggered SMBASE calculation Change-Id: I98f55938f224ee49361d73e68ace9f9fcee7f48a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/x86/mp_init.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38783/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 45f7337..77eb661 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -720,7 +720,7 @@ const struct smm_runtime *runtime; int cpu; uintptr_t curr_smbase; - uintptr_t perm_smbase; + uintptr_t staggered_smbase; p = arg; runtime = p->runtime; @@ -737,9 +737,13 @@ * The permanent handler runs with all cpus concurrently. Precalculate * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. + * + * Hardware assumes SMM entry at SMM_ENTRY_OFFSET, memory below this + * offset won't be accessed. `staggered_smbase` can point below actual + * SMRAM, hence. */ - perm_smbase = mp_state.perm_smbase; - perm_smbase -= cpu * runtime->save_state_size; + staggered_smbase = mp_state.perm_smbase; + staggered_smbase -= cpu * runtime->save_state_size; printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); @@ -747,7 +751,7 @@ mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); stm_setup(cpu, mp_state.perm_smbase, mp_state.perm_smsize, - perm_smbase, runtime->start32_offset); + staggered_smbase, runtime->start32_offset); } static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) -- To view, visit https://review.coreboot.org/c/coreboot/+/38783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f55938f224ee49361d73e68ace9f9fcee7f48a Gerrit-Change-Number: 38783 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32316 Change subject: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Kconfig 3 files changed, 13 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32316/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7e895b4..e65622c 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -34,6 +34,7 @@ #include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/raminit.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -263,13 +254,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 8442dfa..854c835 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -34,6 +34,7 @@ #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -255,13 +246,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index bb6e22c..59b012e 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR -- To view, visit https://review.coreboot.org/c/coreboot/+/32316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Gerrit-Change-Number: 32316 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34791 ) Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ...................................................................... soc/intel/cannonlake: Speed up postcar loading using intermediate caching This patch ensures intermediate caching is enabled to speed up loading and decompression of next stage as we are still in romstage and car tear down will be handled by next stage at its entry. TEST=cbmem -t shows ~2-4ms time savings in warm reboot case with this CL. Change-Id: I3ba63887acb5c4bdeaf3e21c24fb0e631362962c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34791/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 94b9899..04a9d53 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -127,6 +127,21 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } +/* + * Make sure we are enabling intermediate caching to speed up next stage + * (postcar/romstage) loading and decompression as we are still in romstage + * and car tear down will be handled by next stage at its entry. + */ +static void enable_ramstage_caching(uintptr_t base, size_t size) +{ + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); +} + asmlinkage void car_stage_entry(void) { bool s3wake; @@ -160,6 +175,8 @@ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + /* enabling intermediate caching */ + enable_ramstage_caching(top_of_ram, 16*MiB); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -- To view, visit https://review.coreboot.org/c/coreboot/+/34791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba63887acb5c4bdeaf3e21c24fb0e631362962c Gerrit-Change-Number: 34791 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Add postcar_frame_add_ramcache() API
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34805 ) Change subject: arch/x86: Add postcar_frame_add_ramcache() API ...................................................................... arch/x86: Add postcar_frame_add_ramcache() API This patch adds new API for intermediate caching top_of_ram and setting up required MTRR for next stage. Change-Id: Iddafb573afb4799de64754a94816d7f3f2f4982f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34805/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 293ca02..7dc4049 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -329,6 +329,13 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); /* + * Add variable MTRR covering the Top of RAM with given MTRR type. + */ +void postcar_frame_add_ramcache(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + + +/* * Push used MTRR and Max MTRRs on to the stack * and return pointer to stack top. */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 35e139f..8a1f6cb 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -120,6 +120,29 @@ postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } +/* + * Make sure we are enabling intermediate caching to speed up next stage + * (postcar/romstage) loading and decompression as we are still in romstage + * and CAR tear down will be handled by next stage at its entry. + */ +static void enable_top_of_ram_cache(uintptr_t base, size_t size) +{ + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); +} + +void postcar_frame_add_ramcache(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type) +{ + /* enable intermediate caching for Top of RAM */ + enable_top_of_ram_cache(addr, size); + postcar_frame_add_mtrr(pcf, addr, size, type); +} + void *postcar_commit_mtrrs(struct postcar_frame *pcf) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/34805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddafb573afb4799de64754a94816d7f3f2f4982f Gerrit-Change-Number: 34805 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Fixed configuration for DDR Size discovered by Coreboot
by Marc Karasek (Code Review) 09 Jun '23

09 Jun '23

Marc Karasek has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38904 ) Change subject: Fixed configuration for DDR Size discovered by Coreboot ...................................................................... Fixed configuration for DDR Size discovered by Coreboot For qemu-riscv value was incorrect. It was set to 32768 which in turn was being used as 32768MB (32+GB), instead of the 32MB it was intended to represent. Change value so it is a select option based on in menuconfig based on what you want coreboot to "discover" on boot. Current three options are : 128MB 256MB 512MB NOTE: You must specify greater than what is chosen from the above items on the qemu cmdline. Signed-off-by: Marc Karasek <mkarasek(a)cryptocoretech.com> Change-Id: Idef44eb8baf3e89d7c74fa452fc60b7beefa2c48 --- M src/mainboard/emulation/qemu-riscv/Kconfig 1 file changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38904/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 4d4c900..2a119a3 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -54,9 +54,35 @@ int default 1 +choice + prompt "DRAM SIZE MB" + help + Select the size of the DDR coreboot will find. + Note: You must specify a -m <size> greater than + what is chosen here. + + config COREBOOT_DDR_SIZE_128M + bool "128 MB" + help + Choose this option if you want coreboot to find 127MB DDR + + config COREBOOT_DDR_SIZE_256M + bool "256 MB" + help + Choose this option if you want coreboot to find 255MB DDR + + config COREBOOT_DDR_SIZE_512M + bool "512 MB" + help + Choose this option if you want coreboot to find 512MB DDR +endchoice + config DRAM_SIZE_MB int - default 32768 + default 32 + default 32 if COREBOOT_DDR_SIZE_128M + default 64 if COREBOOT_DDR_SIZE_256M + default 128 if COREBOOT_DDR_SIZE_512M config OPENSBI_PLATFORM string -- To view, visit https://review.coreboot.org/c/coreboot/+/38904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef44eb8baf3e89d7c74fa452fc60b7beefa2c48 Gerrit-Change-Number: 38904 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Karasek <marckarasek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add a doc describing an ACPI device for controlling platform radios.
by Matthew Garrett (Code Review) 09 Jun '23

09 Jun '23

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37991 ) Change subject: Add a doc describing an ACPI device for controlling platform radios. ...................................................................... Add a doc describing an ACPI device for controlling platform radios. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I94dc058825cb147aca0d007d68885d4bfbe580a8 --- M Documentation/acpi/index.md A Documentation/acpi/rfkill.md M src/arch/x86/include/arch/acpi.h 3 files changed, 111 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37991/1 diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md index 8add8db..d10bca5 100644 --- a/Documentation/acpi/index.md +++ b/Documentation/acpi/index.md @@ -9,3 +9,7 @@ ## devicetree - [Adding devices to a device tree](devicetree.md) + +## Radio device control + +- [Exposing an ACPI device for controlling radios](rfkill.md) diff --git a/Documentation/acpi/rfkill.md b/Documentation/acpi/rfkill.md new file mode 100644 index 0000000..ef54f16 --- /dev/null +++ b/Documentation/acpi/rfkill.md @@ -0,0 +1,106 @@ +# Coreboot platform rfkill control + +## Introduction + +Many devices support platform-level control over integrated radio devices +such as wifi or bluetooth cards. However, the ACPI specification provides +no generic mechanism for operating systems to interact with these platform +interfaces. This has led to a proliferation of vendor-specific control +mechanisms. Coreboot ports to existing platforms tend to mimic those +interfaces and make use of existing drivers, but this doesn't solve the +problem for devices where coreboot is the primary firmware implementation. + +This specification defines an ACPI device that exposes an interface for +controlling any radios defined by the platform. It is intended to allow for +generic OS drivers to be written which will then work on any coreboot +platform that implements this specification. + +## Device specification + +The coreboot rfkill device must be declared with a _HID of "BOOT0001". +It must implement the following ACPI methods: + +### DEVS + +This method provides a list of the supported radios whose state can be +controlledvia this device. It takes no arguments and returns a single +integer. The integer is a bitmask of radio types supported by the device, +defined as follows: + +| Bit | Radio type | +|-----|---------------| +| 0 | Wifi | +| 1 | Bluetooth | +| 2 | Ultra-Wideband| +| 3 | WiMax | +| 4 | WWAN | +| 5 | GPS | +| 6 | FM | +| 7 | NFC | + +### SSTA + +This defines the mutable ("soft") state of all radios in the system. This +method takes no arguments and returns a single integer. The integer is a +bitmask representing radio state using the same values as defined in +DEVS. If a bit is 1 then the radio is enabled. If a bit is 0 then the radio +is not present. If a bit is not set in the value returned by the DEVS method +then the meaning of the bit returned by SSTA is undefined. The state +returned by SSTA can be overridden by the CNTL method. + +### HSTA + +This defines the immutable ("hard") state of all radios in the system. This +method takes no arguments and returns a single integer. The integer is a +bitmask representing radio state using the same values as defined in +DEVS. If a bit is 1 then the radio is enabled. If a bit is 0 then the radio +is disabled. If a bit is not set in the value returned by the DEVS method +then the meaning of the bit returned by HSTA is undefined. The state +returned by HSTA cannot be overridden by the CNTL method. + +### CNTL + +This method takes a single integer as an argument and returns nothing. The +argument is a bitmask representing radio state using the same values as +defined in DEVS. If a bit is 1 then the platform should enable the +corresponding radio. If a bit is 0 then the platform should disable the +corresponding radio. This method only alters the soft radio state, not the +hard radio state. + +### Notifications + +The platform will send a Notify with a value of 0x80 if the state is updated +via any mechanism other than an OS request. The OS should then re-evaluate +the state by calling SSTA and HSTA. + +## Implementation design + +Two types of blocking are defined - "soft" and "hard". Soft state can be +overridden on request by the OS, for example in response to a hotkey +press. Hard state cannot be overridden by the OS, and should correspond to +cases where some external interface has requested that radios be disabled +(for example, a physical switch on the side of the device). Hard and soft +state should be tracked independently - for instance, if a radio is +currently enabled and then disabled via a physical switch being moved, the +state returned by SSTA should still indicate that the radio is enabled while +the state returned by HSTA should indicate that the radio is disabled. If +the OS then requests that the radio be disabled via the CNTL method, SSTA +and HSTA should now both indicate that the radio is disabled. If the +physical switch is now switched back, HSTA should indicate that the radio is +enabled but SSTA should still indicate that the radio is disabled. Only when +the OS requests that the radio be enabled via CNTL should the radio be +re-enabled. + +If the platform alters the radio state (in response to any form of policy +decision or in response to a physical switch), it should update the soft +block state (if the OS can override this decision) or the hard block state +(if the OS cannot override this decision) and then call Notify on the device +with an argument of 0x80. + +If the platform provides more than one radio of a given type, it should +implement an additional rfkill device. Each radio should only be represented +in a single device. + +If an rfkill device should be explicitly tied to a radio device, then the +radio should be exposed in the ACPI device heirarchy and an rfkill device +that controls only that radio implemented as a child of that device. diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 68475c1..e87df04 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -64,6 +64,7 @@ /* List of ACPI HID that use the coreboot ACPI ID */ enum coreboot_acpi_ids { COREBOOT_ACPI_ID_CBTABLE = 0x0000, /* BOOT0000 */ + COREBOOT_ACPI_ID_RFKILL = 0x0001, /* BOOT0001 */ COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94dc058825cb147aca0d007d68885d4bfbe580a8 Gerrit-Change-Number: 37991 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/sifive/fu540: Fix RISCV_ARCH / RISCV_ABI to support float
by Xiang Wang (Code Review) 09 Jun '23

09 Jun '23

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37593 ) Change subject: soc/sifive/fu540: Fix RISCV_ARCH / RISCV_ABI to support float ...................................................................... soc/sifive/fu540: Fix RISCV_ARCH / RISCV_ABI to support float fu540 hart 0 is based on rv64imac, other hart is based on rv64imafdc. coreboot supports low-privileged non-aligned memory access, which requires the compiler to enable floating-point functionality. Compiling the src/arch/riscv/fp_asm.S file before the correction will not generate any instructions. Change-Id: I0f4828046aeb4803d4437c6adad2191684a632f7 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/soc/sifive/fu540/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37593/1 diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 97c67bf..4ff2827 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -30,11 +30,11 @@ config RISCV_ARCH string - default "rv64imac" + default "rv64imafdc" config RISCV_ABI string - default "lp64" + default "lp64d" config RISCV_CODEMODEL string -- To view, visit https://review.coreboot.org/c/coreboot/+/37593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f4828046aeb4803d4437c6adad2191684a632f7 Gerrit-Change-Number: 37593 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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