coreboot-gerrit April 2020

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Change in coreboot[master]: mb/volteer: enable Early Command Training
by Nick Vaccaro (Code Review) 09 Apr '20

09 Apr '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40023 ) Change subject: mb/volteer: enable Early Command Training ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/40023/7/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/memory.c: https://review.coreboot.org/c/coreboot/+/40023/7/src/mainboard/google/volte… PS7, Line 61: *E nit - add a space betwee '*' and 'E' -- To view, visit https://review.coreboot.org/c/coreboot/+/40023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3 Gerrit-Change-Number: 40023 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Apr 2020 00:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/samsung/530u3c: Add new board
by Angel Pons (Code Review) 09 Apr '20

09 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40279 ) Change subject: [WIP] mb/samsung/530u3c: Add new board ...................................................................... [WIP] mb/samsung/530u3c: Add new board This board seems to have issues with video pipes. Both HDMI and eDP are funky with either vendor firmware or coreboot. Fortunately, I managed to boot with coreboot using the unfixed output of autoport. Needs wooork... Change-Id: I04c138ed9db3228ad8f253138f04ea61a10d0a65 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/samsung/530u3c/Kconfig A src/mainboard/samsung/530u3c/Kconfig.name A src/mainboard/samsung/530u3c/Makefile.inc A src/mainboard/samsung/530u3c/acpi/ec.asl A src/mainboard/samsung/530u3c/acpi/platform.asl A src/mainboard/samsung/530u3c/acpi/superio.asl A src/mainboard/samsung/530u3c/acpi_tables.c A src/mainboard/samsung/530u3c/board_info.txt A src/mainboard/samsung/530u3c/devicetree.cb A src/mainboard/samsung/530u3c/dsdt.asl A src/mainboard/samsung/530u3c/early_init.c A src/mainboard/samsung/530u3c/gma-mainboard.ads A src/mainboard/samsung/530u3c/gpio.c A src/mainboard/samsung/530u3c/hda_verb.c A src/mainboard/samsung/530u3c/mainboard.c 15 files changed, 671 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/40279/1 diff --git a/src/mainboard/samsung/530u3c/Kconfig b/src/mainboard/samsung/530u3c/Kconfig new file mode 100644 index 0000000..777f791 --- /dev/null +++ b/src/mainboard/samsung/530u3c/Kconfig @@ -0,0 +1,47 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_SAMSUNG_530U3C + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default samsung/530u3c + +config MAINBOARD_PART_NUMBER + string + default "530U3C/530U4C" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/samsung/530u3c/Kconfig.name b/src/mainboard/samsung/530u3c/Kconfig.name new file mode 100644 index 0000000..bcdd513 --- /dev/null +++ b/src/mainboard/samsung/530u3c/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SAMSUNG_530U3C + bool "530U3C/530U4C" diff --git a/src/mainboard/samsung/530u3c/Makefile.inc b/src/mainboard/samsung/530u3c/Makefile.inc new file mode 100644 index 0000000..fba28d7 --- /dev/null +++ b/src/mainboard/samsung/530u3c/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/samsung/530u3c/acpi/ec.asl b/src/mainboard/samsung/530u3c/acpi/ec.asl new file mode 100644 index 0000000..ba1d4e4 --- /dev/null +++ b/src/mainboard/samsung/530u3c/acpi/ec.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) + /* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/530u3c/acpi/platform.asl b/src/mainboard/samsung/530u3c/acpi/platform.asl new file mode 100644 index 0000000..af17b0e --- /dev/null +++ b/src/mainboard/samsung/530u3c/acpi/platform.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/530u3c/acpi/superio.asl b/src/mainboard/samsung/530u3c/acpi/superio.asl new file mode 100644 index 0000000..1bc1628 --- /dev/null +++ b/src/mainboard/samsung/530u3c/acpi/superio.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/samsung/530u3c/acpi_tables.c b/src/mainboard/samsung/530u3c/acpi_tables.c new file mode 100644 index 0000000..8e411b2 --- /dev/null +++ b/src/mainboard/samsung/530u3c/acpi_tables.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/samsung/530u3c/board_info.txt b/src/mainboard/samsung/530u3c/board_info.txt new file mode 100644 index 0000000..b5e3dd5 --- /dev/null +++ b/src/mainboard/samsung/530u3c/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +Board URL: FIXME: Add a link to vendor's website. +ROM package: FIXME: Likely DIP-8, SOIC-8, SOIC-16, or WSON-8. +ROM protocol: SPI +Flashrom support: FIXME: Depends, please test! + diff --git a/src/mainboard/samsung/530u3c/devicetree.cb b/src/mainboard/samsung/530u3c/devicetree.cb new file mode 100644 index 0000000..d8baf5a --- /dev/null +++ b/src/mainboard/samsung/530u3c/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + + # FIXME: integrated panel settings + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0 on + subsystemid 0x144d 0xc0d7 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + + register "c2_latency" = "0x0065" + + register "gen1_dec" = "0x0000162c" + register "gen3_dec" = "0x000c0a01" + register "gen4_dec" = "0x000c06a1" + + register "gpi7_routing" = "2" + + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + + device pci 19.0 off end # Intel GbE MAC + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + + # FIXME: EC support? + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/samsung/530u3c/dsdt.asl b/src/mainboard/samsung/530u3c/dsdt.asl new file mode 100644 index 0000000..22064c9 --- /dev/null +++ b/src/mainboard/samsung/530u3c/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/samsung/530u3c/early_init.c b/src/mainboard/samsung/530u3c/early_init.c new file mode 100644 index 0000000..61c702f --- /dev/null +++ b/src/mainboard/samsung/530u3c/early_init.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 0, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. One DIMM is actually memory-down */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/samsung/530u3c/gma-mainboard.ads b/src/mainboard/samsung/530u3c/gma-mainboard.ads new file mode 100644 index 0000000..0dfe68b --- /dev/null +++ b/src/mainboard/samsung/530u3c/gma-mainboard.ads @@ -0,0 +1,24 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + LVDS); + +end GMA.Mainboard; diff --git a/src/mainboard/samsung/530u3c/gpio.c b/src/mainboard/samsung/530u3c/gpio.c new file mode 100644 index 0000000..33cca80 --- /dev/null +++ b/src/mainboard/samsung/530u3c/gpio.c @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/samsung/530u3c/hda_verb.c b/src/mainboard/samsung/530u3c/hda_verb.c new file mode 100644 index 0000000..674d89e --- /dev/null +++ b/src/mainboard/samsung/530u3c/hda_verb.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x144dc0d7, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x144dc0d7), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x90a70940), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/samsung/530u3c/mainboard.c b/src/mainboard/samsung/530u3c/mainboard.c new file mode 100644 index 0000000..bb9b839 --- /dev/null +++ b/src/mainboard/samsung/530u3c/mainboard.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x05, 0x00, 0x00, 0x01, 0x00, 0x00, 0x64, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x64, 0x0e, 0xd8, 0x00, 0x00, 0x1f, 0xce, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* b0 */ 0x17, 0xd4, 0x0e, 0xd8, 0x1c, 0xe8, 0x00, 0x72, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* c0 */ 0x2b, 0x00, 0x27, 0x2b, 0x00, 0x60, 0x00, 0x00, + 0x44, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x02, 0x74, 0x40, 0xe0, 0x00, 0x00, 0x0b, 0xc9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* e0 */ 0x34, 0x32, 0x30, 0x34, 0x44, 0x36, 0x31, 0x00, + 0x4c, 0x69, 0x50, 0x00, 0xff, 0xff, 0xff, 0xff, + /* f0 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write(i, dmp[i]); + + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix these values. Or just kill this completely. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04c138ed9db3228ad8f253138f04ea61a10d0a65 Gerrit-Change-Number: 40279 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/picasso: add get_soc_config to chip.h
by Felix Held (Code Review) 09 Apr '20

09 Apr '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40246 ) Change subject: soc/amd/picasso: add get_soc_config to chip.h ...................................................................... soc/amd/picasso: add get_soc_config to chip.h Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/chip.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40246/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 53c0329..be58a79 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -36,6 +36,8 @@ typedef struct soc_amd_picasso_config config_t; +const config_t *get_soc_config(void); + extern struct device_operations pci_domain_ops; #endif /* __PICASSO_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Gerrit-Change-Number: 40246 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.
by Srinidhi N Kaushik (Code Review) 08 Apr '20

08 Apr '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40026 to look at the new patch set (#8). Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. Update FSP headers for Tiger Lake platform generated based FSP version 2527. BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 3 files changed, 168 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40026/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/40026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Gerrit-Change-Number: 40026 Gerrit-PatchSet: 8 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: {xeon_sp, ocp/tiogapass}: remove unused FSP-style GPIO defs
by Angel Pons (Code Review) 08 Apr '20

08 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39453 ) Change subject: {xeon_sp, ocp/tiogapass}: remove unused FSP-style GPIO defs ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Gerrit-Change-Number: 39453 Gerrit-PatchSet: 23 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Apr 2020 21:20:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd: Use common functions to pass UMA information to ramstage
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36292 ) Change subject: soc/amd: Use common functions to pass UMA information to ramstage ...................................................................... soc/amd: Use common functions to pass UMA information to ramstage This removes the custom implementation using the BIOSRAM scratchpad space. Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/pi/Makefile.inc M src/soc/amd/common/block/pi/agesawrapper.c A src/soc/amd/common/block/pi/uma.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 10 files changed, 65 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36292/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882..03cea2e 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -139,45 +139,6 @@ /* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ #endif -#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE -/* biosram read/write - access registers at 0xfed80500 */ - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} -#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ - #if SUPPORTS_ACPIMMIO_CMOSRAM_BASE /* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 59ab9e5..879b9b9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -194,14 +194,6 @@ void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); -/* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); - /* Access ACPI registers at 0xfed80800 */ uint8_t acpi_read8(uint8_t reg); uint16_t acpi_read16(uint8_t reg); diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index 5afbb3e..41995f6 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -1,11 +1,13 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y) +romstage-y += uma.c romstage-y += agesawrapper.c romstage-y += def_callouts.c romstage-y += heapmanager.c romstage-y += image.c romstage-y += refcode_loader.c +ramstage-y += uma.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += amd_resume_final.c diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 022a8bc..77afeab 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -205,8 +205,8 @@ top = PostParams->MemConfig.Sub4GCacheTop; save_ram_top(top); - save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB); - save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB); + save_uma((u64)PostParams->MemConfig.UmaBase * 64 * KiB, + PostParams->MemConfig.UmaSize * 64 * KiB); print_init_post_settings(PostParams); diff --git a/src/soc/amd/common/block/pi/uma.c b/src/soc/amd/common/block/pi/uma.c new file mode 100644 index 0000000..5d46855 --- /dev/null +++ b/src/soc/amd/common/block/pi/uma.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <romstage_handoff.h> +#include <soc/southbridge.h> +#include <console/console.h> + + +struct save_uma { + uint64_t base; + uint32_t size; +}; + +void save_uma(uint64_t uma_base, uint32_t uma_size) +{ + struct save_uma save = { + .base = uma_base, + .size = uma_size + }; + if (save_romstage_info(&save, sizeof(save))) { + printk(BIOS_DEBUG, "Saving uma information failed!\n"); + return; + } +} + +void get_uma(uint64_t *uma_base, uint32_t *uma_size) +{ + struct save_uma save; + if (get_romstage_info(&save, sizeof(save))) { + printk(BIOS_ERR, "Getting saved uma information failed!\n"); + return; + } + *uma_base = save.base; + *uma_size = save.size; +} diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..f52c622 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -261,14 +261,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 00e7b0f..1562dc7 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -576,27 +576,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab..4504621 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -353,35 +353,19 @@ /** * @brief Save the UMA bize returned by AGESA * - * @param size = in bytes + * @param base, size = in bytes * * @return none */ -void save_uma_size(uint32_t size); +void save_uma(uint64_t uma_base, uint32_t uma_size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Get the UMA bize returned by AGESA * - * @param base = 64bit base address + * @param Pointer base, size = in bytes * * @return none */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); +void get_uma(uint64_t *uma_base, uint32_t *uma_size); /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..c6f7058 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -413,14 +413,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aa..96e587d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -36,6 +36,7 @@ #include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> +#include <romstage_handoff.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -648,27 +649,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Gerrit-Change-Number: 36292 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: lib/romstage_handoff: Add methods to pass on romstage information
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36291 ) Change subject: lib/romstage_handoff: Add methods to pass on romstage information ...................................................................... lib/romstage_handoff: Add methods to pass on romstage information Add 2 generic function that can be used to pass on information from romstage to ramstage. The implementation is such that the saving can be done even if cbmem is not set up initially. TODO: Does it need guarding because it needlessly increases .bss usage? Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/include/romstage_handoff.h M src/lib/romstage_handoff.c 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36291/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..89d9478 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -77,6 +77,7 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_ROMSTAGE_SAVE 0xa7d1f2f3 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index db998ec..bbb0869 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -21,4 +21,11 @@ /* Return 1 if resuming or 0 if not. */ int romstage_handoff_is_resume(void); +/* Returns 0 on success, 1 if the info was copied to a buffer to be migrated + to cbmem later on, < 0 on failure. */ +int save_romstage_info(void *info, size_t info_size); + +/* Return 0 on success, else < 0 on failure */ +int get_romstage_info(void *info, size_t info_size); + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 04ead0a..2f26194 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -77,3 +77,74 @@ return handoff->s3_resume; } + +static u8 save_buffer[256]; +static size_t used_buffer_size; +static int is_migrated; + +static void migrate_save_buffer(int is_recovery) +{ + if (used_buffer_size) + printk(BIOS_DEBUG, "Migrating the romstage save buffer to cbmem\n"); + is_migrated = 1; + save_romstage_info(save_buffer, used_buffer_size); +} + +ROMSTAGE_CBMEM_INIT_HOOK(migrate_save_buffer); + +int save_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + + printk(BIOS_SPEW, "Romstage save: saving %p, size %zu\n", + info, save_size); + + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + if (e != NULL) { + if (cbmem_entry_size(e) > save_size) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + cbmem_entry_remove(e); + } + + e = cbmem_entry_add(CBMEM_ID_ROMSTAGE_SAVE, save_size); + if (e == NULL && is_migrated) { + printk(BIOS_ERR, "Can't copy romstage save buffer to cbmem!\n"); + return -1; + } + + if (e != NULL) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + + /* Cbmem is not yet up, save it for later */ + printk(BIOS_SPEW, "Romstage save: cbmem not yet up, saving info buffer for later\n"); + if (sizeof(save_buffer) < save_size) { + printk(BIOS_ERR, "Romstage save: buffer too small!\n"); + return -1; + } + memcpy(save_buffer, info, save_size); + used_buffer_size = save_size; + return 1; +} + +int get_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + + if (e == NULL) { + printk(BIOS_ERR, "Can't find romstage save\n"); + return -1; + } + + if (save_size > cbmem_entry_size(e)) { + printk(BIOS_ERR, "Romstage save: requested size too large!\n"); + return -1; + } + + memcpy(info, cbmem_entry_start(e), save_size); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Gerrit-Change-Number: 36291 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: soc/amd/stoneyridge: replace get_soc_config with config_of_soc
by Felix Held (Code Review) 08 Apr '20

08 Apr '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40257 ) Change subject: soc/amd/stoneyridge: replace get_soc_config with config_of_soc ...................................................................... soc/amd/stoneyridge: replace get_soc_config with config_of_soc get_soc_config was a reimplementation of config_of_soc. Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/i2c.c 1 file changed, 5 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/40257/1 diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index bd8fd5b..c4d2986 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -5,6 +5,7 @@ #include <arch/acpi.h> #include <console/console.h> #include <delay.h> +#include <device/device.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> #include <soc/iomap.h> @@ -34,19 +35,6 @@ return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; } -static const struct soc_amd_stoneyridge_config *get_soc_config(void) -{ - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - return dev->chip_info; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_stoneyridge_config *config; @@ -54,9 +42,8 @@ if (bus >= ARRAY_SIZE(i2c_bus_address)) return NULL; - config = get_soc_config(); - if (config == NULL) - return NULL; + /* config is not NULL; it it was, config_of_soc calls die() internally */ + config = config_of_soc(); return &config->i2c[bus]; } @@ -97,10 +84,8 @@ size_t i; const struct soc_amd_stoneyridge_config *config; - config = get_soc_config(); - - if (config == NULL) - return; + /* config is not NULL; it it was, config_of_soc calls die() internally */ + config = config_of_soc(); for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/40257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Gerrit-Change-Number: 40257 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/ocp/tiogapass: use common GPIO config
by Maxim Polyakov (Code Review) 08 Apr '20

08 Apr '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39427 to look at the new patch set (#29). Change subject: mb/ocp/tiogapass: use common GPIO config ...................................................................... mb/ocp/tiogapass: use common GPIO config According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the common pad configuration from soc/intel/ common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions. This patch adds the GPIO configuration, which has the format required by the driver from common/gpio. The data for this was taken from the inteltool register dump with AMI firmware and converted to macros using intelp2m (pch-pads-parser) [3,4]. The following pads in the AMI firmware used SMI and SCI input кoute, but since currently SMM GPIO event handlers are absent in the code for xeon-sp, these pads will be configured as input PAD_CFG_GPI: PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_SMI_DRIVER(GPP_E0, NONE, DEEP, LEVEL, NONE), PAD_CFG_GPI_SMI_DRIVER(GPP_E1, NONE, DEEP, LEVEL, NONE). The above configuration should be restored back when the appropriate SMM handlers are added to the code. [1] https://review.coreboot.org/c/coreboot/+/39425 [2] https://review.coreboot.org/c/coreboot/+/39428 [3] https://review.coreboot.org/c/coreboot/+/35643 [4] https://github.com/maxpoliak/pch-pads-parser Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/Makefile.inc M src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/gpio.h M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c 5 files changed, 619 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 29 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/ocp/tiogapass: use common GPIO config [WIP]
by Maxim Polyakov (Code Review) 08 Apr '20

08 Apr '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39427 to look at the new patch set (#28). Change subject: mb/ocp/tiogapass: use common GPIO config [WIP] ...................................................................... mb/ocp/tiogapass: use common GPIO config [WIP] According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the common pad configuration from soc/intel/ common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions. This patch adds the GPIO configuration, which has the format required by the driver from common/gpio. The data for this was taken from the inteltool register dump with AMI firmware and converted to macros using intelp2m (pch-pads-parser) [3,4]. The following pads in the AMI firmware used SMI and SCI input кoute, but since currently SMM GPIO event handlers are absent in the code for xeon-sp, these pads will be configured as input PAD_CFG_GPI: PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_SMI_DRIVER(GPP_E0, NONE, DEEP, LEVEL, NONE), PAD_CFG_GPI_SMI_DRIVER(GPP_E1, NONE, DEEP, LEVEL, NONE). The above configuration should be restored back when the appropriate SMM handlers are added to the code. [1] https://review.coreboot.org/c/coreboot/+/39425 [2] https://review.coreboot.org/c/coreboot/+/39428 [3] https://review.coreboot.org/c/coreboot/+/35643 [4] https://github.com/maxpoliak/pch-pads-parser Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/Makefile.inc M src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/gpio.h M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c 5 files changed, 619 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 28 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2020