coreboot-gerrit March 2020

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Change in coreboot[master]: mb/google/volteer: remove PCIe WWAN support
by Nick Vaccaro (Code Review) 09 Mar '20

09 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39354 ) Change subject: mb/google/volteer: remove PCIe WWAN support ...................................................................... mb/google/volteer: remove PCIe WWAN support Remove support for PCIe WWAN to allow WWAN to enumerate as USB. BUG=b:146226689 TEST=none Change-Id: Ic71e88f7919757f6544a21b1df2e6d9a5a9ea8cc Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/… [View More]mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/39354/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ab50458..f2196df 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -50,7 +50,6 @@ register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" - register "sdcard_cd_gpio" = "GPP_E11" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" @@ -107,23 +106,6 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" - - # TCSS USB3 - register "TcssXhciEn" = "1" - # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" @@ -167,7 +149,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | Fingerprint MCU | + #| GSPI1 | Fingerprint MCU #| I2C0 | Audio | #| I2C1 | Touchscreen | #| I2C2 | WLAN, SAR0 | @@ -340,16 +322,7 @@ device spi 0 on end end end # GSPI0 0xA0AA - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" - device spi 0 on end - end # FPMCU - end # GSPI1 0xA0AB + device pci 1e.3 on end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic71e88f7919757f6544a21b1df2e6d9a5a9ea8cc Gerrit-Change-Number: 39354 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: trogdor: libpayload uart/serial driver support
by mturney mturney (Code Review) 09 Mar '20

09 Mar '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35960 ) Change subject: trogdor: libpayload uart/serial driver support ...................................................................... trogdor: libpayload uart/serial driver support Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M payloads/libpayload/Kconfig A payloads/libpayload/configs/config.trogdor M payloads/… [View More]libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/sc7180.c 4 files changed, 292 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/35960/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 97b970b..aa044bd 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -263,6 +263,16 @@ depends on SERIAL_CONSOLE default n +config SC7180_SERIAL_CONSOLE + bool "SC7180 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + +config CONSOLE_UART_ADDR + hex "Default I/O base for the serial port" + depends on SC7180_SERIAL_CONSOLE + default 0x00A88000 + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor new file mode 100644 index 0000000..0625ff5 --- /dev/null +++ b/payloads/libpayload/configs/config.trogdor @@ -0,0 +1,5 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_SC7180_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e7594..701434d 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c +libc-$(CONFIG_LP_SC7180_SERIAL_CONSOLE) += serial/sc7180.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c diff --git a/payloads/libpayload/drivers/serial/sc7180.c b/payloads/libpayload/drivers/serial/sc7180.c new file mode 100644 index 0000000..d104cd6 --- /dev/null +++ b/payloads/libpayload/drivers/serial/sc7180.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2010-2012, 2014, 2016, 2019, The Linux Foundation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <libpayload.h> + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +#include <sys/types.h> +#include <config.h> + +#define true 1 +#define false 0 +typedef uint8_t bool; + +#define REG_IN(base, offset) (*(volatile unsigned int *)(base + offset)) + +#define REG_OUT(base, offset, value) \ + (*(volatile unsigned int *)(base + offset) = value) + +/* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */ + +#define GENI4_CFG 0x0 +#define GENI4_IMAGE_REGS 0x100 +#define GENI4_DATA 0x600 +#define QUPV3_SE_DMA 0xC00 +#define GENI4_IMAGE 0x1000 +#define QUPV3_SEC 0x2000 + +/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ + +#define SE_HW_PARAM_0_REG (QUPV3_SE_DMA + 0x00000224) +#define SE_HW_PARAM_0_TX_FIFO_DEPTH_MASK 0x3f0000 +#define SE_HW_PARAM_0_TX_FIFO_DEPTH_SHIFT 0x10 + +#define SE_HW_PARAM_1_REG (QUPV3_SE_DMA + 0x00000228) +#define SE_HW_PARAM_1_RX_FIFO_DEPTH_MASK 0x3f0000 +#define SE_HW_PARAM_1_RX_FIFO_DEPTH_SHIFT 0x10 + +#define GENI_FW_REVISION_RO_REG (GENI4_CFG + 0x00000068) +#define GENI_FW_REVISION_RO_PROTOCOL_MASK 0x0000FF00 +#define GENI_FW_REVISION_RO_PROTOCOL_SHIFT 0x00000008 + +#define GENI_SER_M_CLK_CFG_REG (GENI4_CFG + 0x00000048) +#define GENI_SER_S_CLK_CFG_REG (GENI4_CFG + 0x0000004c) + +#define GENI_STATUS_REG (GENI4_CFG + 0x00000040) +#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1 +#define GENI_STATUS_S_GENI_CMD_ACTIVE_MASK 0x1000 + +#define GENI_TX_WATERMARK_REG (GENI4_DATA + 0x0000020c) +#define GENI_RX_WATERMARK_REG (GENI4_DATA + 0x00000210) +#define GENI_RX_RFR_WATERMARK_REG (GENI4_DATA + 0x00000214) + +#define UART_TX_WORD_LEN_REG (GENI4_IMAGE_REGS + 0x00000168) +#define UART_RX_WORD_LEN_REG (GENI4_IMAGE_REGS + 0x0000018c) + +#define UART_TX_PARITY_CFG_REG (GENI4_IMAGE_REGS + 0x000001a4) +#define UART_TX_TRANS_CFG_REG (GENI4_IMAGE_REGS + 0x0000015c) +#define UART_RX_PARITY_CFG_REG (GENI4_IMAGE_REGS + 0x000001a8) +#define UART_RX_TRANS_CFG_REG (GENI4_IMAGE_REGS + 0x00000180) + +#define UART_TX_STOP_BIT_LEN_REG (GENI4_IMAGE_REGS + 0x0000016c) + +#define UART_RX_STALE_CNT_REG (GENI4_IMAGE_REGS + 0x00000194) + +#define GENI_TX_PACKING_CFG0_REG (GENI4_IMAGE_REGS + 0x00000160) +#define GENI_TX_PACKING_CFG1_REG (GENI4_IMAGE_REGS + 0x00000164) +#define GENI_RX_PACKING_CFG0_REG (GENI4_IMAGE_REGS + 0x00000184) +#define GENI_RX_PACKING_CFG1_REG (GENI4_IMAGE_REGS + 0x00000188) + +#define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170) + +/* FIFO, STATUS REGISTERS AND MASKS */ + +#define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100) +#define GENI_RX_FIFOn_REG (GENI4_DATA + 0x00000180) + +#define GENI_TX_FIFO_STATUS_REG (GENI4_DATA + 0x00000200) +#define GENI_TX_FIFO_STATUS_TX_FIFO_WC_MASK 0xfffffff + +#define GENI_RX_FIFO_STATUS_REG (GENI4_DATA + 0x00000204) +#define GENI_RX_FIFO_STATUS_RX_LAST_VALID_BYTES_MASK 0x70000000 +#define GENI_RX_FIFO_STATUS_RX_LAST_VALID_BYTES_SHIFT 0x1c +#define GENI_RX_FIFO_STATUS_RX_FIFO_WC_MASK 0x1ffffff +#define GENI_RX_FIFO_STATUS_RX_FIFO_WC_SHIFT 0x0 + +/* MASTER/TX ENGINE REGISTERS */ + +#define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000) + +/* SECONDARY/RX ENGINE REGISTERS */ + +#define GENI_S_CMD0_REG (GENI4_DATA + 0x00000030) + +#define TX_WATERMARK_MARGIN 4 /* Represented in words */ +#define RX_WATERMARK_MARGIN 8 /* Represented in words */ +#define RX_RFR_WATERMARK_MARGIN 4 /* Represented in words */ + +#define PROTOCOL_UART 0x2 + +static struct console_input_driver consin = { + .next = 0, + .input_type = 0, +}; + +static struct console_output_driver consout = { + .next = 0, +}; + +static bool uart_initialized = false; + +static bool uart_qupv3_init(void); +static unsigned char uart_qupv3_rx_byte(void); +static void uart_qupv3_tx_byte(unsigned char data); + +uintptr_t uart_platform_base(int idx); + +static bool uart_qupv3_init(void) +{ + uintptr_t base = uart_platform_base(0); + unsigned int reg_value; + + reg_value = REG_IN(base, GENI_FW_REVISION_RO_REG); + reg_value &= GENI_FW_REVISION_RO_PROTOCOL_MASK; + reg_value >>= GENI_FW_REVISION_RO_PROTOCOL_SHIFT; + + if (reg_value != PROTOCOL_UART) + return false; + + /* + * If the RX (secondary) sequencer is already active, it means the core + * has been already initialized in the previous stage. Skip + * configuration + */ + if (REG_IN(base, GENI_STATUS_REG) & + GENI_STATUS_S_GENI_CMD_ACTIVE_MASK) { + uart_initialized = true; + return true; + } + + REG_OUT(base, GENI_TX_WATERMARK_REG, TX_WATERMARK_MARGIN); + + /* To get RX FIFO size */ + reg_value = REG_IN(base, SE_HW_PARAM_1_REG); + reg_value &= SE_HW_PARAM_1_RX_FIFO_DEPTH_MASK; + reg_value >>= SE_HW_PARAM_1_RX_FIFO_DEPTH_SHIFT; + + REG_OUT(base, GENI_RX_WATERMARK_REG, reg_value - RX_WATERMARK_MARGIN); + + REG_OUT(base, GENI_RX_RFR_WATERMARK_REG, + reg_value - RX_RFR_WATERMARK_MARGIN); + + REG_OUT(base, UART_TX_WORD_LEN_REG, 0x8); + REG_OUT(base, UART_RX_WORD_LEN_REG, 0x8); + + REG_OUT(base, UART_TX_PARITY_CFG_REG, 0x0); + REG_OUT(base, UART_TX_TRANS_CFG_REG, 0x2); + REG_OUT(base, UART_RX_PARITY_CFG_REG, 0x0); + REG_OUT(base, UART_RX_TRANS_CFG_REG, 0x0); + + REG_OUT(base, UART_TX_STOP_BIT_LEN_REG, 0x0); + + REG_OUT(base, UART_RX_STALE_CNT_REG, 0x16 * 10); + + REG_OUT(base, GENI_TX_PACKING_CFG0_REG, 0x4380E); + REG_OUT(base, GENI_TX_PACKING_CFG1_REG, 0xC3E0E); + REG_OUT(base, GENI_RX_PACKING_CFG0_REG, 0xF); + REG_OUT(base, GENI_RX_PACKING_CFG1_REG, 0x0); + + REG_OUT(base, GENI_S_CMD0_REG, 0x8000000); + + uart_initialized = true; + return true; +} + +unsigned char uart_qupv3_rx_byte(void) +{ + uintptr_t base = uart_platform_base(0); + unsigned char data; + + if (uart_initialized) { + if (REG_IN(base, GENI_RX_FIFO_STATUS_REG) & + GENI_RX_FIFO_STATUS_RX_FIFO_WC_MASK) { + data = (unsigned char)REG_IN(base, GENI_RX_FIFOn_REG) & + 0xFF; + return data; + } + } + return 0x0; +} + +void uart_qupv3_tx_byte(unsigned char data) +{ + uintptr_t base = uart_platform_base(0); + + if (uart_initialized == false) { + if (!uart_qupv3_init()) + return; + } + + while (REG_IN(base, GENI_STATUS_REG) & + GENI_STATUS_M_GENI_CMD_ACTIVE_MASK) + ; + + REG_OUT(base, UART_TX_TRANS_LEN_REG, 1); + REG_OUT(base, GENI_M_CMD0_REG, 0x08000000); + REG_OUT(base, GENI_TX_FIFOn_REG, (unsigned int)data); +} + +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_LP_CONSOLE_UART_ADDR; +} + +void serial_putchar(unsigned int data) +{ + if (data == 0xa) + uart_qupv3_tx_byte(0xd); + uart_qupv3_tx_byte(data); +} + +int serial_havechar(void) +{ + uintptr_t base = uart_platform_base(0); + + if (uart_initialized) { + if (REG_IN(base, GENI_RX_FIFO_STATUS_REG) & + GENI_RX_FIFO_STATUS_RX_FIFO_WC_MASK) { + return 1; + } + } + return 0; +} + +int serial_getchar(void) +{ + return uart_qupv3_rx_byte(); +} + +void serial_console_init(void) +{ + uart_qupv3_init(); + + consout.putchar = &serial_putchar; + console_add_output_driver(&consout); + + consin.havekey = &serial_havechar; + consin.getchar = &serial_getchar; + console_add_input_driver(&consin); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Gerrit-Change-Number: 35960 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
by Patrick Georgi (Code Review) 09 Mar '20

09 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/30360/17/Documentation/mainboard/l… File Documentation/mainboard/libretrend/lt1000.jpg: PS17: `jpegtran -optimize -progressive` cuts this file to 79K with no loss in fidelity, … [View More]

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Change in coreboot[master]: mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree
by Angel Pons (Code Review) 09 Mar '20

09 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39384 ) Change subject: mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree ...................................................................... mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to clobber the registers with garbage in ramstage. Tested, my Asus P5G41T-M LX … [View More]

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Change in coreboot[master]: mb/google/dedede: Add PCIe Root Port Configuration
by Karthik Ramasubramanian (Code Review) 09 Mar '20

09 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39166 ) Change subject: mb/google/dedede: Add PCIe Root Port Configuration ...................................................................... mb/google/dedede: Add PCIe Root Port Configuration Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: … [View More]

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Change in coreboot[master]: mb/google/dedede: Configure EDP_HPD GPIO
by Karthik Ramasubramanian (Code Review) 09 Mar '20

09 Mar '20

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39347 to review the following change. Change subject: mb/google/dedede: Configure EDP_HPD GPIO ...................................................................... mb/google/dedede: Configure EDP_HPD GPIO This enables display for use by payload TEST=Build and boot the mainboard. Ensure that the screens displayed by payload are visible. Signed-off-by: … [View More]

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Change in coreboot[master]: mb/google/dedede: Configure EC <-> AP GPIOs
by Karthik Ramasubramanian (Code Review) 09 Mar '20

09 Mar '20

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39325 to review the following change. Change subject: mb/google/dedede: Configure EC <-> AP GPIOs ...................................................................... mb/google/dedede: Configure EC <-> AP GPIOs BUG=b:150869661 TEST=Build and boot the mainboard. Trigger apreset from EC console. Trigger reboot from AP console. Signed-off-by: … [View More]

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Change in coreboot[master]: mb/google/dedede: Add GPIO list
by Karthik Ramasubramanian (Code Review) 09 Mar '20

09 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39114 ) Change subject: mb/google/dedede: Add GPIO list ...................................................................... mb/google/dedede: Add GPIO list Leave all the GPIOs as not connected so that they can be configured depending on the use-case. BUG=None TEST=Build the mainboard Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: … [View More]I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 290 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39114/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index fa975e7..0e2a168 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,17 +21,63 @@ /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* A7 : SMB_CLK */ + PAD_NC(GPP_A7, NONE), + /* A8 : SMB_DATA */ + PAD_NC(GPP_A8, NONE), + /* A9 : SMB_ALERT_N */ + PAD_NC(GPP_A9, NONE), + /* A10 : WWAN_EN */ + PAD_NC(GPP_A10, NONE), + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), /* A12 : USB_OC1_N */ PAD_NC(GPP_A12, NONE), /* A13 : USB_OC2_N */ PAD_NC(GPP_A13, NONE), /* A14 : USB_OC3_N */ PAD_NC(GPP_A14, NONE), + /* A15 : GPP_A15 */ + PAD_NC(GPP_A15, NONE), + /* A16 : EC_AP_USB_C0_HPD */ + PAD_NC(GPP_A16, NONE), + /* A17 : EDP_HPD */ + PAD_NC(GPP_A17, NONE), /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), + /* A19 : PCHHOT_N */ + PAD_NC(GPP_A19, NONE), + /* B0 : VCCIN_AUX_VID0 */ + PAD_NC(GPP_B0, NONE), + /* B1 : VCCIN_AUX_VID1 */ + PAD_NC(GPP_B1, NONE), + /* B2 : PROCHOT_ODL */ + PAD_NC(GPP_B2, NONE), + /* B3 : TRACKPAD_INT_ODL */ + PAD_NC(GPP_B3, NONE), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B5 : PCIE_CLKREQ0_N */ + PAD_NC(GPP_B5, NONE), + /* B6 : PCIE_CLKREQ1_N */ + PAD_NC(GPP_B6, NONE), + /* B7 : PCIE_CLKREQ2_N */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_CLKREQ3_N */ + PAD_NC(GPP_B8, NONE), + /* B9 : PCIE_CLKREQ4_N */ + PAD_NC(GPP_B9, NONE), + /* B10 : PCIE_CLKREQ5_N */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT_N */ + PAD_NC(GPP_B11, NONE), + /* B12 : AP_SLP_S0_L */ + PAD_NC(GPP_B12, NONE), + /* B13 : PLT_RST_L */ + PAD_NC(GPP_B13, NONE), + /* B14 : SPKR/GSPI0_CS1_N */ + PAD_NC(GPP_B14, NONE), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -40,7 +86,49 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0_N */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI */ + PAD_NC(GPP_B22, NONE), + /* B23 : EC_AP_USB_C1_HDMI_HPD */ + PAD_NC(GPP_B23, NONE), + /* C0 : RAM_STRAP_0 */ + PAD_NC(GPP_C0, NONE), + /* C1 : GPP_C1 */ + PAD_NC(GPP_C1, NONE), + /* C2 : GPP_C2 */ + PAD_NC(GPP_C2, NONE), + /* C3 : RAM_STRAP_1 */ + PAD_NC(GPP_C3, NONE), + /* C4 : RAM_STRAP_2 */ + PAD_NC(GPP_C4, NONE), + /* C5 : RAM_STRAP_3 */ + PAD_NC(GPP_C5, NONE), + /* C6 : PMC_SUSWARN_N */ + PAD_NC(GPP_C6, NONE), + /* C7 : PMC_SUSACK_N */ + PAD_NC(GPP_C7, NONE), + /* C8 : GPP_C8/UART0_RXD */ + PAD_NC(GPP_C8, NONE), + /* C9 : GPP_C9/UART0_TXD */ + PAD_NC(GPP_C9, NONE), + /* C10 : GPP_C10/UART0_RTSB */ + PAD_NC(GPP_C10, NONE), + /* C11 : AP_WP_OD */ + PAD_NC(GPP_C11, NONE), + /* C12 : AP_PEN_DET_ODL */ + PAD_NC(GPP_C12, NONE), + /* C13 : GPP_C13/UART1_TXD */ + PAD_NC(GPP_C13, NONE), + /* C14 : EC_IN_RW_OD */ + PAD_NC(GPP_C14, NONE), + /* C15 : EC_AP_MKBP_INT_L */ + PAD_NC(GPP_C15, NONE), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ @@ -58,6 +146,106 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* D0 : WWAN_HOST_WAKE */ + PAD_NC(GPP_D0, NONE), + /* D1 : WLAN_PERST_L */ + PAD_NC(GPP_D1, NONE), + /* D2 : WLAN_INT_L */ + PAD_NC(GPP_D2, NONE), + /* D3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_D3, NONE), + /* D4 : TOUCH_INT_ODL */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D7 : EMR_INT_ODL */ + PAD_NC(GPP_D7, NONE), + /* D8 : GPP_D8/GSPI2_CS0B/UART0A_RXD */ + PAD_NC(GPP_D8, NONE), + /* D9 : GPP_D9/GSPI2_CLK/UART0A_TXD */ + PAD_NC(GPP_D9, NONE), + /* D10 : GPP_D10/GSPI2_MISO/UART0A_RTSB */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11/GSPI2_MOSI/UART0A_CTSB */ + PAD_NC(GPP_D11, NONE), + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D16 : HP_INT_ODL */ + PAD_NC(GPP_D16, NONE), + /* D17 : EN_SPK */ + PAD_NC(GPP_D17, NONE), + /* D18 : I2S_MCLK */ + PAD_NC(GPP_D18, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_NC(GPP_D22, NONE), + /* D23 : AP_I2C_SUB_SCL */ + PAD_NC(GPP_D23, NONE), + + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E1 : EMR_RESET_L */ + PAD_NC(GPP_E1, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3/SATA_0_DEVSLP */ + PAD_NC(GPP_E3, NONE), + /* E4 : IMGCLKOUT_2 */ + PAD_NC(GPP_E4, NONE), + /* E5 : AP_SUB_IO_2 */ + PAD_NC(GPP_E5, NONE), + /* E6 : GPP_E6/IMGCLKOUT_3 */ + PAD_NC(GPP_E6, NONE), + /* E7 : GPP_E7/SATA_1_DEVSLP */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8/SATA_0_GP */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9/SML_CLK0/SATA_1_GP */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10/SML_DATA0 */ + PAD_NC(GPP_E10, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_NC(GPP_E11, NONE), + /* E12 : GPP_E12/IMGCLKOUT_4 */ + PAD_NC(GPP_E12, NONE), + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_NC(GPP_E13, NONE), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_NC(GPP_E14, NONE), + /* E15 : GPP_E15/DDI1_DDC_SCL */ + PAD_NC(GPP_E15, NONE), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_NC(GPP_E16, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + /* E18 : HDMI_DDC_SDA */ + PAD_NC(GPP_E18, NONE), + /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ + PAD_NC(GPP_E19, NONE), + /* E20 : CNV_BRI_DT_R */ + PAD_NC(GPP_E20, NONE), + /* E21 : CNV_BRI_RSP */ + PAD_NC(GPP_E21, NONE), + /* E22 : CNV_RGI_DT_R */ + PAD_NC(GPP_E22, NONE), + /* E23 : CNV_RGI_RSP */ + PAD_NC(GPP_E23, NONE), + + /* F4 : CNV_RF_RST_L */ + PAD_NC(GPP_F4, NONE), /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -83,6 +271,31 @@ /* F18 : EMMC_RESET_N */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H0 : WWAN_PERST */ + PAD_NC(GPP_H0, NONE), + /* H1 : EN_PP3300_SD_U */ + PAD_NC(GPP_H1, NONE), + /* H2 : CNV_CLKREQ0 */ + PAD_NC(GPP_H2, NONE), + /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ + PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ @@ -95,6 +308,83 @@ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : CPU_C10_GATE_L */ + PAD_NC(GPP_H10, NONE), + /* H11 : GPP_H11/AV_I2S2_SCLK */ + PAD_NC(GPP_H11, NONE), + /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13/AVS_I2S2_TXD/MODEM_CLKREQ */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14/AVS_I2S2_RXD */ + PAD_NC(GPP_H14, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + /* H16 : AP_SUB_IO_L */ + PAD_NC(GPP_H16, NONE), + /* H17 : WWAN_RST_L */ + PAD_NC(GPP_H17, NONE), + /* H18 : WLAN_DISABLE_L */ + PAD_NC(GPP_H18, NONE), + /* H19 : BT_DISABLE_L */ + PAD_NC(GPP_H19, NONE), + + /* R0 : I2S_HP_BCLK */ + PAD_NC(GPP_R0, NONE), + /* R1 : I2S_HP_LRCK */ + PAD_NC(GPP_R1, NONE), + /* R2 : I2S_HP_AUDIO */ + PAD_NC(GPP_R2, NONE), + /* R3 : I2S_HP_MIC */ + PAD_NC(GPP_R3, NONE), + /* R4 : GPP_R04/HDA_RST_N */ + PAD_NC(GPP_R4, NONE), + /* R5 : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S0 : RAM_STRAP_4 */ + PAD_NC(GPP_S0, NONE), + /* S1 : RSVD_STRAP */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S4 : GPP_S04/SNDW1_CLK */ + PAD_NC(GPP_S4, NONE), + /* S5 : GPP_S05/SNDW1_DATA */ + PAD_NC(GPP_S5, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), + + /* GPD0 : AP_BATLOW_L */ + PAD_NC(GPD0, NONE), + /* GPD1 : GPP_GPD1/ACPRESENT */ + PAD_NC(GPD1, NONE), + /* GPD2 : EC_AP_WAKE_ODL */ + PAD_NC(GPD2, NONE), + /* GPD3 : EC_AP_PWR_BTN_ODL */ + PAD_NC(GPD3, NONE), + /* GPD4 : AP_SLP_S3_L */ + PAD_NC(GPD4, NONE), + /* GPD5 : AP_SLP_S4_L */ + PAD_NC(GPD5, NONE), + /* GPD6 : AP_SLP_A_L */ + PAD_NC(GPD6, NONE), + /* GPD7 : GPP_GPD7 */ + PAD_NC(GPD7, NONE), + /* GPD8 : WLAN_SUSCLK */ + PAD_NC(GPD8, NONE), + /* GPD9 : AP_SLP_WLAN_L */ + PAD_NC(GPD9, NONE), + /* GPD10 : AP_SPL_S5_L */ + PAD_NC(GPD10, NONE), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 Gerrit-Change-Number: 39114 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange [View Less]

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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct temperature threshold for PCH Therm...
by Sumeet R Pawnikar (Code Review) 09 Mar '20

09 Mar '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33129 Change subject: soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor ...................................................................... soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal … [View More]shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFA. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/iomap.h A src/soc/intel/cannonlake/include/soc/thermal.h A src/soc/intel/cannonlake/thermal.c 6 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33129/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1328944..03faa3c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -53,6 +53,7 @@ ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c +ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..39f808b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,9 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* PCH Trip Temperature */ + uint8_t pch_trip_temp; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15b..d277658 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -32,6 +32,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/systemagent.h> +#include <soc/thermal.h> #include <stdlib.h> #include "chip.h" @@ -63,6 +64,16 @@ uint8_t reg8; tco_lockdown(); + + /* + * Set low maximum temp value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. + */ + pch_thermal_configuration(); + /* * Disable ACPI PM timer based on dt policy * diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 100bd11..488d938 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -76,6 +76,8 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 +#define THERMAL_BASE_ADDRESS 0xfe600000 + #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 /* diff --git a/src/soc/intel/cannonlake/include/soc/thermal.h b/src/soc/intel/cannonlake/include/soc/thermal.h new file mode 100644 index 0000000..1f4085c --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/thermal.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_THERMAL_H_ +#define _SOC_THERMAL_H_ + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void); + +#endif diff --git a/src/soc/intel/cannonlake/thermal.c b/src/soc/intel/cannonlake/thermal.c new file mode 100644 index 0000000..9d62843 --- /dev/null +++ b/src/soc/intel/cannonlake/thermal.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/thermal.h> + +#include "chip.h" + +#define MAX_TRIP_TEMP 205 +#define DEFAULT_TRIP_TEMP 50 + +static void *pch_thermal_get_bar(struct device *dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + /* + * Bits [31:12] are the base address as per EDS for Thermal Device, + * Don't care about [11:0] bits + */ + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +/* PCH Low Temp Threshold (LTT) */ +static uint16_t pch_get_ltt_value(struct device *dev) +{ + static struct soc_intel_skylake_config *config; + uint16_t ltt_value; + uint16_t trip_temp = DEFAULT_TRIP_TEMP; + + config = dev->chip_info; + + if (config->pch_trip_temp) + trip_temp = config->pch_trip_temp; + + if (trip_temp > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + ltt_value = (trip_temp + 50) * 2; + + return ltt_value; +} + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uint16_t reg16; + struct device *dev = PCH_DEV_THERMAL; + if (!dev) { + printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n"); + return; + } + void *thermalbar = pch_thermal_get_bar(dev); + + /* Use default pre-ram bar */ + if (!thermalbar) { + pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS); + thermalbar = (void *)THERMAL_BASE_ADDRESS; + } + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT); + reg16 &= ~0x1ff; + /* Low Temp Threshold (LTT) */ + reg16 |= pch_get_ltt_value(dev); + write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Gerrit-Change-Number: 33129 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange [View Less]

10 85

Change in coreboot[master]: mb/google/volteer: Enable FPMCU on volteer
by Nick Vaccaro (Code Review) 09 Mar '20

09 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39358 ) Change subject: mb/google/volteer: Enable FPMCU on volteer ...................................................................... mb/google/volteer: Enable FPMCU on volteer BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, … [View More]

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coreboot-gerrit March 2020