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Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling for mushu
by Amanda Hwang (Code Review) 03 Feb '20

03 Feb '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38340 ) Change subject: hatch: Fix FPMCU pwr/rst gpio handling for mushu ...................................................................... hatch: Fix FPMCU pwr/rst gpio handling for mushu Hatch moves power/reset pin control of FPMCU to var/board/ramstage. So add this change in mushu. BUG=b:147274277 TEST=emerge-hatch coreboot Change-Id: I10c9b8f673618ddaddfeed86705f3c838e7021fd Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 3 files changed, 62 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38340/1 diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..0e7863d 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -21,3 +21,4 @@ ramstage-y += gpio.c bootblock-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e1594..18cbc09 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -57,8 +57,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -88,3 +86,32 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10c9b8f673618ddaddfeed86705f3c838e7021fd Gerrit-Change-Number: 38340 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] asus/p2b-d: Fold into asus/p2b-ds as a variant
by Keith Hui (Code Review) 02 Feb '20

02 Feb '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37457 ) Change subject: [RFC] asus/p2b-d: Fold into asus/p2b-ds as a variant ...................................................................... [RFC] asus/p2b-d: Fold into asus/p2b-ds as a variant The two boards already share the exact same romstage.c and only small differences exist in mptable, irq table, devicetree. Share what they could and put what cannot be into subfolders of asus/p2b-ds. Lines split and spaces added to pass lint. The structure is based on google/auron but isn't a full blown board variant setup because the overhead isn't worth it. Build tested. Comments welcome. Change-Id: Ibcb2e80c968c65523ff40cbd9c19fe15e9527e0d Signed-off-by: Keith Hui <buurin(a)gmail.com> --- D src/mainboard/asus/p2b-d/Kconfig D src/mainboard/asus/p2b-d/Kconfig.name D src/mainboard/asus/p2b-d/board_info.txt D src/mainboard/asus/p2b-d/irq_tables.c D src/mainboard/asus/p2b-d/mptable.c D src/mainboard/asus/p2b-d/romstage.c M src/mainboard/asus/p2b-ds/Kconfig M src/mainboard/asus/p2b-ds/Kconfig.name M src/mainboard/asus/p2b-ds/irq_tables.c M src/mainboard/asus/p2b-ds/mptable.c R src/mainboard/asus/p2b-ds/p2b-d/devicetree.cb A src/mainboard/asus/p2b-ds/p2b-d/irq_tables.h R src/mainboard/asus/p2b-ds/p2b-ds/devicetree.cb A src/mainboard/asus/p2b-ds/p2b-ds/irq_tables.h 14 files changed, 121 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/37457/1 diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig deleted file mode 100644 index 8db9b7a..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_D - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-d" - -config MAINBOARD_PART_NUMBER - string - default "P2B-D" - -config IRQ_SLOT_COUNT - int - default 6 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_D diff --git a/src/mainboard/asus/p2b-d/Kconfig.name b/src/mainboard/asus/p2b-d/Kconfig.name deleted file mode 100644 index 23e7808..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_D - bool "P2B-D" diff --git a/src/mainboard/asus/p2b-d/board_info.txt b/src/mainboard/asus/p2b-d/board_info.txt deleted file mode 100644 index fdee74e..0000000 --- a/src/mainboard/asus/p2b-d/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c deleted file mode 100644 index cb72254..0000000 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x54, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c deleted file mode 100644 index fde1281..0000000 --- a/src/mainboard/asus/p2b-d/mptable.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - int ioapic_id, ioapic_ver, isa_bus; - struct mp_config_table *mc; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - ioapic_id = 2; - ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); - - /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */ - - /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - /* Compute the checksums. */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c deleted file mode 100644 index 7fad06b..0000000 --- a/src/mainboard/asus/p2b-d/romstage.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 8b55174..d7b77db 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -12,10 +12,9 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B_DS -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_ASUS_BASEBOARD_P2B_DS + def_bool n select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB @@ -27,20 +26,33 @@ select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM +if BOARD_ASUS_BASEBOARD_P2B_DS + config MAINBOARD_DIR string default "asus/p2b-ds" +config VARIANT_DIR + string + default "p2b-d" if BOARD_ASUS_P2B_D + default "p2b-ds" if BOARD_ASUS_P2B_DS + config MAINBOARD_PART_NUMBER string - default "P2B-DS" + default "P2B-D" if BOARD_ASUS_P2B_D + default "P2B-DS" if BOARD_ASUS_P2B_DS + +config DEVICETREE + string + default "$(CONFIG_VARIANT_DIR)/devicetree.cb" config IRQ_SLOT_COUNT int - default 7 + default 6 if BOARD_ASUS_P2B_D + default 7 if BOARD_ASUS_P2B_DS config MAX_CPUS int default 2 -endif # BOARD_ASUS_P2B_DS +endif # BOARD_ASUS_BASEBOARD_P2B_DS diff --git a/src/mainboard/asus/p2b-ds/Kconfig.name b/src/mainboard/asus/p2b-ds/Kconfig.name index 0335139..740d4e5 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig.name +++ b/src/mainboard/asus/p2b-ds/Kconfig.name @@ -1,2 +1,7 @@ +config BOARD_ASUS_P2B_D + bool "P2B-D" + select BOARD_ASUS_BASEBOARD_P2B_DS + config BOARD_ASUS_P2B_DS bool "P2B-DS" + select BOARD_ASUS_BASEBOARD_P2B_DS diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index 2240b44..0966a22 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -16,29 +16,12 @@ #include <arch/pirq_routing.h> -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x04 << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x36, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, - } -}; +#if CONFIG(BOARD_ASUS_P2B_DS) +#include "p2b-ds/irq_tables.h" +#endif +#if CONFIG(BOARD_ASUS_P2B_D) +#include "p2b-d/irq_tables.h" +#endif unsigned long write_pirq_routing_table(unsigned long addr) { diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index 4e085b1..aeeaa48 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -41,10 +41,12 @@ /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); + if (CONFIG(BOARD_ASUS_P2B_DS)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | + MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, 0x1); + mptable_lintsrc(mc, isa_bus); /* Compute the checksums. */ return mptable_finalize(mc); diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b-ds/p2b-d/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-d/devicetree.cb rename to src/mainboard/asus/p2b-ds/p2b-d/devicetree.cb diff --git a/src/mainboard/asus/p2b-ds/p2b-d/irq_tables.h b/src/mainboard/asus/p2b-ds/p2b-d/irq_tables.h new file mode 100644 index 0000000..0cf6fc1 --- /dev/null +++ b/src/mainboard/asus/p2b-ds/p2b-d/irq_tables.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x54, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, + {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x1, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, + {0x63, 0x1eb8}, {0x60, 0x1eb8} }, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, + {0x60, 0x1eb8}, {0x61, 0x1eb8} }, 0x3, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, + {0x61, 0x1eb8}, {0x62, 0x1eb8} }, 0x4, 0x0}, + {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x0, 0x0}, + } +}; diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b-ds/p2b-ds/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ds/devicetree.cb rename to src/mainboard/asus/p2b-ds/p2b-ds/devicetree.cb diff --git a/src/mainboard/asus/p2b-ds/p2b-ds/irq_tables.h b/src/mainboard/asus/p2b-ds/p2b-ds/irq_tables.h new file mode 100644 index 0000000..ee40690 --- /dev/null +++ b/src/mainboard/asus/p2b-ds/p2b-ds/irq_tables.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x36, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, + {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x1, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, + {0x63, 0x1eb8}, {0x60, 0x1eb8} }, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, + {0x60, 0x1eb8}, {0x61, 0x1eb8} }, 0x3, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, + {0x61, 0x1eb8}, {0x62, 0x1eb8} }, 0x4, 0x0}, + {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, + {0x62, 0x1eb8}, {0x63, 0x1eb8} }, 0x0, 0x0}, + {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, + {0x61, 0x1eb8}, {0x62, 0x1eb8} }, 0x0, 0x0}, + } +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/37457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb2e80c968c65523ff40cbd9c19fe15e9527e0d Gerrit-Change-Number: 37457 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS setting
by Wonkyu Kim (Code Review) 01 Feb '20

01 Feb '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38624 ) Change subject: soc/intel/tigerlake: Configure TCSS setting ...................................................................... soc/intel/tigerlake: Configure TCSS setting Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681 BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3f980d1..a4542fb 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -218,6 +218,34 @@ FORCE_ENABLE, } CnviBtAudioOffload; + /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + + /* + * Tcss Aux Orienation override + * bits 0, 2, ... 10 control override for port + * value: 1 - controlled by iom, 0 - controled by retimer + * bits 1, 3, ... 11 orientation override for port + * value: 0 - not swapped , 1 - swapped + * Reference: IOM_TYPEC_SW_CONFIGURATION_3 in TGL EDS#575681 + */ + uint8_t TcssAuxOri; + + /* + * Tcss HSL Orientation override + * bits 0, 2, ... 10 control override for port + * bits 1, 3, ... 11 orientation override for port + * Reference: IOM_TYPEC_SW_CONFIGURATION_4 in TGL EDS#575681 + */ + uint8_t TcssHslOri; + + /* + * TypeC port GPIO setting + * GPIO pin number for Type C Aux orienation setting when it's controlled by iom + */ + uint32_t IomTypeCPortPadCfg[8]; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..085689c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,12 @@ sizeof(params->SataPortsDevSlp)); } + /* Tcss */ + params->TcssHslOri = config->TcssHslOri; + params->TcssAuxOri = config->TcssAuxOri; + memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, + sizeof(config->IomTypeCPortPadCfg)); + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 6ed3dcd..88c790b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -102,6 +102,10 @@ m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + /* Tcss */ + m_cfg->TcssXhciEn = config->TcssXhciEn; + m_cfg->TcssXdciEn = config->TcssXdciEn; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

7 32

Change in coreboot[master]: ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPS
by Tim Wawrzynczak (Code Review) 01 Feb '20

01 Feb '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38539 ) Change subject: ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPS ...................................................................... ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPS The new host command provides these static capabilities of each USB-PD port: 1) Port number 2) Power role: source, sink, dual 3) Try-power role: none, sink, source 4) Data role: dfp, ufp, dual 5) Port location: these come from power_manager BUG=b:146506369 BRANCH=none TEST=compiles Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/38539/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 86bd4f6..7b5a067 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5853,6 +5853,74 @@ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 /*****************************************************************************/ +/* Get PD port capabilities + * + * Returns the following static *capabilities* of the given port: + * 1) Power role: source, sink, or dual. It is not anticipated that + * future CrOS devices would ever be only a source, so the options are + * sink or dual. + * 2) Try-power role: source, sink, or none (practically speaking, I don't + * believe any CrOS device would support Try.SNK, so this would be source + * or none). + * 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual + * for CrOS devices. + */ +#define EC_CMD_GET_PD_PORT_CAPS 0x0128 + +enum ec_pd_power_role_caps { + EC_PD_POWER_ROLE_SOURCE = 0, + EC_PD_POWER_ROLE_SINK = 1, + EC_PD_POWER_ROLE_DUAL = 2, +}; + +enum ec_pd_try_power_role_caps { + EC_PD_TRY_POWER_ROLE_NONE = 0, + EC_PD_TRY_POWER_ROLE_SINK = 1, + EC_PD_TRY_POWER_ROLE_SOURCE = 2, +}; + +enum ec_pd_data_role_caps { + EC_PD_DATA_ROLE_DFP = 0, + EC_PD_DATA_ROLE_UFP = 1, + EC_PD_DATA_ROLE_DUAL = 2, +}; + +/* From: power_manager/power_supply_properties.proto */ +enum ec_pd_port_location { + /* The location of the port is unknown, or there's only one port. */ + EC_PD_PORT_LOCATION_UNKNOWN = 0, + + /* + * Various positions on the device. The first word describes the side of + * the device where the port is located while the second clarifies the + * position. For example, LEFT_BACK means the farthest-back port on the + * left side, while BACK_LEFT means the leftmost port on the back of the + * device. + */ + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, +}; + +struct ec_params_get_pd_port_caps { + uint8_t port; /* Which port to interrogate */ +} __ec_align1; + +struct ec_response_get_pd_port_caps { + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ +} __ec_align1; + +/*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ /*****************************************************************************/ -- To view, visit https://review.coreboot.org/c/coreboot/+/38539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Gerrit-Change-Number: 38539 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: hatch/mushu: Fix FPMCU pwr/rst gpio handling
by Craig Hesling (Code Review) 01 Feb '20

01 Feb '20

Craig Hesling has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38623 ) Change subject: hatch/mushu: Fix FPMCU pwr/rst gpio handling ...................................................................... hatch/mushu: Fix FPMCU pwr/rst gpio handling This simply makes these variants consistent with other hatch variants. This follows https://review.coreboot.org/c/coreboot/+/37459 . BUG=b/148457345 TEST=None Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling <hesling(a)chromium.org> --- M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/ramstage.c M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 6 files changed, 70 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38623/1 diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 -ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 862b28f..2c4fa50 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -55,8 +55,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c new file mode 100644 index 0000000..8e84308 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..4bf640a 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 -ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e1594..1453cab 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -57,8 +57,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..8e84308 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Gerrit-Change-Number: 38623 Gerrit-PatchSet: 1 Gerrit-Owner: Craig Hesling <hesling(a)chromium.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: mb/google/hatch: Configure gpio setting for dGPU power mode BOMACO
by Amanda Hwang (Code Review) 01 Feb '20

01 Feb '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38210 ) Change subject: mb/google/hatch: Configure gpio setting for dGPU power mode BOMACO ...................................................................... mb/google/hatch: Configure gpio setting for dGPU power mode BOMACO Configure GPP_H22 as output ping for BOMSCO mode enabled. Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/mushu/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38210/1 diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e1594..a60662a 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -41,6 +41,8 @@ PAD_CFG_GPO(GPP_C15, 1, DEEP), /* H3 : SPKR_PA_EN */ PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H22 : BOMACO_EN */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), }; const struct pad_config *override_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/38210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67 Gerrit-Change-Number: 38210 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: mb/google/drallion: Set cpu id to EC
by EricR Lai (Code Review) 01 Feb '20

01 Feb '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38566 ) Change subject: mb/google/drallion: Set cpu id to EC ...................................................................... mb/google/drallion: Set cpu id to EC Set CPU ID and cores to EC then EC will according to different CPU to set different power table. BUG=b:148126144 BRANCH=None TEST=check EC can get correct CPU id and cores. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a --- M src/mainboard/google/drallion/ramstage.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38566/1 diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 3855045..daee09d 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -14,14 +14,19 @@ */ #include <arch/acpi.h> +#include <arch/cpu.h> #include <boardid.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <drivers/vpd/vpd.h> +#include <ec/google/wilco/commands.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> + #define VPD_KEY_SYSTEM_SERIAL "serial_number" #define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" #define VPD_SERIAL_LEN 64 @@ -59,6 +64,20 @@ } } +/* set cpu id to EC, default cores is 4 */ +static int set_cpu_id(void) +{ + uint16_t mch_id = 0; + uint8_t cpu_cores = 4; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_2_2) + cpu_cores = 2; + + return wilco_ec_set_cpuid(cpu_get_cpuid(), cpu_cores, 0); +} + static void mainboard_init(void *chip_info) { const struct pad_config *gpio_table; @@ -66,6 +85,8 @@ gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); + if (set_cpu_id()) + printk(BIOS_ERR, "wilco set cpu id failed\n"); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/38566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a Gerrit-Change-Number: 38566 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37944 ) Change subject: mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method ...................................................................... mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/platform.asl 2 files changed, 2 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37944/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index bcd6de6..dba7809 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -71,62 +71,6 @@ /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 2371eab..a8296cc 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -46,62 +46,6 @@ /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Gerrit-Change-Number: 37944 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: sb/intel/common/acpi: Add more Windows versions
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37943 ) Change subject: sb/intel/common/acpi: Add more Windows versions ...................................................................... sb/intel/common/acpi: Add more Windows versions Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/common/acpi/platform.asl 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37943/1 diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index 03cb625..9cd41eb 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -79,6 +79,14 @@ Store (2001, OSYS) } + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + If (_OSI("Windows 2001 SP2")) { Store (2002, OSYS) } @@ -86,5 +94,21 @@ If (_OSI("Windows 2006")) { Store (2006, OSYS) } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Gerrit-Change-Number: 37943 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
by Patrick Georgi (Code Review) 01 Feb '20

01 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems ...................................................................... util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 479 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Alexander Couzens: Looks good to me, approved diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..9610fd6 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1070,6 +1070,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..4ec79c4 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2157,6 +2157,477 @@ &cannonlake_pch_h_community_4, }; +/* Ice Lake-LP */ +static const char *const icelake_pch_h_group_g_names[] = { + /* GPP_G */ + "GPP_G0", "SD3_CMD", + "GPP_G1", "SD3_D0", + "GPP_G2", "SD3_D1", + "GPP_G3", "SD3_D2", + "GPP_G4", "SD3_D3", + "GPP_G5", "SD3_CDB", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +static const char *const icelake_pch_h_group_b_names[] = { + /* GPP_B */ + "GPP_B0", "CORE_VID_0", + "GPP_B1", "CORE_VID_1", + "GPP_B2", "VRALERTB", + "GPP_B3", "CPU_GP_2", + "GPP_B4", "CPU_GP_3", + "GPP_B5", "ISH_I2C0_SDA", + "GPP_B6", "ISH_I2C0_SCL", + "GPP_B7", "ISH_I2C1_SDA", + "GPP_B8", "ISH_I2C1_SCL", + "GPP_B9", "I2C5_SDA", + "GPP_B10", "I2C5_SCL", + "GPP_B11", "PMCALERTB", + "GPP_B12", "SLP_S0B", + "GPP_B13", "PLTRSTB", + "GPP_B14", "SPKR", + "GPP_B15", "GSPI0_CS0B", + "GPP_B16", "GSPI0_CLK", + "GPP_B17", "GSPI0_MISO", + "GPP_B18", "GSPI0_MOSI", + "GPP_B19", "GSPI1_CS0B", + "GPP_B20", "GSPI1_CLK", + "GPP_B21", "GSPI1_MISO", + "GPP_B22", "GSPI1_MOSI", + "GPP_B23", "SML1ALERTB", + "GPP_B24", "GSPI0_CLK_LOOPBK", + "GPP_B25", "GSPI1_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_a_names[] = { + /* GPP_A */ + "GPP_A0", "ESPI_IO_0", + "GPP_A1", "ESPI_IO_1", + "GPP_A2", "ESPI_IO_2", + "GPP_A3", "ESPI_IO_3", + "GPP_A4", "ESPI_CSB", + "GPP_A5", "ESPI_CLK", + "GPP_A6", "ESPI_RESETB", + "GPP_A7", "I2S2_SCLK", + "GPP_A8", "I2S2_SFRM", + "GPP_A9", "I2S2_TXD", + "GPP_A10", "I2S2_RXD", + "GPP_A11", "SATA_DEVSLP_2", + "GPP_A12", "SATAXPCIE_1", + "GPP_A13", "SATAXPCIE_2", + "GPP_A14", "USB2_OCB_1", + "GPP_A15", "USB2_OCB_2", + "GPP_A16", "USB2_OCB_3", + "GPP_A17", "DDSP_HPD_C", + "GPP_A18", "DDSP_HPD_B", + "GPP_A19", "DDSP_HPD_1", + "GPP_A20", "DDSP_HPD_2", + "GPP_A21", "I2S5_TXD", + "GPP_A22", "I2S5_RXD", + "GPP_A23", "I2S1_SCLK", + "GPP_A24", "ESPI_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_h_names[] = { + /* GPP_H */ + "GPP_H0", "SD_1P8_SEL", + "GPP_H1", "SD_PWR_EN_B", + "GPP_H2", "GPPC_H_2", + "GPP_H3", "SX_EXIT_HOLDOFFB", + "GPP_H4", "I2C2_SDA", + "GPP_H5", "I2C2_SCL", + "GPP_H6", "I2C3_SDA", + "GPP_H7", "I2C3_SCL", + "GPP_H8", "I2C4_SDA", + "GPP_H9", "I2C4_SCL", + "GPP_H10", "SRCCLKREQB_4", + "GPP_H11", "SRCCLKREQB_5", + "GPP_H12", "M2_SKT2_CFG_0", + "GPP_H13", "M2_SKT2_CFG_1", + "GPP_H14", "M2_SKT2_CFG_2", + "GPP_H15", "M2_SKT2_CFG_3", + "GPP_H16", "DDPB_CTRLCLK", + "GPP_H17", "DDPB_CTRLDATA", + "GPP_H18", "CPU_VCCIO_PWR_GATEB", + "GPP_H19", "TIME_SYNC_0", + "GPP_H20", "IMGCLKOUT_1", + "GPP_H21", "IMGCLKOUT_2", + "GPP_H22", "IMGCLKOUT_3", + "GPP_H23", "IMGCLKOUT_4", +}; + +static const char *const icelake_pch_h_group_d_names[] = { + /* GPP_D */ + "GPP_D0", "ISH_GP_0", + "GPP_D1", "ISH_GP_1", + "GPP_D2", "ISH_GP_2", + "GPP_D3", "ISH_GP_3", + "GPP_D4", "IMGCLKOUT_0", + "GPP_D5", "SRCCLKREQB_0", + "GPP_D6", "SRCCLKREQB_1", + "GPP_D7", "SRCCLKREQB_2", + "GPP_D8", "SRCCLKREQB_3", + "GPP_D9", "ISH_SPI_CSB", + "GPP_D10", "ISH_SPI_CLK", + "GPP_D11", "ISH_SPI_MISO", + "GPP_D12", "ISH_SPI_MOSI", + "GPP_D13", "ISH_UART0_RXD", + "GPP_D14", "ISH_UART0_TXD", + "GPP_D15", "ISH_UART0_RTSB", + "GPP_D16", "ISH_UART0_CTSB", + "GPP_D17", "ISH_GP_4", + "GPP_D18", "ISH_GP_5", + "GPP_D19", "I2S_MCLK", + "GPP_D10", "GSPI2_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_f_names[] = { + /* GPP_F */ + "GPP_F0", "CNV_BRI_DT", + "GPP_F1", "CNV_BRI_RSP", + "GPP_F2", "CNV_RGI_DT", + "GPP_F3", "CNV_RGI_RSP", + "GPP_F4", "CNV_RF_RESET_B", + "GPP_F5", "EMMC_HIP_MON", + "GPP_F6", "CNV_PA_BLANKING", + "GPP_F7", "EMMC_CMD", + "GPP_F8", "EMMC_DATA0", + "GPP_F9", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESETB", + "GPP_F19", "A4WP_PRESENT", +}; + +static const char *const icelake_pch_h_group_vgpio_names[] = { + /* vGPIO */ + "CNV_BTEN", "", + "CNV_WCEN", "", + "CNV_BT_HOST_WAKEB", "", + "CNV_BT_IF_SELECT", "", + "vCNV_BT_UART_TXD", "", + "vCNV_BT_UART_RXD", "", + "vCNV_BT_UART_CTS_B", "", + "vCNV_BT_UART_RTS_B", "", + "vCNV_MFUART1_TXD", "", + "vCNV_MFUART1_RXD", "", + "vCNV_MFUART1_CTS_B", "", + "vCNV_MFUART1_RTS_B", "", + "vUART0_TXD", "", + "vUART0_RXD", "", + "vUART0_CTS_B", "", + "vUART0_RTS_B", "", + "vISH_UART0_TXD", "", + "vISH_UART0_RXD", "", + "vISH_UART0_CTS_B", "", + "vISH_UART0_RTS_B", "", + "vCNV_BT_I2S_BCLK", "", + "vCNV_BT_I2S_WS_SYNC", "", + "vCNV_BT_I2S_SDO", "", + "vCNV_BT_I2S_SDI", "", + "vI2S2_SCLK", "", + "vI2S2_SFRM", "", + "vI2S2_TXD", "", + "vI2S2_RXD", "", + "vSD3_CD_B", "", +}; + +static const char *const icelake_pch_h_group_c_names[] = { + /* GPP_C */ + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERTB", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERTB", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", + "GPP_C8", "UART0_RXD", + "GPP_C9", "UART0_TXD", + "GPP_C10", "UART0_RTSB", + "GPP_C11", "UART0_CTSB", + "GPP_C12", "UART1_RXD", + "GPP_C13", "UART1_TXD", + "GPP_C14", "UART1_RTSB", + "GPP_C15", "UART1_CTSB", + "GPP_C16", "I2C0_SDA", + "GPP_C17", "I2C0_SCL", + "GPP_C18", "I2C1_SDA", + "GPP_C19", "I2C1_SCL", + "GPP_C20", "UART2_RXD", + "GPP_C21", "UART2_TXD", + "GPP_C22", "UART2_RTSB", + "GPP_C23", "UART2_CTSB", +}; + +static const char *const icelake_pch_h_group_hvcmos_names[] = { + /* HVCMOS */ + "L_BKLTEN", "", + "L_BKLTCTL", "", + "L_VDDEN", "", + "SYS_PWROK", "", + "SYS_RESETB", "", + "MLK_RSTB", "", +}; + +static const char *const icelake_pch_h_group_e_names[] = { + /* GPP_E */ + "GPP_E0", "SATAXPCIE_0", + "GPP_E1", "SPI1_IO_2", + "GPP_E2", "SPI1_IO_3", + "GPP_E3", "CPU_GP_0", + "GPP_E4", "SATA_DEVSLP_0", + "GPP_E5", "SATA_DEVSLP_1", + "GPP_E6", "GPPC_E_6", + "GPP_E7", "CPU_GP_1", + "GPP_E8", "SATA_LEDB", + "GPP_E9", "USB2_OCB_0", + "GPP_E10", "SPI1_CSB", + "GPP_E11", "SPI1_CLK", + "GPP_E12", "SPI1_MISO_IO_1", + "GPP_E13", "SPI1_MOSI_IO_0", + "GPP_E14", "DDSP_HPD_A", + "GPP_E15", "ISH_GP_6", + "GPP_E16", "ISH_GP_7", + "GPP_E17", "DISP_MISC_4", + "GPP_E18", "DDP1_CTRLCLK", + "GPP_E19", "DDP1_CTRLDATA", + "GPP_E20", "DDP2_CTRLCLK", + "GPP_E21", "DDP2_CTRLDATA", + "GPP_E22", "DDPA_CTRLCLK", + "GPP_E23", "DDPA_CTRLDATA", +}; + +static const char *const icelake_pch_h_group_jtag_names[] = { + /* JTAG */ + "JTAG0", "JTAG_TDO", + "JTAG1", "JTAGX", + "JTAG2", "PRDYB", + "JTAG3", "PREQB", + "JTAG4", "CPU_TRSTB", + "JTAG5", "JTAG_TDI", + "JTAG6", "JTAG_TMS", + "JTAG7", "JTAG_TCK", + "JTAG8", "ITP_PMODE", +}; + +static const char *const icelake_pch_h_group_r_names[] = { + /* GPP_R */ + "GPP_R0", "HDA_BCLK", + "GPP_R1", "HDA_SYNC", + "GPP_R2", "HDA_SDO", + "GPP_R3", "HDA_SDI_0", + "GPP_R4", "HDA_RSTB", + "GPP_R5", "HDA_SDI_1", + "GPP_R6", "I2S1_TXD", + "GPP_R7", "I2S1_RXD", +}; + +static const char *const icelake_pch_h_group_s_names[] = { + /* GPP_S */ + "GPP_S0", "SNDW1_CLK", + "GPP_S1", "SNDW1_DATA", + "GPP_S2", "SNDW2_CLK", + "GPP_S3", "SNDW2_DATA", + "GPP_S4", "SNDW3_CLK", + "GPP_S5", "SNDW3_DATA", + "GPP_S6", "SNDW4_CLK", + "GPP_S7", "SNDW4_DATA", +}; + +static const char *const icelake_pch_h_group_spi_names[] = { + /* SPI */ + "SPIP0", "SPI0_IO_2", + "SPIP1", "SPI0_IO_3", + "SPIP2", "SPI0_MOSI_IO_0", + "SPIP3", "SPI0_MISO_IO_1", + "SPIP4", "SPI0_TPM_CSB", + "SPIP5", "SPI0_FLASH_0_CSB", + "SPIP6", "SPI0_FLASH_1_CSB", + "SPIP7", "SPI0_CLK", + "SPIP8", "SPI0_CLK_LOOPBK", +}; + +static const struct gpio_group icelake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_g_names, +}; + +static const struct gpio_group icelake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_b_names, +}; + +static const struct gpio_group icelake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_a_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { + &icelake_pch_h_group_g, + &icelake_pch_h_group_b, + &icelake_pch_h_group_a, +}; + +static const struct gpio_community icelake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), + .groups = icelake_pch_h_community_0_groups, +}; + +static const struct gpio_group icelake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_h_names, +}; + +static const struct gpio_group icelake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_d_names, +}; + +static const struct gpio_group icelake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_f_names, +}; + +static const struct gpio_group icelake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Group vGPIO_0 -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_vgpio_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { + &icelake_pch_h_group_h, + &icelake_pch_h_group_d, + &icelake_pch_h_group_f, + &icelake_pch_h_group_vgpio_0, +}; + +static const struct gpio_community icelake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), + .groups = icelake_pch_h_community_1_groups, +}; + + +static const struct gpio_community icelake_pch_h_community_2 = { + .name = "------- GPIO Community 2 (skipped)-------", + .pcr_port_id = 0x6c, + .group_count = 0, +}; + +static const struct gpio_community icelake_pch_h_community_3 = { + .name = "------- GPIO Community 3 (skipped)-------", + .pcr_port_id = 0x6b, + .group_count = 0, +}; + +static const struct gpio_group icelake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_c_names, +}; + +static const struct gpio_group icelake_pch_h_group_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_hvcmos_names, +}; + +static const struct gpio_group icelake_pch_h_group_e = { + .display = "------- GPIO Group E -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_e_names, +}; + +static const struct gpio_group icelake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_jtag_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { + &icelake_pch_h_group_c, + &icelake_pch_h_group_hvcmos, + &icelake_pch_h_group_e, + &icelake_pch_h_group_jtag, +}; + +static const struct gpio_community icelake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), + .groups = icelake_pch_h_community_4_groups, +}; + +static const struct gpio_group icelake_pch_h_group_r = { + .display = "------- GPIO Group R -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_r_names, +}; + +static const struct gpio_group icelake_pch_h_group_s = { + .display = "------- GPIO Group S -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_s_names, +}; + +static const struct gpio_group icelake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_spi_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { + &icelake_pch_h_group_r, + &icelake_pch_h_group_s, + &icelake_pch_h_group_spi, +}; + +static const struct gpio_community icelake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), + .groups = icelake_pch_h_community_5_groups, +}; + +static const struct gpio_community *const icelake_pch_h_communities[] = { + &icelake_pch_h_community_0, + &icelake_pch_h_community_1, + &icelake_pch_h_community_2, + &icelake_pch_h_community_3, + &icelake_pch_h_community_4, + &icelake_pch_h_community_5, +}; static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) @@ -2299,6 +2770,12 @@ pad_stepping = 16; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + community_count = ARRAY_SIZE(icelake_pch_h_communities); + communities = icelake_pch_h_communities; + pad_stepping = 16; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..f4bf87b 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -132,6 +132,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: sbbar_phys = 0xfd000000; use_p2sb = false; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 11 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit February 2020