coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Subrata Banik (Code Review) 03 Feb '20

03 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 38: (2 comments) https://review.coreboot.org/c/coreboot/+/18457/38/src/soc/intel/common/base… File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/18457/38/src/soc/intel/common/base… PS38, Line 33: #if CONFIG(PLATFORM_USES_FSP1_1) : #include <fsp/bootblock.h> : #else : static inline void bootblock_fsp_temp_ram_init(void) {} : #endif remove this https://review.coreboot.org/c/coreboot/+/18457/38/src/soc/intel/common/base… PS38, Line 124: i guess we have some fundamental mistake in this patch Flow should be assembly code calling "bootblock_c_entry()"->call should come here in common bootblock->passes to bootblock_main_with_basetime() -> again from lib/bootblock.c it comes into common stage file here with dedicated code like this bootblock_soc_early_init/bootblock_soc_init/bootblock_pch_early_init/bootblock_pch_init/bootblock_cpu_early_init/bootblock_cpu_init -> Idea is to make all common operations across core/atom here and also provide a placeholder to perform any specific SoC related job like page table at line 93 (that code shouldn't be here) So whoever debug can trace the flow easily and new SoC port job also reduced, if nothing specific to SoC code then bootblock.c won't even exist inside SoC directory. -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 38 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Feb 2020 11:08:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Patrick Rudolph (Code Review) 03 Feb '20

03 Feb '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 38: (4 comments) https://review.coreboot.org/c/coreboot/+/18457/37//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/18457/37//COMMIT_MSG@11 PS37, Line 11: flexibility I don't see that achieved. As the sequence is hardcoded and no functions are optional there's no flexibility. https://review.coreboot.org/c/coreboot/+/18457/37//COMMIT_MSG@49 PS37, Line 49: custom That reads as everything introduced is optional, and SoC maintainers can do whatever they want. https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/base… File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/base… PS37, Line 39: bootblock_soc_early_init(void) This reminds me on UEFI implementations that use function pointers everywhere * Why are all ops mandatory? * Why are you using function pointers? That prevents the linker from doing garbage collection * Using runtime checks prevent build time errors, that's likely not what we want, as all functions are mandatory * Giving SoC maintainers flexibility in naming scheme is likely not what we want. It will be impossible to find the corresponding SoC function in an IDE * There's only a single soc at time, so why use function pointers at all? https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/base… PS37, Line 102: (CONFIG(PAGING_IN_CACHE_AS_RAM)) Why is there APL/GLK specific code here? Wasn't the idea to make it more flexible? -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 38 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Feb 2020 10:48:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Usha P (Code Review) 03 Feb '20

03 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 37: > Patch Set 36: > > (4 comments) Updated the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 37 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Feb 2020 08:41:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Usha P (Code Review) 03 Feb '20

03 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 37: (4 comments) https://review.coreboot.org/c/coreboot/+/18457/36//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/18457/36//COMMIT_MSG@9 PS36, Line 9: is > are Done https://review.coreboot.org/c/coreboot/+/18457/36//COMMIT_MSG@9 PS36, Line 9: ensures > ensure Done https://review.coreboot.org/c/coreboot/+/18457/36//COMMIT_MSG@10 PS36, Line 10: align > aligned Done https://review.coreboot.org/c/coreboot/+/18457/36//COMMIT_MSG@14 PS36, Line 14: soc > SoCs Done -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 37 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Feb 2020 08:40:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Usha P (Code Review) 03 Feb '20

03 Feb '20

Usha P has uploaded a new patch set (#37) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... soc/intel/common: Add bootblock common stage file The intention of this design is to commonalize redundant basic initialization procedure in an intel SoC, along with giving any new SoCs flexibility to add custom init sequences. Platform initialization in bootblock can be visualized mainly as initializing the below components. 1. SoC - mainly System Agent, PMC, etc 2. PCH - PCH IPs like GSPI, SPI, SMBUS, P2SB 3. CPU - Early MTRR setup (enable SPI cache), Paging Bootblock initialization is also split into the below stages 1. Early - prior to console init 2. Late - post console init A unified structure of functions is created to facilitate running the above defined sequence (and dropping the word "late") struct bootblock_ops { void (*bootblock_soc_early_init)(void); void (*bootblock_soc_init)(void); void (*bootblock_pch_early_init)(void); void (*bootblock_pch_init)(void); void (*bootblock_cpu_early_init)(void); void (*bootblock_cpu_init)(void); }; Also, some of the platform initialization is common across Intel SoCs. Those sequences are moved to a common location, which can be used by the SoC code. bootblock_cmn_soc_early_init() bootblock_cmn_soc_init() bootblock_cmn_pch_early_init() bootblock_cmn_pch_init() bootblock_cmn_cpu_early_init() bootblock_cmn_cpu_init() The control over what is to be initialized in bootblock is governed by the actuall SoC code. Soc should define the operations to be executed using the bootblock_ops structure. The SoC code can use the common functions along with its own custom ones. BUG=b:78109109 TEST=Boot to OS on CNL, GLK systems. Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- A src/soc/intel/common/basecode/bootblock/Kconfig A src/soc/intel/common/basecode/bootblock/Makefile.inc A src/soc/intel/common/basecode/bootblock/bootblock.c A src/soc/intel/common/basecode/include/intelbasecode/bootblock.h 4 files changed, 181 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18457/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 37 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jackso...
by Raymond Chung (Code Review) 03 Feb '20

03 Feb '20

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38675 ) Change subject: src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jacksonville LOM GbE ...................................................................... src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jacksonville LOM GbE FSP defined a special clock source usage 0x70 for PCH LAN device, update that to intel coffeelake_rvp cml_s platform. TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I67399b88520f1371400f0dcd414ac2bcbc51082e Signed-off-by: raymondchung <raymondchung(a)ami.corp-partner.google.com> --- M src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38675/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb index 8ffee7c..aaf1230 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb @@ -102,7 +102,7 @@ # PCIe root port 13 for GBe LAN register "PcieRpEnable[12]" = "1" # RP 13 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_LAN" # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67399b88520f1371400f0dcd414ac2bcbc51082e Gerrit-Change-Number: 38675 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: Move SA _CRS to runtime SSDT generator
by Furquan Shaikh (Code Review) 03 Feb '20

03 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38608 to look at the new patch set (#2). Change subject: WIP: Move SA _CRS to runtime SSDT generator ...................................................................... WIP: Move SA _CRS to runtime SSDT generator This is currently WIP patch. Change-Id: I58fbc5c99dcdb9463da9f2ace3423294af614abf Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 64 insertions(+), 113 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38608/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fbc5c99dcdb9463da9f2ace3423294af614abf Gerrit-Change-Number: 38608 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/google/fizz: Drop NO_FADT_8042 in Kconfig
by Edward O'Callaghan (Code Review) 03 Feb '20

03 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38502 ) Change subject: mainboard/google/fizz: Drop NO_FADT_8042 in Kconfig ...................................................................... mainboard/google/fizz: Drop NO_FADT_8042 in Kconfig This looks like it is only relevant to Skylake. Change-Id: Idb82b6339dc6bb78c02d49eddd31623aaad083ad Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/fizz/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38502/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index fbe98be..6265297 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -18,7 +18,6 @@ select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT - select NO_FADT_8042 select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb82b6339dc6bb78c02d49eddd31623aaad083ad Gerrit-Change-Number: 38502 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/t440p: fix keyboard backlight
by Iru Cai (vimacs) (Code Review) 03 Feb '20

03 Feb '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38650 to review the following change. Change subject: lenovo/t440p: fix keyboard backlight ...................................................................... lenovo/t440p: fix keyboard backlight Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/mainboard/lenovo/t440p/cmos.layout M src/mainboard/lenovo/t440p/devicetree.cb 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38650/1 diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 8c5fb0b..e61886b 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -103,9 +103,10 @@ 8 1 Primary 9 0 AHCI 9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only +# Haswell ThinkPads has no Thinklight +#10 0 Both +10 1 Keyboard +#10 2 Thinklight only 10 3 None #12 0 Integrated Only #12 1 Discrete Only diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 7e5e616..b63767e 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -83,6 +83,7 @@ register "config1" = "0x0d" register "config2" = "0xa8" register "config3" = "0xc4" + register "has_keyboard_backlight" = "1" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" -- To view, visit https://review.coreboot.org/c/coreboot/+/38650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043 Gerrit-Change-Number: 38650 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling for mushu
by Amanda Hwang (Code Review) 03 Feb '20

03 Feb '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38340 ) Change subject: hatch: Fix FPMCU pwr/rst gpio handling for mushu ...................................................................... hatch: Fix FPMCU pwr/rst gpio handling for mushu Hatch moves power/reset pin control of FPMCU to var/board/ramstage. So add this change in mushu. BUG=b:147274277 TEST=emerge-hatch coreboot Change-Id: I10c9b8f673618ddaddfeed86705f3c838e7021fd Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/mushu/Makefile.inc M src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/ramstage.c 3 files changed, 62 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38340/1 diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5a..0e7863d 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -21,3 +21,4 @@ ramstage-y += gpio.c bootblock-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e1594..18cbc09 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -57,8 +57,6 @@ * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -88,3 +86,32 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10c9b8f673618ddaddfeed86705f3c838e7021fd Gerrit-Change-Number: 38340 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020