coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1625 discussions

Change in coreboot[master]: ec/google/chromeec: Add new wrappers for host commands
by Tim Wawrzynczak (Code Review) 01 Feb '20

01 Feb '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38540 ) Change subject: ec/google/chromeec: Add new wrappers for host commands ...................................................................... ec/google/chromeec: Add new wrappers for host commands Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 86 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38540/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 0b23034..7a4f27f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -15,16 +15,21 @@ #include <stdint.h> #include <string.h> -#include <cbmem.h> -#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> #include <assert.h> #include <bootmode.h> #include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> #include <delay.h> +#include <device/device.h> +#include <device/path.h> #include <elog.h> #include <rtc.h> -#include <stdlib.h> #include <security/vboot/vboot_common.h> +#include <stdlib.h> #include <timer.h> #include "chip.h" @@ -1419,6 +1424,60 @@ return ec_image_type; } +int google_chromeec_get_num_pd_ports(int *num_ports) +{ + struct ec_response_charge_port_count resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_CHARGE_PORT_COUNT, + .cmd_version = 0, + .cmd_data_out = &resp, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + *num_ports = resp.port_count; + return 0; +} + +int google_chromeec_get_pd_port_caps(int port, + enum ec_pd_power_role_caps *power_role_cap, + enum ec_pd_try_power_role_caps *try_power_role_cap, + enum ec_pd_data_role_caps *data_role_cap, + enum ec_pd_port_location *port_location) +{ + struct ec_params_get_pd_port_caps params = { + .port = port, + }; + struct ec_response_get_pd_port_caps resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_PD_PORT_CAPS, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + *power_role_cap = resp.pd_power_role_cap; + *try_power_role_cap = resp.pd_try_power_role_cap; + *data_role_cap = resp.pd_data_role_cap; + *port_location = resp.pd_port_location; + + return 0; +} + void google_chromeec_init(void) { google_chromeec_log_uptimeinfo(); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index d90d24c..8051486 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -299,4 +299,28 @@ */ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); +/** + * Get number of PD-capable USB ports from EC. + * + * @param *num_ports If successful, num_ports is the number + * of PD-capable USB ports according to the EC. + * @return 0 on success, -1 on error + */ +int google_chromeec_get_num_pd_ports(int *num_ports); + +/** + * Get role-based capabilities for a USB-PD port + * + * @param port Which port to get information about + * @param *power_role_cap The power-role capabillity of the port + * @param *try_power_role_cap The Try-power-role capability of the port + * @param *data_role_cap The data role capability of the port + * @param *port_location Location of the port on the device + * @return 0 on success, -1 on error + */ +int google_chromeec_get_pd_port_caps(int port, + enum ec_pd_power_role_caps *power_role_cap, + enum ec_pd_try_power_role_caps *try_power_role_cap, + enum ec_pd_data_role_caps *data_role_cap, + enum ec_pd_port_location *port_location); #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Gerrit-Change-Number: 38540 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/docker/Makefile: Correct help output
by Wim Vervoorn (Code Review) 01 Feb '20

01 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38649 ) Change subject: util/docker/Makefile: Correct help output ...................................................................... util/docker/Makefile: Correct help output The help output suggests clean-docker should be used to remove the docker coreboot containers and images. The Makefile actually supports the docker-clean target. Corrected the help output to reflect the actual Makefile target. BUG=N/A TEST=build Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38649/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 619de85..808a1d7 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -193,7 +193,7 @@ @echo " doc.coreboot.org - Build doc.coreboot.org container" @echo " clean-coreboot-containers - Remove all docker coreboot containers" @echo " clean-coreboot-images - Remove all docker coreboot images" - @echo " clean-docker - Remove docker coreboot containers & images" + @echo " docker-clean - Remove docker coreboot containers & images" @echo @echo "Commands for using docker images" @echo " docker-build-coreboot - Build coreboot under coreboot-sdk" -- To view, visit https://review.coreboot.org/c/coreboot/+/38649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Gerrit-Change-Number: 38649 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/t520: Switch to overridetree
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37295 ) Change subject: mb/lenovo/t520: Switch to overridetree ...................................................................... mb/lenovo/t520: Switch to overridetree Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/Kconfig R src/mainboard/lenovo/t520/devicetree.cb D src/mainboard/lenovo/t520/variants/t520/devicetree.cb A src/mainboard/lenovo/t520/variants/t520/overridetree.cb A src/mainboard/lenovo/t520/variants/w520/overridetree.cb 5 files changed, 26 insertions(+), 183 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37295/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index a6183d9..6d31be2 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -51,9 +51,9 @@ string default "lenovo/t520" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb similarity index 98% rename from src/mainboard/lenovo/t520/variants/w520/devicetree.cb rename to src/mainboard/lenovo/t520/devicetree.cb index 8b2cbe7..49e57db 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -90,7 +90,7 @@ end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb deleted file mode 100644 index 0bfa18f..0000000 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ /dev/null @@ -1,180 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21cf inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d1 - end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x1f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21ce - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI-2-PCI bridge - - device pci 1f.0 on #LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x09" - register "config2" = "0xa0" - register "config3" = "0xc2" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus - device pci 1f.5 off end # IDE controller - device pci 1f.6 off end # Thermal controller - end - end -end diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb new file mode 100644 index 0000000..8016d10 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -0,0 +1,16 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end # LPC bridge + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller + end + end +end diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb new file mode 100644 index 0000000..a6f3738 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -0,0 +1,7 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Gerrit-Change-Number: 37295 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: nb/intel/sandybridge: improve indexed register helper macros
by Felix Held (Code Review) 01 Feb '20

01 Feb '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38577 ) Change subject: nb/intel/sandybridge: improve indexed register helper macros ...................................................................... nb/intel/sandybridge: improve indexed register helper macros Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38577/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index f5c1e41..ffc1d9f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -128,11 +128,11 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* Indexed register helper macros */ -#define Gz(r, z) ((r) + ((z) * 0x100)) -#define Ly(r, y) ((r) + ((y) * 4)) -#define Cx(r, x) ((r) + ((x) * 0x400)) -#define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) -#define GzLy(r, z, y) ((r) + ((z) * 0x100) + ((y) * 4)) +#define Gz(r, z) ((r) + ((z) << 8)) +#define Ly(r, y) ((r) + ((y) << 2)) +#define Cx(r, x) ((r) + ((x) << 10)) +#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) +#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) /* byte lane training register base addresses */ #define LANEBASE_B0 0x0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/38577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Gerrit-Change-Number: 38577 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: device/pnp_device: improve warning/error messages
by Felix Held (Code Review) 31 Jan '20

31 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38655 ) Change subject: device/pnp_device: improve warning/error messages ...................................................................... device/pnp_device: improve warning/error messages Explicitly state that the assignment is missing in the devicetree. In the case of the warnings, the missing assignments might not be an issue. Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38655/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 81aa889..dc921e7 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -129,12 +129,12 @@ (resource->index != PNP_IDX_IRQ0) && (resource->index != PNP_IDX_IRQ1)) printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " - "0x%010llx not assigned\n", dev_path(dev), + "0x%010llx not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); else printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, + "not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Gerrit-Change-Number: 38655 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Jump to page:

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020