coreboot-gerrit February 2020

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Change in coreboot[master]: mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37944 ) Change subject: mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method ...................................................................... mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/platform.asl 2 files changed, 2 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37944/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index bcd6de6..dba7809 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -71,62 +71,6 @@ /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 2371eab..a8296cc 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -46,62 +46,6 @@ /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Gerrit-Change-Number: 37944 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: sb/intel/common/acpi: Add more Windows versions
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37943 ) Change subject: sb/intel/common/acpi: Add more Windows versions ...................................................................... sb/intel/common/acpi: Add more Windows versions Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/common/acpi/platform.asl 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37943/1 diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index 03cb625..9cd41eb 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -79,6 +79,14 @@ Store (2001, OSYS) } + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + If (_OSI("Windows 2001 SP2")) { Store (2002, OSYS) } @@ -86,5 +94,21 @@ If (_OSI("Windows 2006")) { Store (2006, OSYS) } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Gerrit-Change-Number: 37943 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
by Patrick Georgi (Code Review) 01 Feb '20

01 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems ...................................................................... util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 479 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Alexander Couzens: Looks good to me, approved diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..9610fd6 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1070,6 +1070,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..4ec79c4 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2157,6 +2157,477 @@ &cannonlake_pch_h_community_4, }; +/* Ice Lake-LP */ +static const char *const icelake_pch_h_group_g_names[] = { + /* GPP_G */ + "GPP_G0", "SD3_CMD", + "GPP_G1", "SD3_D0", + "GPP_G2", "SD3_D1", + "GPP_G3", "SD3_D2", + "GPP_G4", "SD3_D3", + "GPP_G5", "SD3_CDB", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +static const char *const icelake_pch_h_group_b_names[] = { + /* GPP_B */ + "GPP_B0", "CORE_VID_0", + "GPP_B1", "CORE_VID_1", + "GPP_B2", "VRALERTB", + "GPP_B3", "CPU_GP_2", + "GPP_B4", "CPU_GP_3", + "GPP_B5", "ISH_I2C0_SDA", + "GPP_B6", "ISH_I2C0_SCL", + "GPP_B7", "ISH_I2C1_SDA", + "GPP_B8", "ISH_I2C1_SCL", + "GPP_B9", "I2C5_SDA", + "GPP_B10", "I2C5_SCL", + "GPP_B11", "PMCALERTB", + "GPP_B12", "SLP_S0B", + "GPP_B13", "PLTRSTB", + "GPP_B14", "SPKR", + "GPP_B15", "GSPI0_CS0B", + "GPP_B16", "GSPI0_CLK", + "GPP_B17", "GSPI0_MISO", + "GPP_B18", "GSPI0_MOSI", + "GPP_B19", "GSPI1_CS0B", + "GPP_B20", "GSPI1_CLK", + "GPP_B21", "GSPI1_MISO", + "GPP_B22", "GSPI1_MOSI", + "GPP_B23", "SML1ALERTB", + "GPP_B24", "GSPI0_CLK_LOOPBK", + "GPP_B25", "GSPI1_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_a_names[] = { + /* GPP_A */ + "GPP_A0", "ESPI_IO_0", + "GPP_A1", "ESPI_IO_1", + "GPP_A2", "ESPI_IO_2", + "GPP_A3", "ESPI_IO_3", + "GPP_A4", "ESPI_CSB", + "GPP_A5", "ESPI_CLK", + "GPP_A6", "ESPI_RESETB", + "GPP_A7", "I2S2_SCLK", + "GPP_A8", "I2S2_SFRM", + "GPP_A9", "I2S2_TXD", + "GPP_A10", "I2S2_RXD", + "GPP_A11", "SATA_DEVSLP_2", + "GPP_A12", "SATAXPCIE_1", + "GPP_A13", "SATAXPCIE_2", + "GPP_A14", "USB2_OCB_1", + "GPP_A15", "USB2_OCB_2", + "GPP_A16", "USB2_OCB_3", + "GPP_A17", "DDSP_HPD_C", + "GPP_A18", "DDSP_HPD_B", + "GPP_A19", "DDSP_HPD_1", + "GPP_A20", "DDSP_HPD_2", + "GPP_A21", "I2S5_TXD", + "GPP_A22", "I2S5_RXD", + "GPP_A23", "I2S1_SCLK", + "GPP_A24", "ESPI_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_h_names[] = { + /* GPP_H */ + "GPP_H0", "SD_1P8_SEL", + "GPP_H1", "SD_PWR_EN_B", + "GPP_H2", "GPPC_H_2", + "GPP_H3", "SX_EXIT_HOLDOFFB", + "GPP_H4", "I2C2_SDA", + "GPP_H5", "I2C2_SCL", + "GPP_H6", "I2C3_SDA", + "GPP_H7", "I2C3_SCL", + "GPP_H8", "I2C4_SDA", + "GPP_H9", "I2C4_SCL", + "GPP_H10", "SRCCLKREQB_4", + "GPP_H11", "SRCCLKREQB_5", + "GPP_H12", "M2_SKT2_CFG_0", + "GPP_H13", "M2_SKT2_CFG_1", + "GPP_H14", "M2_SKT2_CFG_2", + "GPP_H15", "M2_SKT2_CFG_3", + "GPP_H16", "DDPB_CTRLCLK", + "GPP_H17", "DDPB_CTRLDATA", + "GPP_H18", "CPU_VCCIO_PWR_GATEB", + "GPP_H19", "TIME_SYNC_0", + "GPP_H20", "IMGCLKOUT_1", + "GPP_H21", "IMGCLKOUT_2", + "GPP_H22", "IMGCLKOUT_3", + "GPP_H23", "IMGCLKOUT_4", +}; + +static const char *const icelake_pch_h_group_d_names[] = { + /* GPP_D */ + "GPP_D0", "ISH_GP_0", + "GPP_D1", "ISH_GP_1", + "GPP_D2", "ISH_GP_2", + "GPP_D3", "ISH_GP_3", + "GPP_D4", "IMGCLKOUT_0", + "GPP_D5", "SRCCLKREQB_0", + "GPP_D6", "SRCCLKREQB_1", + "GPP_D7", "SRCCLKREQB_2", + "GPP_D8", "SRCCLKREQB_3", + "GPP_D9", "ISH_SPI_CSB", + "GPP_D10", "ISH_SPI_CLK", + "GPP_D11", "ISH_SPI_MISO", + "GPP_D12", "ISH_SPI_MOSI", + "GPP_D13", "ISH_UART0_RXD", + "GPP_D14", "ISH_UART0_TXD", + "GPP_D15", "ISH_UART0_RTSB", + "GPP_D16", "ISH_UART0_CTSB", + "GPP_D17", "ISH_GP_4", + "GPP_D18", "ISH_GP_5", + "GPP_D19", "I2S_MCLK", + "GPP_D10", "GSPI2_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_f_names[] = { + /* GPP_F */ + "GPP_F0", "CNV_BRI_DT", + "GPP_F1", "CNV_BRI_RSP", + "GPP_F2", "CNV_RGI_DT", + "GPP_F3", "CNV_RGI_RSP", + "GPP_F4", "CNV_RF_RESET_B", + "GPP_F5", "EMMC_HIP_MON", + "GPP_F6", "CNV_PA_BLANKING", + "GPP_F7", "EMMC_CMD", + "GPP_F8", "EMMC_DATA0", + "GPP_F9", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESETB", + "GPP_F19", "A4WP_PRESENT", +}; + +static const char *const icelake_pch_h_group_vgpio_names[] = { + /* vGPIO */ + "CNV_BTEN", "", + "CNV_WCEN", "", + "CNV_BT_HOST_WAKEB", "", + "CNV_BT_IF_SELECT", "", + "vCNV_BT_UART_TXD", "", + "vCNV_BT_UART_RXD", "", + "vCNV_BT_UART_CTS_B", "", + "vCNV_BT_UART_RTS_B", "", + "vCNV_MFUART1_TXD", "", + "vCNV_MFUART1_RXD", "", + "vCNV_MFUART1_CTS_B", "", + "vCNV_MFUART1_RTS_B", "", + "vUART0_TXD", "", + "vUART0_RXD", "", + "vUART0_CTS_B", "", + "vUART0_RTS_B", "", + "vISH_UART0_TXD", "", + "vISH_UART0_RXD", "", + "vISH_UART0_CTS_B", "", + "vISH_UART0_RTS_B", "", + "vCNV_BT_I2S_BCLK", "", + "vCNV_BT_I2S_WS_SYNC", "", + "vCNV_BT_I2S_SDO", "", + "vCNV_BT_I2S_SDI", "", + "vI2S2_SCLK", "", + "vI2S2_SFRM", "", + "vI2S2_TXD", "", + "vI2S2_RXD", "", + "vSD3_CD_B", "", +}; + +static const char *const icelake_pch_h_group_c_names[] = { + /* GPP_C */ + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERTB", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERTB", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", + "GPP_C8", "UART0_RXD", + "GPP_C9", "UART0_TXD", + "GPP_C10", "UART0_RTSB", + "GPP_C11", "UART0_CTSB", + "GPP_C12", "UART1_RXD", + "GPP_C13", "UART1_TXD", + "GPP_C14", "UART1_RTSB", + "GPP_C15", "UART1_CTSB", + "GPP_C16", "I2C0_SDA", + "GPP_C17", "I2C0_SCL", + "GPP_C18", "I2C1_SDA", + "GPP_C19", "I2C1_SCL", + "GPP_C20", "UART2_RXD", + "GPP_C21", "UART2_TXD", + "GPP_C22", "UART2_RTSB", + "GPP_C23", "UART2_CTSB", +}; + +static const char *const icelake_pch_h_group_hvcmos_names[] = { + /* HVCMOS */ + "L_BKLTEN", "", + "L_BKLTCTL", "", + "L_VDDEN", "", + "SYS_PWROK", "", + "SYS_RESETB", "", + "MLK_RSTB", "", +}; + +static const char *const icelake_pch_h_group_e_names[] = { + /* GPP_E */ + "GPP_E0", "SATAXPCIE_0", + "GPP_E1", "SPI1_IO_2", + "GPP_E2", "SPI1_IO_3", + "GPP_E3", "CPU_GP_0", + "GPP_E4", "SATA_DEVSLP_0", + "GPP_E5", "SATA_DEVSLP_1", + "GPP_E6", "GPPC_E_6", + "GPP_E7", "CPU_GP_1", + "GPP_E8", "SATA_LEDB", + "GPP_E9", "USB2_OCB_0", + "GPP_E10", "SPI1_CSB", + "GPP_E11", "SPI1_CLK", + "GPP_E12", "SPI1_MISO_IO_1", + "GPP_E13", "SPI1_MOSI_IO_0", + "GPP_E14", "DDSP_HPD_A", + "GPP_E15", "ISH_GP_6", + "GPP_E16", "ISH_GP_7", + "GPP_E17", "DISP_MISC_4", + "GPP_E18", "DDP1_CTRLCLK", + "GPP_E19", "DDP1_CTRLDATA", + "GPP_E20", "DDP2_CTRLCLK", + "GPP_E21", "DDP2_CTRLDATA", + "GPP_E22", "DDPA_CTRLCLK", + "GPP_E23", "DDPA_CTRLDATA", +}; + +static const char *const icelake_pch_h_group_jtag_names[] = { + /* JTAG */ + "JTAG0", "JTAG_TDO", + "JTAG1", "JTAGX", + "JTAG2", "PRDYB", + "JTAG3", "PREQB", + "JTAG4", "CPU_TRSTB", + "JTAG5", "JTAG_TDI", + "JTAG6", "JTAG_TMS", + "JTAG7", "JTAG_TCK", + "JTAG8", "ITP_PMODE", +}; + +static const char *const icelake_pch_h_group_r_names[] = { + /* GPP_R */ + "GPP_R0", "HDA_BCLK", + "GPP_R1", "HDA_SYNC", + "GPP_R2", "HDA_SDO", + "GPP_R3", "HDA_SDI_0", + "GPP_R4", "HDA_RSTB", + "GPP_R5", "HDA_SDI_1", + "GPP_R6", "I2S1_TXD", + "GPP_R7", "I2S1_RXD", +}; + +static const char *const icelake_pch_h_group_s_names[] = { + /* GPP_S */ + "GPP_S0", "SNDW1_CLK", + "GPP_S1", "SNDW1_DATA", + "GPP_S2", "SNDW2_CLK", + "GPP_S3", "SNDW2_DATA", + "GPP_S4", "SNDW3_CLK", + "GPP_S5", "SNDW3_DATA", + "GPP_S6", "SNDW4_CLK", + "GPP_S7", "SNDW4_DATA", +}; + +static const char *const icelake_pch_h_group_spi_names[] = { + /* SPI */ + "SPIP0", "SPI0_IO_2", + "SPIP1", "SPI0_IO_3", + "SPIP2", "SPI0_MOSI_IO_0", + "SPIP3", "SPI0_MISO_IO_1", + "SPIP4", "SPI0_TPM_CSB", + "SPIP5", "SPI0_FLASH_0_CSB", + "SPIP6", "SPI0_FLASH_1_CSB", + "SPIP7", "SPI0_CLK", + "SPIP8", "SPI0_CLK_LOOPBK", +}; + +static const struct gpio_group icelake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_g_names, +}; + +static const struct gpio_group icelake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_b_names, +}; + +static const struct gpio_group icelake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_a_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { + &icelake_pch_h_group_g, + &icelake_pch_h_group_b, + &icelake_pch_h_group_a, +}; + +static const struct gpio_community icelake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), + .groups = icelake_pch_h_community_0_groups, +}; + +static const struct gpio_group icelake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_h_names, +}; + +static const struct gpio_group icelake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_d_names, +}; + +static const struct gpio_group icelake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_f_names, +}; + +static const struct gpio_group icelake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Group vGPIO_0 -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_vgpio_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { + &icelake_pch_h_group_h, + &icelake_pch_h_group_d, + &icelake_pch_h_group_f, + &icelake_pch_h_group_vgpio_0, +}; + +static const struct gpio_community icelake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), + .groups = icelake_pch_h_community_1_groups, +}; + + +static const struct gpio_community icelake_pch_h_community_2 = { + .name = "------- GPIO Community 2 (skipped)-------", + .pcr_port_id = 0x6c, + .group_count = 0, +}; + +static const struct gpio_community icelake_pch_h_community_3 = { + .name = "------- GPIO Community 3 (skipped)-------", + .pcr_port_id = 0x6b, + .group_count = 0, +}; + +static const struct gpio_group icelake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_c_names, +}; + +static const struct gpio_group icelake_pch_h_group_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_hvcmos_names, +}; + +static const struct gpio_group icelake_pch_h_group_e = { + .display = "------- GPIO Group E -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_e_names, +}; + +static const struct gpio_group icelake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_jtag_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { + &icelake_pch_h_group_c, + &icelake_pch_h_group_hvcmos, + &icelake_pch_h_group_e, + &icelake_pch_h_group_jtag, +}; + +static const struct gpio_community icelake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), + .groups = icelake_pch_h_community_4_groups, +}; + +static const struct gpio_group icelake_pch_h_group_r = { + .display = "------- GPIO Group R -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_r_names, +}; + +static const struct gpio_group icelake_pch_h_group_s = { + .display = "------- GPIO Group S -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_s_names, +}; + +static const struct gpio_group icelake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_spi_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { + &icelake_pch_h_group_r, + &icelake_pch_h_group_s, + &icelake_pch_h_group_spi, +}; + +static const struct gpio_community icelake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), + .groups = icelake_pch_h_community_5_groups, +}; + +static const struct gpio_community *const icelake_pch_h_communities[] = { + &icelake_pch_h_community_0, + &icelake_pch_h_community_1, + &icelake_pch_h_community_2, + &icelake_pch_h_community_3, + &icelake_pch_h_community_4, + &icelake_pch_h_community_5, +}; static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) @@ -2299,6 +2770,12 @@ pad_stepping = 16; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + community_count = ARRAY_SIZE(icelake_pch_h_communities); + communities = icelake_pch_h_communities; + pad_stepping = 16; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..f4bf87b 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -132,6 +132,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: sbbar_phys = 0xfd000000; use_p2sb = false; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 11 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/cbfstool/lzma: Make clang-11+'s indentation checker happy
by Patrick Georgi (Code Review) 01 Feb '20

01 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38637 ) Change subject: util/cbfstool/lzma: Make clang-11+'s indentation checker happy ...................................................................... util/cbfstool/lzma: Make clang-11+'s indentation checker happy Newest clang compilers warn about "misleading indentation", and because warnings-are-errors in our builds, that breaks the build. The lzma code base is vendored in, so we might just have to update it, but that's a bigger effort than just removing a couple of spaces (the coding style of the file is horrible, but I will only change it as much as the compilers ask for). BUG=chromium:1039526 Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/lzma/C/LzmaEnc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38637/1 diff --git a/util/cbfstool/lzma/C/LzmaEnc.c b/util/cbfstool/lzma/C/LzmaEnc.c index e7d14c5..f2a8320 100644 --- a/util/cbfstool/lzma/C/LzmaEnc.c +++ b/util/cbfstool/lzma/C/LzmaEnc.c @@ -1246,7 +1246,7 @@ startLen = lenTest + 1; /* if (_maxMode) */ - { + { uint32_t lenTest2 = lenTest + 1; uint32_t limit = lenTest2 + p->numFastuint8_ts; uint32_t nextRepMatchPrice; @@ -1290,7 +1290,7 @@ } } } - } + } } } /* for (uint32_t lenTest = 2; lenTest <= newLen; lenTest++) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd Gerrit-Change-Number: 38637 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: mb/google/hatch: Modify kohaku's EC_SCI_EVENTS mask
by Tim Wawrzynczak (Code Review) 01 Feb '20

01 Feb '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38654 ) Change subject: mb/google/hatch: Modify kohaku's EC_SCI_EVENTS mask ...................................................................... mb/google/hatch: Modify kohaku's EC_SCI_EVENTS mask Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=System shows ACPI interrupt as the wakeup IRQ, and the MKBP host event is properly processed as well. Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38654/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index a58d41d..377b703 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -20,12 +20,29 @@ #define EC_ENABLE_MULTIPLE_DPTF_PROFILES +/* Add EC_HOST_EVENT_MKBP from baseboard */ #undef MAINBOARD_EC_S3_WAKE_EVENTS - #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ +#undef MAINBOARD_EC_SCI_EVENTS +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + #endif /* VARIANT_EC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1 Gerrit-Change-Number: 38654 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: ec/google/chromeec: Add new wrappers for host commands
by Tim Wawrzynczak (Code Review) 01 Feb '20

01 Feb '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38540 ) Change subject: ec/google/chromeec: Add new wrappers for host commands ...................................................................... ec/google/chromeec: Add new wrappers for host commands Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 86 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38540/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 0b23034..7a4f27f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -15,16 +15,21 @@ #include <stdint.h> #include <string.h> -#include <cbmem.h> -#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> #include <assert.h> #include <bootmode.h> #include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> #include <delay.h> +#include <device/device.h> +#include <device/path.h> #include <elog.h> #include <rtc.h> -#include <stdlib.h> #include <security/vboot/vboot_common.h> +#include <stdlib.h> #include <timer.h> #include "chip.h" @@ -1419,6 +1424,60 @@ return ec_image_type; } +int google_chromeec_get_num_pd_ports(int *num_ports) +{ + struct ec_response_charge_port_count resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_CHARGE_PORT_COUNT, + .cmd_version = 0, + .cmd_data_out = &resp, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + *num_ports = resp.port_count; + return 0; +} + +int google_chromeec_get_pd_port_caps(int port, + enum ec_pd_power_role_caps *power_role_cap, + enum ec_pd_try_power_role_caps *try_power_role_cap, + enum ec_pd_data_role_caps *data_role_cap, + enum ec_pd_port_location *port_location) +{ + struct ec_params_get_pd_port_caps params = { + .port = port, + }; + struct ec_response_get_pd_port_caps resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_PD_PORT_CAPS, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + *power_role_cap = resp.pd_power_role_cap; + *try_power_role_cap = resp.pd_try_power_role_cap; + *data_role_cap = resp.pd_data_role_cap; + *port_location = resp.pd_port_location; + + return 0; +} + void google_chromeec_init(void) { google_chromeec_log_uptimeinfo(); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index d90d24c..8051486 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -299,4 +299,28 @@ */ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); +/** + * Get number of PD-capable USB ports from EC. + * + * @param *num_ports If successful, num_ports is the number + * of PD-capable USB ports according to the EC. + * @return 0 on success, -1 on error + */ +int google_chromeec_get_num_pd_ports(int *num_ports); + +/** + * Get role-based capabilities for a USB-PD port + * + * @param port Which port to get information about + * @param *power_role_cap The power-role capabillity of the port + * @param *try_power_role_cap The Try-power-role capability of the port + * @param *data_role_cap The data role capability of the port + * @param *port_location Location of the port on the device + * @return 0 on success, -1 on error + */ +int google_chromeec_get_pd_port_caps(int port, + enum ec_pd_power_role_caps *power_role_cap, + enum ec_pd_try_power_role_caps *try_power_role_cap, + enum ec_pd_data_role_caps *data_role_cap, + enum ec_pd_port_location *port_location); #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Gerrit-Change-Number: 38540 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/docker/Makefile: Correct help output
by Wim Vervoorn (Code Review) 01 Feb '20

01 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38649 ) Change subject: util/docker/Makefile: Correct help output ...................................................................... util/docker/Makefile: Correct help output The help output suggests clean-docker should be used to remove the docker coreboot containers and images. The Makefile actually supports the docker-clean target. Corrected the help output to reflect the actual Makefile target. BUG=N/A TEST=build Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38649/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 619de85..808a1d7 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -193,7 +193,7 @@ @echo " doc.coreboot.org - Build doc.coreboot.org container" @echo " clean-coreboot-containers - Remove all docker coreboot containers" @echo " clean-coreboot-images - Remove all docker coreboot images" - @echo " clean-docker - Remove docker coreboot containers & images" + @echo " docker-clean - Remove docker coreboot containers & images" @echo @echo "Commands for using docker images" @echo " docker-build-coreboot - Build coreboot under coreboot-sdk" -- To view, visit https://review.coreboot.org/c/coreboot/+/38649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Gerrit-Change-Number: 38649 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/t520: Switch to overridetree
by Peter Lemenkov (Code Review) 01 Feb '20

01 Feb '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37295 ) Change subject: mb/lenovo/t520: Switch to overridetree ...................................................................... mb/lenovo/t520: Switch to overridetree Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/Kconfig R src/mainboard/lenovo/t520/devicetree.cb D src/mainboard/lenovo/t520/variants/t520/devicetree.cb A src/mainboard/lenovo/t520/variants/t520/overridetree.cb A src/mainboard/lenovo/t520/variants/w520/overridetree.cb 5 files changed, 26 insertions(+), 183 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37295/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index a6183d9..6d31be2 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -51,9 +51,9 @@ string default "lenovo/t520" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb similarity index 98% rename from src/mainboard/lenovo/t520/variants/w520/devicetree.cb rename to src/mainboard/lenovo/t520/devicetree.cb index 8b2cbe7..49e57db 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -90,7 +90,7 @@ end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb deleted file mode 100644 index 0bfa18f..0000000 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ /dev/null @@ -1,180 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21cf inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d1 - end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x1f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21ce - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI-2-PCI bridge - - device pci 1f.0 on #LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x09" - register "config2" = "0xa0" - register "config3" = "0xc2" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus - device pci 1f.5 off end # IDE controller - device pci 1f.6 off end # Thermal controller - end - end -end diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb new file mode 100644 index 0000000..8016d10 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -0,0 +1,16 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end # LPC bridge + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller + end + end +end diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb new file mode 100644 index 0000000..a6f3738 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -0,0 +1,7 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Gerrit-Change-Number: 37295 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: improve indexed register helper macros
by Felix Held (Code Review) 01 Feb '20

01 Feb '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38577 ) Change subject: nb/intel/sandybridge: improve indexed register helper macros ...................................................................... nb/intel/sandybridge: improve indexed register helper macros Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38577/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index f5c1e41..ffc1d9f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -128,11 +128,11 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* Indexed register helper macros */ -#define Gz(r, z) ((r) + ((z) * 0x100)) -#define Ly(r, y) ((r) + ((y) * 4)) -#define Cx(r, x) ((r) + ((x) * 0x400)) -#define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) -#define GzLy(r, z, y) ((r) + ((z) * 0x100) + ((y) * 4)) +#define Gz(r, z) ((r) + ((z) << 8)) +#define Ly(r, y) ((r) + ((y) << 2)) +#define Cx(r, x) ((r) + ((x) << 10)) +#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) +#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) /* byte lane training register base addresses */ #define LANEBASE_B0 0x0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/38577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Gerrit-Change-Number: 38577 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: device/pnp_device: improve warning/error messages
by Felix Held (Code Review) 31 Jan '20

31 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38655 ) Change subject: device/pnp_device: improve warning/error messages ...................................................................... device/pnp_device: improve warning/error messages Explicitly state that the assignment is missing in the devicetree. In the case of the warnings, the missing assignments might not be an issue. Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38655/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 81aa889..dc921e7 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -129,12 +129,12 @@ (resource->index != PNP_IDX_IRQ0) && (resource->index != PNP_IDX_IRQ1)) printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " - "0x%010llx not assigned\n", dev_path(dev), + "0x%010llx not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); else printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, + "not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Gerrit-Change-Number: 38655 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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