Change in coreboot[master]: src/northbridge/intel/haswell/early_init.c: Fix type definition of de...

[Name of user not set (Code Review)]

Name of user not set #1002789 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: src/northbridge/intel/haswell/early_init.c: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

src/northbridge/intel/haswell/early_init.c: Fix type definition of dev in PCI_FUNC(dev)

The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN()
function. Tested on a T440P, and necessary on this board to enable the dGPU.
Will submit subsequent patches to enable dGPU.

Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan 
---
M src/northbridge/intel/haswell/early_init.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38722/1

diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 666bda2..6aad4a3 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -101,7 +101,7 @@
    }

pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
-	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev));
+	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));

/*
     * The PEG device is hidden while the MRC runs. This is because the
@@ -110,8 +110,8 @@
     * to these configurations.
     */
    pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0);
-	peg_hidden[PCI_FUNC(dev)] = true;
-	printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev));
+	peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+	printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
 }

void haswell_unhide_peg(void)

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: src/northbridge/intel/haswell/early_init.c: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

Patch Set 1: Code-Review+1

(3 comments)

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@7 
PS1, Line 7: src/northbridge/intel/haswell/early_init.c: Fix type definition of dev in PCI_FUNC(dev)
You can drop some boilerplate here, the prefix doesn't have to be a
full path, e.g.

nb/intel/haswell: Fix type of dev in PCI_FUNC(dev)

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@10 
PS1, Line 10: function
technically, it's a macro, not a function

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@11 
PS1, Line 11: Will submit subsequent patches to enable dGPU.
Please break lines before 72 chars.

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[Name of user not set (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38722

to look at the new patch set (#2).

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.

Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan 
---
M src/northbridge/intel/haswell/early_init.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38722/2

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[Name of user not set (Code Review)]

Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

Patch Set 2:

(3 comments)
> Patch Set 1: Code-Review+1
>
> (3 comments)

Comments fixed.

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@7 
PS1, Line 7: src/northbridge/intel/haswell/early_init.c: Fix type definition of dev in PCI_FUNC(dev)
> You can drop some boilerplate here, the prefix doesn't have to be a […]

Fixed

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@10 
PS1, Line 10: function
> technically, it's a macro, not a function

Updated commit message.

https://review.coreboot.org/c/coreboot/+/38722/1//COMMIT_MSG@11 
PS1, Line 11: Will submit subsequent patches to enable dGPU.
> Please break lines before 72 chars.

Ack

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[Name of user not set (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38722

to look at the new patch set (#3).

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.

Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan 
---
M src/northbridge/intel/haswell/early_init.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38722/3

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.

Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/haswell/early_init.c
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 666bda2..6aad4a3 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -101,7 +101,7 @@
    }

pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
-	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev));
+	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));

/*
     * The PEG device is hidden while the MRC runs. This is because the
@@ -110,8 +110,8 @@
     * to these configurations.
     */
    pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0);
-	peg_hidden[PCI_FUNC(dev)] = true;
-	printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev));
+	peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+	printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
 }

void haswell_unhide_peg(void)

Change in coreboot[master]: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38722 )

Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/481
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/480
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/479

Please note: This test is under development and might not be accurate at all!