Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38722 )
Change subject: nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev) ......................................................................
nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board to enable the dGPU.
Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2 Signed-off-by: Chris Morgan macromorgan@hotmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/early_init.c 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 666bda2..6aad4a3 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -101,7 +101,7 @@ }
pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); - printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev)); + printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
/* * The PEG device is hidden while the MRC runs. This is because the @@ -110,8 +110,8 @@ * to these configurations. */ pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0); - peg_hidden[PCI_FUNC(dev)] = true; - printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev)); + peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; + printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); }
void haswell_unhide_peg(void)