build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 )
Change subject: soc/intel/tigerlake: Add code for early tcss
......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37870/20/early_tcss.c
File early_tcss.c:
https://review.coreboot.org/c/coreboot/+/37870/20/early_tcss.c@81
PS20, Line 81: / * send USB connect request */
space prohibited after that '*' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/37870/20/early_tcss.c@81
PS20, Line 81: / * send USB connect request */
need consistent spacing around '*' (ctx:WxO)
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Brandon Breitenstein has uploaded a new patch set (#20) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 )
Change subject: soc/intel/tigerlake: Add code for early tcss
......................................................................
soc/intel/tigerlake: Add code for early tcss
In order for USB Type-C to be detected prior to loading Kernel
PMC IPC driver is needed to communicate with PMC in order to
correctly set the USB Mux settings. This patch is adding in
support for early detection of both USB and Display Port.
BUG=b:141608957
BRANCH=NONE
TEST: built and booted TGL U RVP
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
A early_tcss.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/early_tcss.c
4 files changed, 469 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/20
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Gerrit-MessageType: newpatchset
Brandon Breitenstein has uploaded a new patch set (#13) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37867 )
Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
......................................................................
src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
EC being the TCPM decides the mux configuration
after negotiating with the port partner on the
Type-C port. The APIS added here will give the
current essential mux state information for a
given port.
BUG=None
BRANCH=None
TEST= Tested boots from USB-TypeC flash drive
on TGLRVP
Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00
Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com>
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_commands.h
3 files changed, 116 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37867/13
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Gerrit-MessageType: newpatchset
Brandon Breitenstein has uploaded a new patch set (#15) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37871 )
Change subject: soc/intel/common/block: Enable PMC IPC driver
......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel
PMC IPC driver API is needed to send IPC commands to the PMC to update
connection/disconnection states.
BUG=b:141608957
BRANCH=none
TEST: built coreboot image and booted to Chrome OS
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 100 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37871/15
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 )
Change subject: sc7180: Add UART support
......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35500/26/src/soc/qualcomm/sc7180/q…
File src/soc/qualcomm/sc7180/qupv3_uart.c:
https://review.coreboot.org/c/coreboot/+/35500/26/src/soc/qualcomm/sc7180/q…
PS26, Line 65: #ifndef __VERSTAGE__
> This change is made by considering the case, if firmware is updated and to load the updated firmware […]
No, please don't do that. We don't want to reload the firmware in every stage just in case. If we ever ship an RW update that needs to fix QUP firmware (which I hope should be unlikely after shipping), we will address that explicitly (we need to anyway because we would need to re-run qupv3_fw_init() and then reload all the QUPs, right?).
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 )
Change subject: soc/intel/tigerlake: Add code for early tcss
......................................................................
Patch Set 19:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37870/19/early_tcss.c
File early_tcss.c:
https://review.coreboot.org/c/coreboot/+/37870/19/early_tcss.c@81
PS19, Line 81: / * send USB connect request */
space prohibited after that '*' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/37870/19/early_tcss.c@81
PS19, Line 81: / * send USB connect request */
need consistent spacing around '*' (ctx:WxO)
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