coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util: Modify LPDDR4 spd_tools to generate SPDs for ADL boards
by Amanda Hwang (Code Review) 17 Dec '20

17 Dec '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48526 ) Change subject: util: Modify LPDDR4 spd_tools to generate SPDs for ADL boards ...................................................................... util: Modify LPDDR4 spd_tools to generate SPDs for ADL boards Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. BUG=b:173132516 Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/gen_spd.go 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/48526/1 diff --git a/util/spd_tools/lp4x/gen_spd.go b/util/spd_tools/lp4x/gen_spd.go index e63ca8d..94cfb8d 100644 --- a/util/spd_tools/lp4x/gen_spd.go +++ b/util/spd_tools/lp4x/gen_spd.go @@ -29,11 +29,13 @@ PlatformTGL = 0 PlatformJSL = 1 + PlatformADL = 0 ) var platformMap = map[string]int { "TGL": PlatformTGL, "JSL": PlatformJSL, + "ADL": PlatformADL, } var currPlatform int -- To view, visit https://review.coreboot.org/c/coreboot/+/48526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84 Gerrit-Change-Number: 48526 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 17 Dec '20

17 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/gpio/gpio_dev.c: PS13: > I guess this could also be part of `gpio.c`. I had a reason to do that but I forgot what it was :'D I'll check that again -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 21:20:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 17 Dec '20

17 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/xeon_sp/cpx… PS13, Line 64: } > Please keep the braces and add them for the new path. If one path of an […] ack, will do that later, though -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 21:18:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Nico Huber (Code Review) 17 Dec '20

17 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 13: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/gpio/gpio_dev.c: PS13: I guess this could also be part of `gpio.c`. https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/48583/13/src/soc/intel/xeon_sp/cpx… PS13, Line 64: } Please keep the braces and add them for the new path. If one path of an if/else-if statement has braces, all should. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 20:45:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device + util/sconfig: introduce new device `gpio`
by Nico Huber (Code Review) 17 Dec '20

17 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48582 ) Change subject: device + util/sconfig: introduce new device `gpio` ...................................................................... Patch Set 6: Code-Review+1 Looks good. Will stall a bit, though, to give others time to have a look. -- To view, visit https://review.coreboot.org/c/coreboot/+/48582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Gerrit-Change-Number: 48582 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 20:35:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/hda_verb.c: Clarify mask usage
by Angel Pons (Code Review) 17 Dec '20

17 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48357 ) Change subject: soc/intel/common/hda_verb.c: Clarify mask usage ...................................................................... soc/intel/common/hda_verb.c: Clarify mask usage The `azalia_set_bits` will mask out all bits, so just use zero for clarity. The resulting behavior is the same in both cases. Change-Id: I27777f1e836fa973859629d48964060bec02c87a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48357/1 diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index ecf5a51..5a4b467 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -24,7 +24,7 @@ write8(base + HDA_STATESTS_REG, 0xf); /* Turn off the link and poll RESET# bit until it reads back as 0 */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Turn on the link and poll RESET# bit until it reads back as 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27777f1e836fa973859629d48964060bec02c87a Gerrit-Change-Number: 48357 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
by Nico Huber (Code Review) 17 Dec '20

17 Dec '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48325 ) Change subject: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration ...................................................................... soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 43f272e..b51c73c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -56,8 +56,6 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "PmConfigPciClockRun" = "1" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 6bdfcaf..8ad7852 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -10,7 +10,6 @@ register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - register "PmConfigPciClockRun" = "1" register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" # VR Settings Configuration for 2 Domains diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c9519cd..ef16f38 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -338,7 +338,6 @@ params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; - params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f4744c9..7d9d934 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -377,11 +377,6 @@ } PmConfigSlpAMinAssert; /* - * This member describes whether or not the PCI ClockRun feature of PCH - * should be enabled. Values 0: Disabled, 1: Enabled - */ - u8 PmConfigPciClockRun; - /* * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, * 1: Enabled */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Gerrit-Change-Number: 48325 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
by Nico Huber (Code Review) 17 Dec '20

17 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48325 ) Change subject: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Gerrit-Change-Number: 48325 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 20:05:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add GPIO to drobit support
by Tim Wawrzynczak (Code Review) 17 Dec '20

17 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48497 ) Change subject: mb/google/volteer: Add GPIO to drobit support ...................................................................... Patch Set 4: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/48497/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/drobit/gpio.c: https://review.coreboot.org/c/coreboot/+/48497/4/src/mainboard/google/volte… PS4, Line 144: use tab instead of spaces please -- To view, visit https://review.coreboot.org/c/coreboot/+/48497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Gerrit-Change-Number: 48497 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 19:56:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Update SPD table for drobit
by Tim Wawrzynczak (Code Review) 17 Dec '20

17 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48496 ) Change subject: mb/google/volteer: Update SPD table for drobit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f Gerrit-Change-Number: 48496 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Dec 2020 19:37:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020