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Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the CCI frequency
by Yidi Lin (Code Review) 28 Jan '21

28 Jan '21

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46411 to review the following change. Change subject: HACK: soc/mediatek: Add function to raise the CCI frequency ...................................................................... HACK: soc/mediatek: Add function to raise the CCI frequency Implement mt_pll_raise_cci_freq() in MT8192 to raise the frequency. usage: mt_pll_raise_cci_freq(1400UL * MHz); note: Obviously, little/big/cci raise_freq() could be merged. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 54b12e8..59a70ff 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -60,6 +60,7 @@ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); void mt_pll_raise_ca76_freq(u32 freq); +void mt_pll_raise_cci_freq(u32 freq); enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index cd65d25..9b13398 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -573,3 +573,30 @@ /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch cci clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, + MCU_MUX_SRC_DIV_PLL1); + + /* disable ccipll frequency output */ + clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); + + /* raise ccipll frequency */ + pll_set_rate(&plls[APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch cci clock source back to ccipll */ + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, + MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Gerrit-Change-Number: 46411 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/emulation: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46077 ) Change subject: mb/emulation: Convert to ASL 2.0 syntax ...................................................................... mb/emulation: Convert to ASL 2.0 syntax Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl M src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl M src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl M src/mainboard/emulation/qemu-i440fx/acpi/isa.asl 4 files changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46077/1 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 3969f25..1805f79 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -14,20 +14,20 @@ // _MAT method - create an madt APIC buffer // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) + Local0 = DerefOf (CPON [Arg0]) // Local1 = Buffer (in madt APIC form) to return - Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) + Local1 = Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0} // Update the processor id, Local APIC id, and enable/disable status - Store(Arg0, Index(Local1, 2)) - Store(Arg0, Index(Local1, 3)) - Store(Local0, Index(Local1, 4)) + Local1 [2] = Arg0 + Local1 [3] = Arg0 + Local1 [4] = Local0 Return (Local1) } Method(CPST, 1, NotSerialized) { // _STA method - return ON status of cpu // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) + Local0 = DerefOf (CPON [Arg0]) If (Local0) { Return (0xF) } Else { @@ -46,35 +46,35 @@ } Method(PRSC, 0) { // Local5 = active CPU bitmap - Store(PRS, Local5) + Local5 = PRS // Local2 = last read byte from bitmap - Store(Zero, Local2) + Local2 = 0 // Local0 = Processor ID / APIC ID iterator - Store(Zero, Local0) - While (LLess(Local0, SizeOf(CPON))) { + Local0 = 0 + While (Local0 < SizeOf(CPON)) { // Local1 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Local0)), Local1) - If (And(Local0, 0x07)) { + Local1 = DerefOf (CPON [Local0]) + If (Local0 & 0x07) { // Shift down previously read bitmap byte - ShiftRight(Local2, 1, Local2) + Local2 >>= 1 } Else { // Read next byte from CPU bitmap - Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2) + Local2 = DerefOf (Local5 [Local0 >> 3]) } // Local3 = active state for this cpu - Store(And(Local2, 1), Local3) + Local3 = Local2 & 1 - If (LNotEqual(Local1, Local3)) { + If (Local1 != Local3) { // State change - update CPON with new state - Store(Local3, Index(CPON, Local0)) + CPON [Local0] = Local3 // Do CPU notify - If (LEqual(Local3, 1)) { + If (Local3 == 1) { NTFY(Local0, 1) } Else { NTFY(Local0, 3) } } - Increment(Local0) + Local0++ } } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl index 5fe06b4..ff09db4 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl @@ -17,12 +17,12 @@ Method(DBUG, 1) { ToHexString(Arg0, Local0) ToBuffer(Local0, Local0) - Subtract(SizeOf(Local0), 1, Local1) - Store(Zero, Local2) - While (LLess(Local2, Local1)) { - Store(DerefOf(Index(Local0, Local2)), DBGB) - Increment(Local2) + Local1 = SizeOf(Local0) - 1 + Local2 = 0 + While (Local2 < Local1) { + DBGB = DerefOf( Local0 [Local2]) + Local2++ } - Store(0x0A, DBGB) + DBGB = 0x0A } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index 51e4f74..da670cf 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -14,13 +14,13 @@ PRD, 32, } Method(_STA, 0, NotSerialized) { - Store(VEND, Local0) - Store(PRD, Local1) - ShiftRight(Local0, 16, Local0) - If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) { + Local0 = VEND + Local1 = PRD + Local0 >>= 16 + If ((Local0 == 0) || (Local0 == 0xffff)) { Return (0x0) } - If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) { + If ((Local1 == 0) || (Local1 > 100000000)) { Return (0x0) } Return (0x0F) diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl index 38374a1..a547c93 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl @@ -37,8 +37,8 @@ Device(FDC0) { Name(_HID, EisaId("PNP0700")) Method(_STA, 0, NotSerialized) { - Store(FDEN, Local0) - If (LEqual(Local0, 0)) { + Local0 = FDEN + If (Local0 == 0) { Return (0x00) } Else { Return (0x0F) @@ -55,8 +55,8 @@ Device(LPT) { Name(_HID, EisaId("PNP0400")) Method(_STA, 0, NotSerialized) { - Store(LPEN, Local0) - If (LEqual(Local0, 0)) { + Local0 = LPEN + If (Local0 == 0) { Return (0x00) } Else { Return (0x0F) @@ -72,8 +72,8 @@ Name(_HID, EisaId("PNP0501")) Name(_UID, 0x01) Method(_STA, 0, NotSerialized) { - Store(CAEN, Local0) - If (LEqual(Local0, 0)) { + Local0 = CAEN + If (Local0 == 0) { Return (0x00) } Else { Return (0x0F) @@ -89,8 +89,8 @@ Name(_HID, EisaId("PNP0501")) Name(_UID, 0x02) Method(_STA, 0, NotSerialized) { - Store(CBEN, Local0) - If (LEqual(Local0, 0)) { + Local0 = CBEN + If (Local0 == 0) { Return (0x00) } Else { Return (0x0F) -- To view, visit https://review.coreboot.org/c/coreboot/+/46077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae Gerrit-Change-Number: 46077 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46163 ) Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ...................................................................... mb/emulation/qemu-q35: Convert to ASL 2.0 syntax Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46163/1 diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a9c96be..274cccb 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -45,31 +45,31 @@ CreateDWordField(Arg3, 0, CDW1) // Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { // Create DWORD-addressable fields from the Capabilities Buffer CreateDWordField(Arg3, 4, CDW2) CreateDWordField(Arg3, 8, CDW3) // Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) + SUPP = CDW2 + CTRL = CDW3 // Always allow native PME, AER (no dependencies) // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) + CTRL &= 0x1D - If (LNotEqual(Arg1, One)) { + If (Arg1 != 1) { // Unknown revision - Or(CDW1, 0x08, CDW1) + CDW1 |= 0x08 } - If (LNotEqual(CDW3, CTRL)) { + If (CDW3 != CTRL) { // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) + CDW1 |= 0x10 } // Update DWORD3 in the buffer - Store(CTRL, CDW3) + CDW3 = CTRL } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID + CDW1 |= 4 // Unrecognized UUID } Return (Arg3) } @@ -144,7 +144,7 @@ /* Zero => PIC mode, One => APIC Mode */ Name(\PICF, Zero) Method(\_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) + \PICF = Arg0 } Scope(\_SB) { @@ -268,7 +268,7 @@ section 6.2.8.1 */ /* Note: we provide the same info as the PCI routing table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { + If (\PICF == 0) { Return (PRTP) } Else { Return (PRTA) @@ -291,7 +291,7 @@ Method(IQST, 1, NotSerialized) { // _STA method - get status - If (And(0x80, Arg0)) { + If (0x80 & Arg0) { Return (0x09) } Return (0x0B) @@ -302,7 +302,7 @@ Interrupt(, Level, ActiveHigh, Shared) { 0 } }) CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) + PRRI = Arg0 & 0x0F Return (PRR0) } @@ -319,14 +319,14 @@ Return (IQST(reg)) \ } \ Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ + reg |= 0x80 \ } \ Method(_CRS, 0, NotSerialized) { \ Return (IQCR(reg)) \ } \ Method(_SRS, 1, NotSerialized) { \ CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ + reg = PRRI \ } \ } -- To view, visit https://review.coreboot.org/c/coreboot/+/46163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Gerrit-Change-Number: 46163 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: arch/x86: Remove C_ENV_BOOTBLOCK_SIZE
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47600 ) Change subject: arch/x86: Remove C_ENV_BOOTBLOCK_SIZE ...................................................................... arch/x86: Remove C_ENV_BOOTBLOCK_SIZE With top-aligned bootblock this is no longer globally needed. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/config.facebook_fbg1701.mboot_vboot M src/arch/x86/Kconfig M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_m/Kconfig M src/mainboard/aopen/dxplplusu/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/portwell/m107/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/southbridge/intel/i82371eb/bootblock.c 25 files changed, 4 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47600/1 diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index b372bbe..34d349a 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,5 +1,4 @@ CONFIG_VENDOR_FACEBOOK=y -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f4ddd20..4213041 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -179,11 +179,6 @@ hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE -# 64KiB default bootblock size -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x10000 - # Default address romstage is to be linked at config ROMSTAGE_ADDR hex diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 1ccfa5d..3c5a1ca 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -38,10 +38,6 @@ hex default 0x4000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - config ENABLE_MRC_CACHE bool "Use cached memory configuration" default n diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index e626ef1..a13385a 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -38,10 +38,6 @@ hex default 0x4000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 2b6deb6..841b796 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -30,9 +30,4 @@ hex default 0x1000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x4000 if BOOTBLOCK_CONSOLE - default 0x2000 - endif diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72..1b930de 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -10,10 +10,6 @@ select SSE select SETUP_XIP_CACHE -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x4000 - config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 8b1f5ed..32eedb6 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -22,8 +22,4 @@ hex default 0x2000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - endif diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 0036915..4ee9b73 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -26,8 +26,4 @@ int default 4 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x4000 - endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 9187b05..8027946 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -64,10 +64,6 @@ hex default 0x90000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x4000 - config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..5881ab1 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -76,10 +76,6 @@ bool default n -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x4000 - config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 0f23ed2..85d79a4 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -64,10 +64,6 @@ bool "TPM Setup in RAMSTAGE" default n -config C_ENV_BOOTBLOCK_SIZE - hex "C Bootblock Size" - default 0x4000 - config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST bool default y diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index bc06151..3935b38 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -63,8 +63,4 @@ bool default y -config C_ENV_BOOTBLOCK_SIZE - hex "C Bootblock Size" - default 0x4000 - endif # BOARD_PORTWELL_M107 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3917fea..517f954 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -168,10 +168,6 @@ default 133 # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - # This SoC does not map SPI flash like many previous SoC. Therefore we provide # a custom media driver that facilitates mapping config X86_TOP4G_BOOTMEDIA_MAP diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index edbc6fd..987a689 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -50,10 +50,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7b9b88b..ac1251d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -288,10 +288,6 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 89bbbb0..d094fba 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -149,10 +149,6 @@ hex "MMIO base address for UART" default 0xd4000000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - config DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" depends on !FSP_CAR diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52e9a74..7913ff2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -176,10 +176,6 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 294f19f8..9be1145 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -182,10 +182,6 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index f8e967b..0b57b7e 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -213,10 +213,6 @@ hex default 0x4000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 - ##### # Test support ##### diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ce46d06..a263cbe1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -118,10 +118,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config EXCLUDE_NATIVE_SD_INTERFACE bool default n diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 507f871..100a49a 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -199,10 +199,6 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3d3e803..67b2315 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -92,10 +92,6 @@ hex default 0x80000000 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config HEAP_SIZE hex default 0x80000 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 28e7b83..09eb53d 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -55,10 +55,6 @@ hex default 0x7C00 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config HEAP_SIZE hex default 0x80000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 2e0778e..cf4fc68 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -51,10 +51,6 @@ hex default 0x7C00 -config C_ENV_BOOTBLOCK_SIZE - hex - default 0xC000 - config HEAP_SIZE hex default 0x80000 diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 05b2d2c..6a1f654 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -22,11 +22,10 @@ } /* TODO: Does not need to happen before console init. */ -/* The whole rom is not accessible before this so limit - the bootblock size. */ -#if CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000 -#error "CONFIG_C_ENV_BOOTBLOCK_SIZE needs to be below 64KiB" -#endif +/* + * TODO: The whole rom is not accessible before this so bootblock size + * is limited to 64 KiB. This should be asserted build-time, but it is not. + */ void bootblock_early_southbridge_init(void) { u16 reg16; -- To view, visit https://review.coreboot.org/c/coreboot/+/47600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Gerrit-Change-Number: 47600 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: arch/x86: Top-align .text in bootblock
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47971 ) Change subject: arch/x86: Top-align .text in bootblock ...................................................................... arch/x86: Top-align .text in bootblock Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/bootblock.ld 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/47971/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f4ddd20..1ec0390 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -184,6 +184,9 @@ hex default 0x10000 +config FIXED_BOOTBLOCK_SIZE + bool + # Default address romstage is to be linked at config ROMSTAGE_ADDR hex diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index bb22413..52bccfc 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -14,6 +14,11 @@ SECTIONS { . = _ebootblock - CONFIG_C_ENV_BOOTBLOCK_SIZE; +#if !CONFIG(FIXED_BOOTBLOCK_SIZE) + . = BOOTBLOCK_TOP - PROGRAM_SZ; + . = ALIGN(16); +#endif + _bootblock = .; INCLUDE "bootblock/lib/program.ld" @@ -32,6 +37,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ + PROGRAM_SZ = SIZEOF(.text) + 32; EARLYASM_SZ = SIZEOF(.init) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16); . = ID_SECTION; -- To view, visit https://review.coreboot.org/c/coreboot/+/47971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a Gerrit-Change-Number: 47971 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: arch/x86: Top-align .init in bootblock
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47970 ) Change subject: arch/x86: Top-align .init in bootblock ...................................................................... arch/x86: Top-align .init in bootblock Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock.ld M src/arch/x86/memlayout.ld M src/lib/program.ld 3 files changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/47970/1 diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index a0da25e..bb22413 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -12,8 +12,27 @@ #endif SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + . = _ebootblock - CONFIG_C_ENV_BOOTBLOCK_SIZE; + + _bootblock = .; + + INCLUDE "bootblock/lib/program.ld" + + . = ID_SECTION - EARLYASM_SZ; + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); + BOOTBLOCK_TOP = .; + .init (.) : { + *(.init._start); + *(.init); + KEEP(*(.id.keep)); + } + + /* + * Allocation reserves extra space here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + EARLYASM_SZ = SIZEOF(.init) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16); . = ID_SECTION; .flashrom_id (.): { @@ -34,4 +53,9 @@ . = 15; BYTE(0x00); } + _ebootblock = .; } + +_bogus1 = ASSERT(_bootblock & 0x80000000, "_bootblock too low, invalid ld script"); +_bogus2 = ASSERT(_start16bit & 0x80000000, "_start16bit too low, invalid ld script"); +_bogus3 = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 52694fa..a0b0f53 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,8 +28,6 @@ #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, - CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" diff --git a/src/lib/program.ld b/src/lib/program.ld index 98e88e2..b825f4f 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -15,9 +15,11 @@ _text = .; *(.text._start); *(.text.stage_entry); +#if !(ENV_X86 && ENV_BOOTBLOCK) KEEP(*(.id.keep)); *(.init._start); *(.init); +#endif *(.text); *(.text.*); -- To view, visit https://review.coreboot.org/c/coreboot/+/47970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Gerrit-Change-Number: 47970 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: cpu/x86: Link entry32.inc
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47969 ) Change subject: cpu/x86: Link entry32.inc ...................................................................... cpu/x86: Link entry32.inc TBD: Address SPDX license header mismatch Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47969/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3727165..58de291 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -101,8 +101,6 @@ bootblock-y += gdt_init.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -bootblock-y += bootblock_crt0.S - ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) else diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc deleted file mode 100644 index b28fa2f..0000000 --- a/src/cpu/x86/32bit/entry32.inc +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* For starting coreboot in protected mode */ - -#include <arch/rom_segs.h> -#include <cpu/x86/post_code.h> - - .code32 -/* - * When we come here we are in protected mode. - * NOTE aligned to 4 so that we are sure that the prefetch - * cache will be reloaded. - */ - .align 4 - -.globl __protected_start -__protected_start: - /* Save the BIST value */ - movl %eax, %ebp - -#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) - post_code(POST_ENTER_PROTECTED_MODE) -#endif - - movw $ROM_DATA_SEG, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Restore the BIST value to %eax */ - movl %ebp, %eax diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index f1bca0e..33a65e7 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -5,6 +5,7 @@ subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm +bootblock-y += entry32.S bootblock-y += entry16.S bootblock-y += reset16.S diff --git a/src/arch/x86/bootblock_crt0.S b/src/cpu/x86/entry32.S similarity index 61% rename from src/arch/x86/bootblock_crt0.S rename to src/cpu/x86/entry32.S index d151feb..d428fd4 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/cpu/x86/entry32.S @@ -1,4 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* For starting coreboot in protected mode */ + /* * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. @@ -8,15 +11,38 @@ * */ +#include <arch/rom_segs.h> #include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> .section ".init", "ax", @progbits + .code32 /* - * Include the old code for reset vector and protected mode entry. That code has - * withstood the test of time. + * When we come here we are in protected mode. + * NOTE aligned to 4 so that we are sure that the prefetch + * cache will be reloaded. */ -#include <cpu/x86/32bit/entry32.inc> + .align 4 + +.globl __protected_start +__protected_start: + /* Save the BIST value */ + movl %eax, %ebp + +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) + post_code(POST_ENTER_PROTECTED_MODE) +#endif + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Restore the BIST value to %eax */ + movl %ebp, %eax #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) -- To view, visit https://review.coreboot.org/c/coreboot/+/47969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Gerrit-Change-Number: 47969 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: cpu/x86: Link reset16.inc
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47968 ) Change subject: cpu/x86: Link reset16.inc ...................................................................... cpu/x86: Link reset16.inc Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_crt0.S M src/cpu/x86/Makefile.inc R src/cpu/x86/reset16.S 3 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47968/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index a457978..d151feb 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -16,7 +16,6 @@ * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 8862e87..f1bca0e 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,6 +6,7 @@ subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm bootblock-y += entry16.S +bootblock-y += reset16.S additional-dirs += $(obj)/cpu/x86 diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/reset16.S similarity index 97% rename from src/cpu/x86/16bit/reset16.inc rename to src/cpu/x86/reset16.S index b5abb3d..3858014 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/reset16.S @@ -12,4 +12,3 @@ * instead of the weird 16 bit relocations that binutils does not * handle consistently between versions because they are used so rarely. */ - .previous -- To view, visit https://review.coreboot.org/c/coreboot/+/47968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Gerrit-Change-Number: 47968 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cpu/x86: Link entry16.inc
by Kyösti Mälkki (Code Review) 28 Jan '21

28 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47967 ) Change subject: cpu/x86: Link entry16.inc ...................................................................... cpu/x86: Link entry16.inc TBD: Address SPDX license header Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_crt0.S M src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry16.S M src/lib/program.ld 5 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47967/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 10a8763..a457978 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -16,7 +16,6 @@ * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 873a809..b28fa2f 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -13,6 +13,7 @@ */ .align 4 +.globl __protected_start __protected_start: /* Save the BIST value */ movl %eax, %ebp diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..8862e87 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -5,6 +5,8 @@ subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm +bootblock-y += entry16.S + additional-dirs += $(obj)/cpu/x86 SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/entry16.S similarity index 94% rename from src/cpu/x86/16bit/entry16.inc rename to src/cpu/x86/entry16.S index 5e90da1..7043aab 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/entry16.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* * This software and ancillary information (herein called SOFTWARE) * called LinuxBIOS is made available under the terms described here. @@ -28,10 +30,11 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. +.section ".init._start", "ax", @progbits + +/* Symbol _start16bit must reachable from the reset vector, and be aligned to + * 4kB to start AP CPUs with Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/lib/program.ld b/src/lib/program.ld index 457a20a..98e88e2 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -16,6 +16,7 @@ *(.text._start); *(.text.stage_entry); KEEP(*(.id.keep)); + *(.init._start); *(.init); *(.text); *(.text.*); -- To view, visit https://review.coreboot.org/c/coreboot/+/47967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Gerrit-Change-Number: 47967 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: soc/intel/apollolake: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 27 Jan '21

27 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46235 ) Change subject: soc/intel/apollolake: Convert to ASL 2.0 syntax ...................................................................... soc/intel/apollolake: Convert to ASL 2.0 syntax Change-Id: Ifc400433323630393566899dbeb5b0fac1a4bd00 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl 7 files changed, 87 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46235/1 diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 1fe58e1..f5795ef 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -25,8 +25,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM0_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -55,8 +55,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM1_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -85,8 +85,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM2_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -115,8 +115,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM3_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) } @@ -137,9 +137,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (\_SB.GPC0 (Local2), Local1) - Or (Local1, PAD_CFG0_TX_STATE, Local1) + Local2 = Arg0 + Local1 = \_SB.GPC0 (Local2) + Local1 |= PAD_CFG0_TX_STATE \_SB.SPC0 (Local2, Local1) } @@ -151,9 +151,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (\_SB.GPC0 (Local2), Local1) - And (Local1, Not (PAD_CFG0_TX_STATE), Local1) + Local2 = Arg0 + Local1 = \_SB.GPC0 (Local2) + Local1 &= ~PAD_CFG0_TX_STATE \_SB.SPC0 (Local2, Local1) } } diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl index 0ec9140..b7d14cc 100644 --- a/src/soc/intel/apollolake/acpi/gpiolib.asl +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -6,7 +6,7 @@ Method (GPC0, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -19,19 +19,19 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW0 register */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } /* Get Pad Configuration DW1 register value */ Method (GPC1, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Add (Arg0, 0x4), Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field (PDW1, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -44,12 +44,12 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW1 register */ - Store (Add (Arg0, 0x4), Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field(PDW1, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } /* Get DW0 address of a given pad */ @@ -57,11 +57,9 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (0, Local1) - Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS), - Local1, Local1) - Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply ( - GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1) + Local1 = 0 + Local1 |= ((Arg0 << 16) | CONFIG_PCR_BASE_ADDRESS) + Local1 |= (PAD_CFG_BASE + (Arg1 * GPIO_NUM_PAD_CFG_REGS * 4)) Return (Local1) } @@ -69,7 +67,7 @@ Method (CHSA, 0x1, Serialized) { /* Arg0 - GPIO pad offset relative to the community */ - Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1) + Local1 = HOSTSW_OWN_REG_0 + ((Arg0 / 32) * 4) Return (Local1) } @@ -78,10 +76,10 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (CHSA (Arg1), Local1) + Local1 = CHSA (Arg1) OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + (CONFIG_PCR_BASE_ADDRESS, (Arg0 << 16)), Local1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } @@ -94,13 +92,13 @@ /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ /* Arg2 - Value for Host own register */ - Store (CHSA (Arg1), Local1) + Local1 = CHSA (Arg1) OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + (CONFIG_PCR_BASE_ADDRESS, (Arg0 << 16)), Local1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } - Store (Arg2, TEMP) + TEMP = Arg2 } } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1450983..df99154 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -78,12 +78,12 @@ CreateDwordField (MCRS, PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, PMIN) + PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 /* Read MMCONF base */ - And(\_SB.PCI0.MCHC.MCNF, 0xF0000000, PMAX) + PMAX = \_SB.PCI0.MCHC.MCNF & 0xF0000000 /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + PLEN = (PMAX - PMIN) + 1 /* Find GFX resource area in GCRS */ CreateDwordField(MCRS, STOM._MIN, GMIN) @@ -91,25 +91,25 @@ CreateDwordField(MCRS, STOM._LEN, GLEN) /* Read BGSM */ - And(\_SB.PCI0.MCHC.BGSM, 0xFFF00000, GMIN) + GMIN = \_SB.PCI0.MCHC.BGSM & 0xFFF00000 /* Read TOLUD */ - And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + GMAX = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 + GMAX-- + GLEN = (GMAX - GMIN) + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) - Subtract (Add (MMIN, MLEN), 1, MMAX) + MLEN = A4GS + MMIN = A4GB + MMAX = (MMIN - MLEN) +1 } Return (MCRS) diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index c3f862e..b23c541 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -29,19 +29,17 @@ * Arg2 - Function Index */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { @@ -56,13 +54,13 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } } diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index f0f49f3..daa77e2 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -39,8 +39,8 @@ /* Define the PowerResource for PCIe slot */ Method (_STA, 0, Serialized) { - Store (PDS, PDST) - If (LEqual (PDS, 1)) { + PDST = PDS + If (PDS == 1) { Return (0xf) } Else { Return (0) @@ -49,7 +49,7 @@ Method (_ON, 0, Serialized) { - If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + If ((PDST == 1) && (\PRT0 != 0)) { /* Enter this condition if device * is connected */ @@ -57,25 +57,25 @@ /* De-assert PERST */ \_SB.PCI0.PRDA (\PRT0) - Store (0, BDQA) /* Set BLKDQDA to 0 */ - Store (0, BPLL) /* Set BLKPLLEN to 0 */ + BDQA = 0 /* Set BLKDQDA to 0 */ + BPLL = 0 /* Set BLKPLLEN to 0 */ /* Set L23_Rdy to Detect Transition * (L23R2DT) */ - Store (1, L23R) + L23R = 1 Sleep (16) - Store (0, Local0) + Local0 = 0 /* Delay for transition Detect * and link to train */ While (L23R) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) - Increment (Local0) + Local0++ } } /* End PDS condition check */ } @@ -83,22 +83,22 @@ Method (_OFF, 0, Serialized) { /* Set L23_Rdy Entry Request (L23ER) */ - If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + If ((PDST == 1) && (\PRT0 != 0)) { /* enter this condition if device * is connected */ - Store (1, L23E) + L23E = 1 Sleep (16) - Store (0, Local0) + Local0 = 0 While (L23E) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) - Increment (Local0) + Local0++ } - Store (1, BDQA) /* Set BLKDQDA to 1 */ - Store (1, BPLL) /* Set BLKPLLEN to 1 */ + BDQA = 1 /* Set BLKDQDA to 1 */ + BPLL = 1 /* Set BLKPLLEN to 1 */ /* Assert PERST */ \_SB.PCI0.PRAS (\PRT0) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 7611a2d..7b0e497 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -30,15 +30,15 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) + IBAS = PMC_BAR0 CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) + MDBA = MCH_BASE_ADDRESS + MAILBOX_DATA CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) + MIBA = MCH_BASE_ADDRESS + MAILBOX_INTF CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (SRAM_BASE_0, SBAS) + SBAS = SRAM_BASE_0 Return (^RBUF) } diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index 1ee70ad..f7de2dc 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -4,8 +4,7 @@ /* 0xD6- is the port address */ /* 0x600- is the dynamic clock gating control register offset (GENR) */ OperationRegion (SBMM, SystemMemory, - Or ( Or (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18) + (CONFIG_PCR_BASE_ADDRESS | (0xD6 << PCR_PORTID_SHIFT) | 0x0600), 0x18) Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, @@ -23,10 +22,10 @@ */ Method (SCPG, 2, Serialized) { - if (LEqual(Arg0, 0x1)) { - Or (^GENR, Arg1, ^GENR) - } ElseIf (LEqual(Arg0, 0x0)){ - And (^GENR, Arg1, ^GENR) + if (Arg0 == 0x1) { + ^GENR |= Arg1 + } ElseIf (Arg0 == 0x0){ + ^GENR &= Arg1 } } @@ -44,13 +43,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delays in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -58,7 +57,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -118,14 +117,14 @@ Method (_INI, 0) { /* Check SDCard CD port is valid */ - If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + If ((\SCDP != 0) && (\SCDO != 0)) { /* Store DW0 address of SD_CD */ - Store (GDW0 (\SCDP, \SCDO), SCD0) + SCD0 = GDW0 (\SCDP, \SCDO) /* Get the current SD_CD ownership */ - Store (\_SB.GHO (\SCDP, \SCDO), Local0) + Local0 = \_SB.GHO (\SCDP, \SCDO) /* Set host ownership as GPIO in HOSTSW_OWN reg */ - Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0) + Local0 |= 1 << (\SCDO % 32) \_SB.SHO (\SCDP, \SCDO, Local0) } } @@ -133,20 +132,20 @@ Method (_PS0, 0, NotSerialized) { /* Check SDCard CD port is valid */ - If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + If ((\SCDP != 0) && (\SCDO != 0)) { /* Store DW0 into local0 to get rxstate of GPIO */ - Store (\_SB.GPC0 (SCD0), Local0) + Local0 = \_SB.GPC0 (SCD0) /* Extract rxstate [bit 1] of sdcard card detect pin */ - And (Local0, PAD_CFG0_RX_STATE, Local0) + Local0 &= PAD_CFG0_RX_STATE /* If the sdcard is present, rxstate is low. * If sdcard is not present, rxstate is High. * Write the inverted value of rxstate to GRR3. */ - If (LEqual (Local0, 0)) { - Store (1, ^^GRR3) + If (Local0 == 0) { + ^^GRR3 = 1 } Else { - Store (0, ^^GRR3) + ^^GRR3 = 0 } Sleep (2) } @@ -155,7 +154,7 @@ Method (_PS3, 0, NotSerialized) { /* Clear GRR3 to Power Gate SD Controller */ - Store (0, ^^GRR3) + ^^GRR3 = 0 } Device (CARD) -- To view, visit https://review.coreboot.org/c/coreboot/+/46235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc400433323630393566899dbeb5b0fac1a4bd00 Gerrit-Change-Number: 46235 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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