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Change in coreboot[master]: soc/intel/broadwell: Clean up cosmetics
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47024 ) Change subject: soc/intel/broadwell: Clean up cosmetics ...................................................................... soc/intel/broadwell: Clean up cosmetics To ease merging with Lynxpoint, define the port mask. Also simplify several register operations and drop outdated `Set timings` comment. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6fd5516b33fe4c3d7099651ec452359030b8d509 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 16 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47024/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index f63d4ba..3ed136b 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -13,6 +13,8 @@ #include "rcba.h" #include "sata.h" +#define SATA_PORT_MASK 0x0f + static inline u32 sir_read(struct device *dev, int idx) { pci_write_config32(dev, SATA_SIRI, idx); @@ -43,13 +45,12 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); - /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0xf; + reg16 &= ~SATA_PORT_MASK; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); @@ -61,13 +62,12 @@ reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ pci_write_config32(dev, 0x98, reg32); - /* Setup register 9Ch */ - reg16 = (1 << 5); /* BWG step 12 */ - pci_write_config16(dev, 0x9c, reg16); + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); /* SATA Initialization register */ reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0xf) << 24; + reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); @@ -95,7 +95,7 @@ } else { /* Enable DEVSLP */ reg32 = read32(abar + 0x24); - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + reg32 |= (1 << 5) | (1 << 4)|(1 << 3)|(1 << 2); write32(abar + 0x24, reg32); for (port = 0; port < 4; port++) { @@ -112,10 +112,10 @@ */ reg32 = RCBA32(0x3a84); /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) reg32 |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) reg32 |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = reg32; @@ -239,29 +239,22 @@ reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); - reg32 = pci_read_config32(dev, 0x98); - reg32 |= 1 << 29; - pci_write_config32(dev, 0x98, reg32); + pci_or_config32(dev, 0x98, 1 << 29); /* Register Lock */ - reg32 = pci_read_config32(dev, 0x9c); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x9c, reg32); + pci_or_config32(dev, 0x9c, 1 << 31); } -/* - * Set SATA controller mode early so the resource allocator can - * properly assign IO/Memory resources for the controller. - */ static void sata_enable(struct device *dev) { /* Get the chip configuration */ const struct soc_intel_broadwell_pch_config *config = config_of(dev); - u16 map = 0x0060; - map |= (config->sata_port_map ^ 0xf) << 8; - - pci_write_config16(dev, 0x90, map); + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd5516b33fe4c3d7099651ec452359030b8d509 Gerrit-Change-Number: 47024 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Align memmap.h with Haswell
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46956 ) Change subject: soc/intel/broadwell: Align memmap.h with Haswell ...................................................................... soc/intel/broadwell: Align memmap.h with Haswell This is merely to reduce cosmetic differences. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I473336a77179a3d1d26933f481abded49e9f0864 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi/gpio.asl M src/soc/intel/broadwell/pch/acpi/lpc.asl M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/gpio.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/rcba.h M src/soc/intel/broadwell/pch/smbus.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pei_data.c 21 files changed, 82 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46956/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index fc41259..db9aced 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); return current; } diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index b18ec78..d4f6a1b 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,7 +9,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 607178c..8b63ec7 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -174,11 +174,11 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) - Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) - Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x4000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x8000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x1000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x1000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) }) diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index af5ba14..31786f3 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,9 +11,9 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(HOST_BRIDGE, EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index dfce0fd..df3a7550 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -85,9 +85,9 @@ /* MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + (x))) /* Memory controller characteristics */ #define NUM_CHANNELS 2 diff --git a/src/soc/intel/broadwell/memmap.h b/src/soc/intel/broadwell/memmap.h index 241569e..e69b88e 100644 --- a/src/soc/intel/broadwell/memmap.h +++ b/src/soc/intel/broadwell/memmap.h @@ -3,17 +3,9 @@ #ifndef _BROADWELL_IOMAP_H_ #define _BROADWELL_IOMAP_H_ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - -#define MCH_BASE_ADDRESS 0xfed10000 -#define MCH_BASE_SIZE 0x8000 - -#define DMI_BASE_ADDRESS 0xfed18000 -#define DMI_BASE_SIZE 0x1000 - -#define EP_BASE_ADDRESS 0xfed19000 -#define EP_BASE_SIZE 0x1000 +#define DEFAULT_MCHBAR 0xfed10000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 @@ -21,10 +13,7 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x4000 - -#define HPET_BASE_ADDRESS 0xfed00000 +#define DEFAULT_RCBA 0xfed1c000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -32,14 +21,10 @@ #define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_SIZE 0x1000 -#define ACPI_BASE_ADDRESS 0x1000 -#define ACPI_BASE_SIZE 0x100 +#define DEFAULT_PMBASE 0x1000 -#define GPIO_BASE_ADDRESS 0x1400 -#define GPIO_BASE_SIZE 0x400 - -#define SMBUS_BASE_ADDRESS 0x0400 -#define SMBUS_BASE_SIZE 0x10 +#define DEFAULT_GPIOBASE 0x1400 +#define DEFAULT_GPIOSIZE 0x400 /* Temporary addresses used in romstage */ #define EARLY_GTT_BAR 0xe0000000 diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 33293a4..1319a02 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -115,9 +115,9 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { MCHBAR, 0x8000, get_bar, "MCHBAR" }, + { DMIBAR, 0x1000, get_bar, "DMIBAR" }, + { EPBAR, 0x1000, get_bar, "EPBAR" }, { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, }; diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl index 6b20f27..afbd4d6 100644 --- a/src/soc/intel/broadwell/pch/acpi/gpio.asl +++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl @@ -41,9 +41,9 @@ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - BLEN = GPIO_BASE_SIZE - BMIN = GPIO_BASE_ADDRESS - BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1 + BLEN = DEFAULT_GPIOSIZE + BMIN = DEFAULT_GPIOBASE + BMAX = DEFAULT_GPIOBASE + DEFAULT_GPIOSIZE - 1 Return (RBUF) } diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index ae54ce3..5f69d7c 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -155,7 +155,7 @@ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff) + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff) }) Method (_CRS, 0, NotSerialized) diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index c7c6207..b10c62d 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -15,7 +15,7 @@ } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 79cfe90..fa6ff95 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -14,7 +14,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) @@ -49,13 +49,13 @@ static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); - pci_write_config32(PCH_LPC_DEV, PMBASE, ACPI_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, GPIO_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, GPIO_EN); @@ -89,15 +89,15 @@ (void)RCBA32(HPTC); /* Enable HPET to start counter */ - setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0); + setbits32((void *)CONFIG_HPET_ADDRESS + 0x10, 1 << 0); /* Disable reset */ RCBA32_OR(GCS, 1 << 5); /* TCO timer halt */ - u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); + u16 reg16 = inb(DEFAULT_PMBASE + TCO1_CNT); reg16 |= TCO_TMR_HLT; - outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); + outb(reg16, DEFAULT_PMBASE + TCO1_CNT); /* Enable upper 128 bytes of CMOS */ RCBA32_OR(RC, 1 << 2); diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 5679541..39e3508 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -8,7 +8,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = DEFAULT_PMBASE; fadt->sci_int = 9; diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/soc/intel/broadwell/pch/gpio.c index eac484c..d61670d 100644 --- a/src/soc/intel/broadwell/pch/gpio.c +++ b/src/soc/intel/broadwell/pch/gpio.c @@ -53,8 +53,8 @@ break; /* Setup Configuration registers 1 and 2 */ - outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio)); - outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio)); + outl(entry->conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio)); + outl(entry->conf1, DEFAULT_GPIOBASE + GPIO_CONFIG1(gpio)); /* Determine set and bit based on GPIO number */ set = gpio >> 5; @@ -78,14 +78,14 @@ } for (set = 0; set <= 2; set++) { - outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set)); + outl(owner[set], DEFAULT_GPIOBASE + GPIO_OWNER(set)); + outl(route[set], DEFAULT_GPIOBASE + GPIO_ROUTE(set)); + outl(irqen[set], DEFAULT_GPIOBASE + GPIO_IRQ_IE(set)); + outl(reset[set], DEFAULT_GPIOBASE + GPIO_RESET(set)); } - outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); - outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); + outl(blink, DEFAULT_GPIOBASE + GPIO_BLINK); + outl(pirq2apic, DEFAULT_GPIOBASE + GPIO_PIRQ_APIC_EN); } int get_gpio(int gpio_num) @@ -93,7 +93,7 @@ if (gpio_num > MAX_GPIO_NUMBER) return 0; - return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); + return !!(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); } /* @@ -122,13 +122,13 @@ if (gpio_num > MAX_GPIO_NUMBER) return; - conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + conf0 = inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)); conf0 &= ~GPO_LEVEL_MASK; conf0 |= value << GPO_LEVEL_SHIFT; - outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + outl(conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)); } int gpio_is_native(int gpio_num) { - return !(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & 1); + return !(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & 1); } diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 2114a84..d5ecdeb 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -194,10 +194,10 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); /* Prepare sleep mode */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(DEFAULT_PMBASE + PM1_CNT); reg32 &= ~SLP_TYP; reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + outl(reg32, DEFAULT_PMBASE + PM1_CNT); /* Set up NMI on errors */ reg8 = inb(0x61); @@ -499,9 +499,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (default_decode_base > RCBA_BASE_ADDRESS) { + if (default_decode_base > DEFAULT_RCBA) { res = new_resource(dev, RCBA); - res->base = RCBA_BASE_ADDRESS; + res->base = DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; @@ -583,11 +583,11 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE, GPIO_BASE); + pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ - pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); + pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 0x100, PMBASE); /* LPC Generic IO Decode range. */ if (dev->chip_info) { diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h index 40467ed..7e9e1a5 100644 --- a/src/soc/intel/broadwell/pch/pm.h +++ b/src/soc/intel/broadwell/pch/pm.h @@ -5,7 +5,7 @@ #include <acpi/acpi.h> -/* ACPI_BASE_ADDRESS / PMBASE */ +/* DEFAULT_PMBASE / PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index cc61715..e8af6cc 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -24,7 +24,7 @@ static inline uint16_t get_gpiobase(void) { - return GPIO_BASE_ADDRESS; + return DEFAULT_GPIOBASE; } /* Print status bits with descriptive names */ @@ -424,5 +424,5 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t) DEFAULT_PMBASE; } diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index bb80550..562b876 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -50,7 +50,7 @@ break; } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + outl(ps->pm1_cnt & ~(SLP_TYP), DEFAULT_PMBASE + PM1_CNT); } if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) @@ -86,19 +86,19 @@ { struct chipset_power_state *ps = &power_state; - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); - ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); - ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); - ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); - ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2)); - ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3)); - ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); - ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1)); - ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); - ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3)); + ps->pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + ps->pm1_en = inw(DEFAULT_PMBASE + PM1_EN); + ps->pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + ps->tco1_sts = inw(DEFAULT_PMBASE + TCO1_STS); + ps->tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + ps->gpe0_sts[0] = inl(DEFAULT_PMBASE + GPE0_STS(0)); + ps->gpe0_sts[1] = inl(DEFAULT_PMBASE + GPE0_STS(1)); + ps->gpe0_sts[2] = inl(DEFAULT_PMBASE + GPE0_STS(2)); + ps->gpe0_sts[3] = inl(DEFAULT_PMBASE + GPE0_STS(3)); + ps->gpe0_en[0] = inl(DEFAULT_PMBASE + GPE0_EN(0)); + ps->gpe0_en[1] = inl(DEFAULT_PMBASE + GPE0_EN(1)); + ps->gpe0_en[2] = inl(DEFAULT_PMBASE + GPE0_EN(2)); + ps->gpe0_en[3] = inl(DEFAULT_PMBASE + GPE0_EN(3)); ps->gen_pmcon1 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_1); ps->gen_pmcon2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2); diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/soc/intel/broadwell/pch/rcba.h index b514c6a..7293dff 100644 --- a/src/soc/intel/broadwell/pch/rcba.h +++ b/src/soc/intel/broadwell/pch/rcba.h @@ -5,9 +5,9 @@ #include <soc/intel/broadwell/memmap.h> -#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x)) +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c index 8985905..76562ce 100644 --- a/src/soc/intel/broadwell/pch/smbus.c +++ b/src/soc/intel/broadwell/pch/smbus.c @@ -61,7 +61,7 @@ static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_BASE_ADDRESS; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/soc/intel/broadwell/pch/smi.c index 21986e3..3231f2c 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/soc/intel/broadwell/pch/smi.c @@ -14,9 +14,9 @@ u32 smi_en; printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", DEFAULT_PMBASE); - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + smi_en = inl(DEFAULT_PMBASE + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index d79082a..ec3f819 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -16,13 +16,13 @@ pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; pei_data->usbdebug = CONFIG(USBDEBUG); - pei_data->pciexbar = MCFG_BASE_ADDRESS; - pei_data->smbusbar = SMBUS_BASE_ADDRESS; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; pei_data->ehcibar = EARLY_EHCI_BAR; pei_data->xhcibar = EARLY_XHCI_BAR; pei_data->gttbar = EARLY_GTT_BAR; - pei_data->pmbase = ACPI_BASE_ADDRESS; - pei_data->gpiobase = GPIO_BASE_ADDRESS; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; -- To view, visit https://review.coreboot.org/c/coreboot/+/46956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I473336a77179a3d1d26933f481abded49e9f0864 Gerrit-Change-Number: 46956 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/intel/broadwell: Refactor MRC entry
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47000 ) Change subject: soc/intel/broadwell: Refactor MRC entry ...................................................................... soc/intel/broadwell: Refactor MRC entry Twist and bend the code so that it looks more like Haswell. Change-Id: I03eda7efe022ec8d7b684926c28d0e3b546165b2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/raminit.c A src/soc/intel/broadwell/raminit.h M src/soc/intel/broadwell/romstage.c M src/soc/intel/broadwell/romstage.h 4 files changed, 107 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47000/1 diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index f011679..5339daa 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -9,18 +9,50 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <security/vboot/vboot_common.h> #include <soc/intel/broadwell/romstage.h> #include "haswell.h" #include "pei_data.h" #include "pei_wrapper.h" +#include "raminit.h" + +#define MRC_CACHE_VERSION 0 + +void save_mrc_data(struct pei_data *pei_data) +{ + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, + pei_data->data_to_save_size); + + if (pei_data->data_to_save == NULL || !pei_data->data_to_save_size) + return; + + /* Save the MRC S3 restore data to cbmem */ + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->data_to_save, + pei_data->data_to_save_size); +} + +static void prepare_mrc_cache(struct pei_data *pei_data) +{ + size_t mrc_size; + + /* Preset just in case there is an error */ + pei_data->saved_data = NULL; + pei_data->saved_data_size = 0; + + pei_data->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &mrc_size); + + if (!pei_data->saved_data) { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + return; + } + + pei_data->saved_data_size = mrc_size; + + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->saved_data, + pei_data->saved_data_size); +} static const char *const ecc_decoder[] = { "inactive", @@ -29,10 +61,7 @@ "active", }; -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +/* Print out the memory controller configuration, as per the values in its registers. */ static void report_memory_config(void) { int i; @@ -72,47 +101,39 @@ } } -/* +/** * Find PEI executable in coreboot filesystem and execute it. + * + * @param pei_data: configuration data for UEFI PEI reference code */ -void raminit(struct pei_data *pei_data) +void sdram_initialize(struct pei_data *pei_data) { - size_t mrc_size; - struct memory_info *mem_info; pei_wrapper_entry_t entry; - int ret; - struct cbfsf f; + uint32_t type = CBFS_TYPE_MRC; + struct cbfsf f; - broadwell_fill_pei_data(pei_data); + printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && - vboot_recovery_mode_enabled()) { + if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else { /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - pei_data->saved_data = - mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, - &mrc_size); - if (pei_data->saved_data) { - /* MRC cache found */ - pei_data->saved_data_size = mrc_size; - } else if (pei_data->boot_mode == ACPI_S3) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - system_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); - } + prepare_mrc_cache(pei_data); + } + + /* If MRC data is not found, we cannot continue S3 resume */ + if (pei_data->boot_mode == ACPI_S3 && !pei_data->saved_data) { + post_code(POST_RESUME_FAILURE); + printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); + system_reset(); } /* - * Do not use saved pei data. Can be set by mainboard romstage + * Do not use saved pei data. Can be set by mainboard romstage * to force a full train of memory on every boot. */ if (pei_data->disable_saved_data) { @@ -124,52 +145,37 @@ /* Determine if mrc.bin is in the cbfs. */ if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; + entry = rdev_mmap_full(&f.data); + if (entry) { + int rv = entry(pei_data); + + if (rv < 0) + die("pei_data version mismatch\n"); + } else { + die("UEFI PEI System Agent not found.\n"); } - printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); - - ret = entry(pei_data); - if (ret < 0) - die("pei_data version mismatch\n"); - - /* Print the MRC version after executing the UEFI PEI stage. */ + /* Print the MRC version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); +} - if (pei_data->boot_mode != ACPI_S3) { - cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - system_reset(); - } +void setup_sdram_meminfo(struct pei_data *pei_data) +{ + struct memory_info *mem_info; - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); - - if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) - mrc_cache_stash_data(MRC_TRAINING_DATA, 0, - pei_data->data_to_save, - pei_data->data_to_save_size); - - printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); - - if (!mem_info) { - printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n"); - return; - } + if (!mem_info) + die("Failed to add memory info to CBMEM.\n"); memset(mem_info, 0, sizeof(*mem_info)); + /* Translate pei_memory_info struct data into memory_info struct */ mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { diff --git a/src/soc/intel/broadwell/raminit.h b/src/soc/intel/broadwell/raminit.h new file mode 100644 index 0000000..e2363cb --- /dev/null +++ b/src/soc/intel/broadwell/raminit.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include <stdint.h> +#include "pei_data.h" + +void sdram_initialize(struct pei_data *pei_data); +void setup_sdram_meminfo(struct pei_data *pei_data); + +/* save_mrc_data() must be called after cbmem has been initialized. */ +void save_mrc_data(struct pei_data *pei_data); + +#endif /* RAMINIT_H */ diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index bea9feb..c47d60f 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -2,6 +2,8 @@ #include <acpi/acpi.h> #include <arch/romstage.h> +#include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> @@ -17,6 +19,7 @@ #include "pch/gpio.h" #include "pch/me.h" #include "pch/pch.h" +#include "raminit.h" /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) @@ -64,11 +67,25 @@ /* Save ME HSIO version */ intel_me_hsio_version(&power_state->hsio_version, &power_state->hsio_checksum); + broadwell_fill_pei_data(&pei_data); + /* Initialize RAM */ - raminit(&pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (!s3resume) { + cbmem_initialize_empty(); + /* Save data returned from MRC on non-S3 resumes. */ + save_mrc_data(&pei_data); + } else if (cbmem_initialize()) { + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + system_reset(); + } + + setup_sdram_meminfo(&pei_data); + romstage_handoff_init(s3resume); mainboard_post_raminit(s3resume); diff --git a/src/soc/intel/broadwell/romstage.h b/src/soc/intel/broadwell/romstage.h index d788155..d364317 100644 --- a/src/soc/intel/broadwell/romstage.h +++ b/src/soc/intel/broadwell/romstage.h @@ -8,8 +8,6 @@ void mainboard_pre_raminit(struct pei_data *pei_data); void mainboard_post_raminit(const int s3resume); -void raminit(struct pei_data *pei_data); - void report_platform_info(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03eda7efe022ec8d7b684926c28d0e3b546165b2 Gerrit-Change-Number: 47000 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: broadwell: Clean up pei_data callbacks
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46996 ) Change subject: broadwell: Clean up pei_data callbacks ...................................................................... broadwell: Clean up pei_data callbacks None of the boards uses the romstage_params struct. Relocate common prototypes to soc code. A follow-up will clean up google/auron headers. Change-Id: I1e255500ef56509a2b9e3f8c8d8abb8248f9612f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/include/variant/spd.h M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/gandof/include/variant/spd.h M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/include/variant/spd.h M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/include/variant/spd.h M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/spd/spd.c D src/mainboard/google/jecht/spd/spd.h M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/pei_wrapper.h M src/soc/intel/broadwell/romstage.c M src/soc/intel/broadwell/romstage.h 22 files changed, 19 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46996/1 diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index d3a799c..7ecddcf 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -12,14 +12,6 @@ { } -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); - mainboard_fill_spd_data(&rp->pei_data); - -} - void mainboard_post_raminit(struct romstage_params *rp) { /* Do variant-specific init */ diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h index 74e3cdf..7e34ca1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h @@ -20,7 +20,4 @@ #define SPD_GPIO_BIT1 9 #define SPD_GPIO_BIT2 47 -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index b56de42..5521c3f 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -6,6 +6,7 @@ #include <string.h> #include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h index 74e3cdf..7e34ca1 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h @@ -20,7 +20,4 @@ #define SPD_GPIO_BIT1 9 #define SPD_GPIO_BIT2 47 -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index b56de42..5521c3f 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -6,6 +6,7 @@ #include <string.h> #include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h index 5ebd8c2..7f7914d 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h @@ -3,7 +3,4 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 3e605bc..e74e6b9 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <variant/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h index 2263672..dfcd7cc 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h @@ -20,7 +20,4 @@ #define SPD_GPIO_BIT1 9 #define SPD_GPIO_BIT2 47 -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index b56de42..5521c3f 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -6,6 +6,7 @@ #include <string.h> #include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h index 903b60a..da8c387 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h @@ -21,7 +21,4 @@ #define SPD_GPIO_BIT2 47 #define SPD_GPIO_BIT3 8 -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 4f367fa..b35a57f 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -6,6 +6,7 @@ #include <string.h> #include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h index c9b0498..79fbc1b 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/spd.h +++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h @@ -21,7 +21,4 @@ #define SPD_GPIO_BIT2 67 #define SPD_GPIO_BIT3 65 -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 055f725..a8ab2e3 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -6,6 +6,7 @@ #include <string.h> #include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index f28ee86..e1dacba 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -8,16 +8,8 @@ #include <soc/intel/broadwell/romstage.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include <mainboard/google/jecht/spd/spd.h> #include "onboard.h" -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); - mainboard_fill_spd_data(&rp->pei_data); -} - void mainboard_post_raminit(struct romstage_params *rp) { if (CONFIG(CHROMEOS)) diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 005645e..36ebd5b 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/intel/broadwell/pei_data.h> -#include <mainboard/google/jecht/spd/spd.h> +#include <soc/intel/broadwell/pei_wrapper.h> /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/jecht/spd/spd.h b/src/mainboard/google/jecht/spd/spd.h deleted file mode 100644 index 5ebd8c2..0000000 --- a/src/mainboard/google/jecht/spd/spd.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 89c1a06..b8f0c67 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -6,12 +6,6 @@ #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); -} - void mainboard_post_raminit(struct romstage_params *rp) { } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 103d22d..2395ed6 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -4,12 +4,6 @@ #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); -} - void mainboard_post_raminit(struct romstage_params *rp) { } diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index ec3f819..df28e21 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -11,6 +11,10 @@ console_tx_byte(b); } +__weak void mainboard_fill_spd_data(struct pei_data *pei_data) +{ +} + void broadwell_fill_pei_data(struct pei_data *pei_data) { pei_data->pei_version = PEI_VERSION; diff --git a/src/soc/intel/broadwell/pei_wrapper.h b/src/soc/intel/broadwell/pei_wrapper.h index 01762d2..f62aafa 100644 --- a/src/soc/intel/broadwell/pei_wrapper.h +++ b/src/soc/intel/broadwell/pei_wrapper.h @@ -29,4 +29,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); +/* Optional */ +void mainboard_fill_spd_data(struct pei_data *pei_data); + #endif diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index f9242fd..ce77159 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -7,6 +7,7 @@ #include <elog.h> #include <romstage_handoff.h> #include <soc/intel/broadwell/pch/pm.h> +#include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <stdint.h> #include <timestamp.h> @@ -44,8 +45,9 @@ /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); - /* Fill in mainboard pei_date. */ - mainboard_pre_raminit(&rp); + /* Fill in mainboard pei_data */ + mainboard_fill_pei_data(&rp.pei_data); + mainboard_fill_spd_data(&rp.pei_data); post_code(0x32); diff --git a/src/soc/intel/broadwell/romstage.h b/src/soc/intel/broadwell/romstage.h index 2e72a2f..0d00acc 100644 --- a/src/soc/intel/broadwell/romstage.h +++ b/src/soc/intel/broadwell/romstage.h @@ -12,7 +12,7 @@ struct pei_data pei_data; }; -void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_pre_raminit(struct pei_data *pei_data); void mainboard_post_raminit(struct romstage_params *params); void raminit(struct pei_data *pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/46996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e255500ef56509a2b9e3f8c8d8abb8248f9612f Gerrit-Change-Number: 46996 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: mb/google/auron: Clean up romstage logic
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46997 ) Change subject: mb/google/auron: Clean up romstage logic ...................................................................... mb/google/auron: Clean up romstage logic Refactor code to allow dropping unnecessary files. Change-Id: I2920c6f8d3f5dbff6148419ab24edbd460a6795e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h D src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_paine/variant.c D src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/variant.c D src/mainboard/google/auron/variants/buddy/include/variant/spd.h M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c D src/mainboard/google/auron/variants/gandof/include/variant/spd.h M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c D src/mainboard/google/auron/variants/lulu/include/variant/spd.h M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c D src/mainboard/google/auron/variants/samus/include/variant/spd.h M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c 25 files changed, 106 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46997/1 diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c deleted file mode 100644 index 7ecddcf..0000000 --- a/src/mainboard/google/auron/romstage.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <soc/intel/broadwell/pei_data.h> -#include <soc/intel/broadwell/pei_wrapper.h> -#include <soc/intel/broadwell/romstage.h> -#include <variant/spd.h> -#include "variant.h" - -__weak void variant_romstage_entry(struct romstage_params *rp) -{ -} - -void mainboard_post_raminit(struct romstage_params *rp) -{ - /* Do variant-specific init */ - variant_romstage_entry(rp); -} diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 5ee400f..96518a7 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -8,7 +8,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); -void variant_romstage_entry(struct romstage_params *rp); + void lan_init(void); #endif diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h deleted file mode 100644 index 7e34ca1..0000000 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Auron board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index ac22a8f..756dfac 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 5521c3f..a2d55ea 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -10,7 +10,23 @@ #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/spd.h> + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Auron board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 static void mainboard_print_spd_info(uint8_t spd[]) { diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index 4cafe30..d925f9f 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -3,6 +3,7 @@ #include <smbios.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> +#include <soc/intel/broadwell/romstage.h> int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -20,3 +21,7 @@ return len; } + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h deleted file mode 100644 index 7e34ca1..0000000 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Auron board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -#endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index ac22a8f..756dfac 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 5521c3f..a2d55ea 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -10,7 +10,23 @@ #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/spd.h> + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Auron board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 static void mainboard_print_spd_info(uint8_t spd[]) { diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index 4cafe30..d925f9f 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -3,6 +3,7 @@ #include <smbios.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> +#include <soc/intel/broadwell/romstage.h> int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -20,3 +21,7 @@ return len; } + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h deleted file mode 100644 index 7f7914d..0000000 --- a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#endif diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index db4ef36..b4135bd 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> +#include <soc/intel/broadwell/romstage.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -42,3 +42,7 @@ /* P4: Card Reader, CRS1 */ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index e74e6b9..da5f331 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -2,7 +2,6 @@ #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> -#include <variant/spd.h> /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h deleted file mode 100644 index dfcd7cc..0000000 --- a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Gandof board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index ac22a8f..756dfac 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 5521c3f..73dd3de 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -10,7 +10,23 @@ #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/spd.h> + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Gandof board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 static void mainboard_print_spd_info(uint8_t spd[]) { diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index 6ee1026..4ebab64 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -24,7 +24,7 @@ return len; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(struct romstage_params *rp) { if (rp->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(75); diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h deleted file mode 100644 index da8c387..0000000 --- a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Lulu board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 -#define SPD_GPIO_BIT3 8 - -#endif diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index 6ce9b35..46592cb 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index b35a57f..8ce5c34 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -10,7 +10,24 @@ #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/spd.h> + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Lulu board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 +#define SPD_GPIO_BIT3 8 static void mainboard_print_spd_info(uint8_t spd[]) { diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index f45f765..9a60933 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -34,7 +34,7 @@ return len; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(struct romstage_params *rp) { if (rp->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(75); diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h deleted file mode 100644 index 79fbc1b..0000000 --- a/src/mainboard/google/auron/variants/samus/include/variant/spd.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 69 -#define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 67 -#define SPD_GPIO_BIT3 65 - -#endif diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 8a9ed86..4ff3196 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <string.h> -#include <soc/intel/broadwell/pch/gpio.h> #include <soc/intel/broadwell/pei_data.h> #include <soc/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index a8ab2e3..08b8e0a 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -10,7 +10,24 @@ #include <soc/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/spd.h> + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 69 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 67 +#define SPD_GPIO_BIT3 65 static void mainboard_print_spd_info(uint8_t spd[]) { diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 33f164c..6d80949 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -21,7 +21,7 @@ return 0; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(struct romstage_params *rp) { if (rp->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(100); -- To view, visit https://review.coreboot.org/c/coreboot/+/46997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2920c6f8d3f5dbff6148419ab24edbd460a6795e Gerrit-Change-Number: 46997 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: broadwell: Simplify `mainboard_post_raminit` callback
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46998 ) Change subject: broadwell: Simplify `mainboard_post_raminit` callback ...................................................................... broadwell: Simplify `mainboard_post_raminit` callback Prepare to ditch romstage_params. The only thing that mainboards care about is whether the current boot is a resume from S3, and nothing else. Change-Id: I703d9a1bfa1d3229b55f3a7ee9ec2f210fc9495e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/variants/auron_paine/variant.c M src/mainboard/google/auron/variants/auron_yuna/variant.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/broadwell/romstage.h 11 files changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46998/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index d925f9f..15b082e 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -22,6 +22,6 @@ return len; } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { } diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index d925f9f..15b082e 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -22,6 +22,6 @@ return len; } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { } diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index b4135bd..b52ca6f 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -43,6 +43,6 @@ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { } diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index 4ebab64..5bdb1d2 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -24,8 +24,8 @@ return len; } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(75); } diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 9a60933..8bd34fc 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -34,8 +34,8 @@ return len; } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(75); } diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 6d80949..9852f1f 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -21,9 +21,9 @@ return 0; } -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(100); printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index e1dacba..eb187c2 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -10,7 +10,7 @@ #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { if (CONFIG(CHROMEOS)) init_bootmode_straps(); diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index b8f0c67..53745e6 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -6,6 +6,6 @@ #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 2395ed6..34aaf00 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -4,6 +4,6 @@ #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { } diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index ce77159..73afc15 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -34,7 +34,9 @@ /* Get power state */ rp.power_state = fill_power_state(); - elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + const int s3resume = rp.power_state->prev_sleep_state == ACPI_S3; + + elog_boot_notify(s3resume); /* Print useful platform information */ report_platform_info(); @@ -67,7 +69,7 @@ timestamp_add_now(TS_AFTER_INITRAM); - romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); + romstage_handoff_init(s3resume); - mainboard_post_raminit(&rp); + mainboard_post_raminit(s3resume); } diff --git a/src/soc/intel/broadwell/romstage.h b/src/soc/intel/broadwell/romstage.h index 0d00acc..f5fda23 100644 --- a/src/soc/intel/broadwell/romstage.h +++ b/src/soc/intel/broadwell/romstage.h @@ -13,7 +13,7 @@ }; void mainboard_pre_raminit(struct pei_data *pei_data); -void mainboard_post_raminit(struct romstage_params *params); +void mainboard_post_raminit(const int s3resume); void raminit(struct pei_data *pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/46998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d9a1bfa1d3229b55f3a7ee9ec2f210fc9495e Gerrit-Change-Number: 46998 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/broadwell: Get rid of `struct romstage_params`
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46999 ) Change subject: soc/intel/broadwell: Get rid of `struct romstage_params` ...................................................................... soc/intel/broadwell: Get rid of `struct romstage_params` This is no longer necessary. Get rid of it. Change-Id: Ib91b99332e05555b9ea746a7b202231bff47cf6a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/broadwell/romstage.h 4 files changed, 12 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46999/1 diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h index 7e9e1a5..918b3a6 100644 --- a/src/soc/intel/broadwell/pch/pm.h +++ b/src/soc/intel/broadwell/pch/pm.h @@ -110,6 +110,8 @@ uint16_t hsio_checksum; }; +struct chipset_power_state *fill_power_state(void); + /* PM1_CNT */ void enable_pm1_control(uint32_t mask); void disable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index 562b876..a39822a 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -14,6 +14,7 @@ #include "lpc.h" #include "pch.h" +#include "pm.h" static struct chipset_power_state power_state; diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 73afc15..bea9feb 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -21,7 +21,8 @@ /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) { - struct romstage_params rp = { 0 }; + struct chipset_power_state *power_state; + struct pei_data pei_data = { 0 }; post_code(0x30); @@ -32,9 +33,9 @@ pch_early_init(); /* Get power state */ - rp.power_state = fill_power_state(); + power_state = fill_power_state(); - const int s3resume = rp.power_state->prev_sleep_state == ACPI_S3; + const int s3resume = power_state->prev_sleep_state == ACPI_S3; elog_boot_notify(s3resume); @@ -48,24 +49,23 @@ init_gpios(mainboard_gpio_config); /* Fill in mainboard pei_data */ - mainboard_fill_pei_data(&rp.pei_data); - mainboard_fill_spd_data(&rp.pei_data); + mainboard_fill_pei_data(&pei_data); + mainboard_fill_spd_data(&pei_data); post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; + pei_data.boot_mode = power_state->prev_sleep_state; /* Print ME state before MRC */ intel_me_status(); /* Save ME HSIO version */ - intel_me_hsio_version(&rp.power_state->hsio_version, - &rp.power_state->hsio_checksum); + intel_me_hsio_version(&power_state->hsio_version, &power_state->hsio_checksum); /* Initialize RAM */ - raminit(&rp.pei_data); + raminit(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); diff --git a/src/soc/intel/broadwell/romstage.h b/src/soc/intel/broadwell/romstage.h index f5fda23..d788155 100644 --- a/src/soc/intel/broadwell/romstage.h +++ b/src/soc/intel/broadwell/romstage.h @@ -5,20 +5,11 @@ #include <soc/intel/broadwell/pei_data.h> -struct chipset_power_state; -struct pei_data; -struct romstage_params { - struct chipset_power_state *power_state; - struct pei_data pei_data; -}; - void mainboard_pre_raminit(struct pei_data *pei_data); void mainboard_post_raminit(const int s3resume); void raminit(struct pei_data *pei_data); -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); void report_platform_info(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib91b99332e05555b9ea746a7b202231bff47cf6a Gerrit-Change-Number: 46999 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: mb/google/hatch/dratini: Describe the privacy_gpio
by Ricardo Ribalda (Code Review) 28 Jan '21

28 Jan '21

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47362 ) Change subject: mb/google/hatch/dratini: Describe the privacy_gpio ...................................................................... mb/google/hatch/dratini: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and gpio. BUG=b:172807539 Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/dratini/overridetree.cb 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47362/1 diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index ccb5c05..f50f8f2 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -16,6 +16,8 @@ PAD_NC(GPP_A19, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index c5e2aeb..98beaaa 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -69,6 +69,19 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/47362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168 Gerrit-Change-Number: 47362 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/parrot: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46177 ) Change subject: mb/google/parrot: Convert to ASL 2.0 syntax ...................................................................... mb/google/parrot: Convert to ASL 2.0 syntax Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/parrot/acpi/mainboard.asl M src/mainboard/google/parrot/acpi/platform.asl M src/mainboard/google/parrot/acpi/thermal.asl 3 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46177/1 diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 39a428b..6d5e907 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -22,7 +22,7 @@ Name(_HID, EisaId("PNP0C0D")) Method(_LID, 0) { - Store (GP15, \LIDS) + \LIDS = GP15 Return (\LIDS) } } diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl index 2e14a71..861ba52 100644 --- a/src/mainboard/google/parrot/acpi/platform.asl +++ b/src/mainboard/google/parrot/acpi/platform.asl @@ -15,16 +15,16 @@ { /* Update in case state changed while asleep */ /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ADPT + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (GP15, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = GP15 + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.LID0, 0x80) } diff --git a/src/mainboard/google/parrot/acpi/thermal.asl b/src/mainboard/google/parrot/acpi/thermal.asl index 852f58f..2d32d47 100644 --- a/src/mainboard/google/parrot/acpi/thermal.asl +++ b/src/mainboard/google/parrot/acpi/thermal.asl @@ -26,10 +26,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -55,23 +55,23 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from the Embedded Controller - Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTMP // Re-read from EC if the temperature is very high to // avoid OS shutdown if we got a bad reading. - If (LGreaterEqual (Local0, \TCRT)) { - Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0) - If (LGreaterEqual (Local0, \TCRT)) { + If (Local0 >= \TCRT) { + Local0 = \_SB.PCI0.LPCB.EC0.CTMP + If (Local0 >= \TCRT) { // Check if this is an early read - If (LLess (CRDC, IRDC)) { - Store (0, Local0) + If (CRDC < IRDC) { + Local0 = 0 } } } // Keep track of first few reads by the OS - If (LLess (CRDC, IRDC)) { - Increment (CRDC) + If (CRDC < IRDC) { + CRDC++ } Return (CTOK (Local0)) -- To view, visit https://review.coreboot.org/c/coreboot/+/46177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84 Gerrit-Change-Number: 46177 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/mediatek/mt8192: Implement dram all channel calibration
by CK HU (Code Review) 28 Jan '21

28 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44715 to review the following change. Change subject: soc/mediatek/mt8192: Implement dram all channel calibration ...................................................................... soc/mediatek/mt8192: Implement dram all channel calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 358 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44715/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1a5f242..8362c05 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -4031,6 +4031,51 @@ dramc_set_broadcast(bc_bak); } +static void move_dramc_delay(const struct ddr_cali* cali, reg_transfer *ui, + reg_transfer *mck, s8 shift_ui) +{ + s32 sum; + u8 ui_offset = ui->offset, ui_width = 4, mck_offset = mck->offset, mck_width = 3; + u32 *ui_reg = ui->addr, *mck_reg = mck->addr; + + u32 tmp_ui, tmp_mck, ui_mask, mck_mask; + u8 div_shift = get_mck2ui_div_shift(cali); + + ui_mask = (BIT(ui_width) - 1); + mck_mask = (BIT(mck_width) - 1); + tmp_ui = ((read32(ui_reg) >> ui_offset) & ui_mask) & (~(1 << div_shift)); + tmp_mck = (read32(mck_reg) >> mck_offset) & mck_mask; + + sum = (tmp_mck << div_shift) + tmp_ui + shift_ui; + + if (sum < 0) { + tmp_ui = 0; + tmp_mck = 0; + } else { + tmp_mck = sum >> div_shift; + tmp_ui = sum - (tmp_mck << div_shift); + } + + clrsetbits32(ui_reg, ui_mask << ui_offset, tmp_ui << ui_offset); + clrsetbits32(mck_reg, mck_mask << mck_offset, tmp_mck << mck_offset); +} + +void shift_dq_ui(const struct ddr_cali* cali, u8 rk, s8 shift_ui) +{ + u8 chn = cali->chn; + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 4}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 4}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 4}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 4}}; + + for (u8 idx = 0; idx < ARRAY_SIZE(ui_regs); idx++) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + static void ddr_update_ac_timing(const struct ddr_cali *cali) { u8 table_idx; @@ -4407,3 +4452,255 @@ dramc_before_calibration(cali); } +void tx_picg_setting(const struct ddr_cali *cali) +{ + u32 dqs_oen_final, dq_oen_final; + u16 dqs_oen_2t[2], dqs_oen_05t[2], dqs_oen_delay[2]; + u16 dq_oen_2t[2], dq_oen_05t[2], dq_oen_delay[2]; + u16 comb_tx_sel[2]; + u16 shift_dqs_div[2], shift_dq_div[2]; + u16 comb_tx_picg_cnt; + u8 div_ratio; + + comb_tx_picg_cnt = 3; + if (get_div_mode(cali) == DIV8_MODE) { + shift_dqs_div[0] = 10; + shift_dqs_div[1] = 6; + shift_dq_div[0] = 8; + shift_dq_div[1] = 4; + div_ratio = 3; + } else { + shift_dqs_div[0] = 2; + shift_dqs_div[1] = 0; + shift_dq_div[0] = 0; + shift_dq_div[1] = 0; + div_ratio = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dqs_oen_2t[0] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0); + dqs_oen_05t[0] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_OEN_DQS0); + dqs_oen_delay[0] = (dqs_oen_2t[0] << div_ratio) + dqs_oen_05t[0]; + dqs_oen_2t[1] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1); + dqs_oen_05t[1] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_OEN_DQS1); + dqs_oen_delay[1] = (dqs_oen_2t[1] << div_ratio) + dqs_oen_05t[1]; + + dqs_oen_final = (dqs_oen_delay[0] > dqs_oen_delay[1]) ? + dqs_oen_delay[1]: dqs_oen_delay[0]; + dqs_oen_final += 1; + + comb_tx_sel[0] = (dqs_oen_final > shift_dqs_div[0]) ? + ((dqs_oen_final - shift_dqs_div[0]) >> div_ratio) : 0; + + if (get_div_mode(cali) == DIV4_MODE) + comb_tx_sel[1] = 0; + else + comb_tx_sel[1] = (dqs_oen_final > shift_dqs_div[1]) ? + ((dqs_oen_final - shift_dqs_div[1]) >> div_ratio): 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, comb_tx_sel[0], + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, comb_tx_sel[1], + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, comb_tx_picg_cnt); + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + dq_oen_2t[0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + dq_oen_05t[0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_OEN_DQ0); + dq_oen_delay[0] = (dq_oen_2t[0] << div_ratio) + dq_oen_05t[0]; + dq_oen_2t[1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + dq_oen_05t[1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1); + dq_oen_delay[1] = (dq_oen_2t[1] << div_ratio) + dq_oen_05t[1]; + + dq_oen_final = (dq_oen_delay[0] > dq_oen_delay[1]) ? + dq_oen_delay[1] : dq_oen_delay[0]; + dq_oen_final += 1; + + comb_tx_sel[0] = (dq_oen_final > shift_dq_div[0]) ? + ((dq_oen_final - shift_dq_div[0]) >> div_ratio) : 0; + + if (get_div_mode(cali) == DIV4_MODE) + comb_tx_sel[1] = 0; + else + comb_tx_sel[1] = (dq_oen_final > shift_dq_div[1]) ? + ((dq_oen_final - shift_dq_div[1]) >> div_ratio): 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, comb_tx_sel[0], + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, comb_tx_sel[1]); + } + } +} + +void xrtrtr_shu_setting(const struct ddr_cali *cali) +{ + dram_freq_grp freq_group = get_freq_group(cali); + u8 rk_sel_ui_minus = 0, rk_sel_mck_minus = 0; + + if (freq_group == DDRFREQ_400) + rk_sel_mck_minus = 1; + else if (freq_group >= DDRFREQ_1600) + rk_sel_ui_minus = 2; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, rk_sel_mck_minus, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, rk_sel_ui_minus, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1); +} + +void freq_jump_ratio_calculation(const struct ddr_cali *cali) +{ + u32 src_freq, dst_freq, src_shu, dst_shu, jump_ratio_index; + u16 jump_ratio[12] = {0}; + + jump_ratio_index = 0; + src_freq = get_frequency(cali); + src_shu = get_shu(cali); + + if (src_freq != 400) { + for (dst_shu = DRAM_DFS_SHU0; dst_shu < DRAM_DFS_SHU_MAX; dst_shu++) { + dst_freq = get_frequency_by_shu(dst_shu); + jump_ratio[jump_ratio_index] = DIV_ROUND_CLOSEST(dst_freq * 32, src_freq); + + dramc_dbg("Jump_RATIO [%d]: 0x%x\tFreq %d -> %d\tDDR%d -> DDR%d\n", + jump_ratio_index, jump_ratio[jump_ratio_index], + src_shu, dst_shu, src_freq << 1, dst_freq << 1); + jump_ratio_index++; + } + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set0, + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, jump_ratio[0], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, jump_ratio[1], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, jump_ratio[2], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, jump_ratio[3]); + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set1, + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, jump_ratio[4], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, jump_ratio[5], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, jump_ratio[6], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, jump_ratio[7]); + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set2, + SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, jump_ratio[8], + SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, jump_ratio[9]); + } +} + +void dramc_hmr4_presetting(const struct ddr_cali* cali) +{ + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFR_PERIOD_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRCNT_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x80); + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 1); + else + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 0); + + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 1); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); + } +} + +void dramc_enable_perbank_refresh(bool en) +{ + if (en) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_PBREF_BK_REFA_ENA, 1, + REFCTRL0_PBREF_BK_REFA_NUM, 2); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_KEEP_PBREF, 0, + REFCTRL0_KEEP_PBREF_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 1); + } + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, en); +} + +void dramc_modified_refresh_mode(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.refpend1, + REFPEND1_MPENDREFCNT_TH0, 2, + REFPEND1_MPENDREFCNT_TH1, 2, + REFPEND1_MPENDREFCNT_TH2, 4, + REFPEND1_MPENDREFCNT_TH3, 5, + REFPEND1_MPENDREFCNT_TH4, 5, + REFPEND1_MPENDREFCNT_TH5, 3, + REFPEND1_MPENDREFCNT_TH6, 3, + REFPEND1_MPENDREFCNT_TH7, 3); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REFPEND_OPT1, 1, + REFCTRL1_REFPEND_OPT2, 1); + SET32_BITFIELDS(&ch[chn].ao.shu_ref0, SHU_REF0_MPENDREF_CNT, 4); + } +} + +void dramc_cke_debounce(const struct ddr_cali* cali) +{ + if (get_freq_group(cali) < DDRFREQ_2133) + return; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rk = 0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_cke_ctrl, + SHURK_CKE_CTRL_CKE_DBE_CNT, 15); +} + +void dramc_hw_dqsosc(const struct ddr_cali* cali, u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.tx_freq_ratio_old_mode0, + TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 1); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 1, + TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 0, + TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 0); + + SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, MPC_CTRL_MPC_BLOCKALE_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0); + SET32_BITFIELDS(&ch[chn].ao.rk[0].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); + if (cali->support_ranks == DUAL_RANK_DDR) + SET32_BITFIELDS(&ch[chn].ao.rk[1].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_DRSCLR_RK0_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); +} + +void apply_write_dbi_power_improve(bool en) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.dbiwr_protect, + DBIWR_PROTECT_DBIWR_OPT_B1, 0, + DBIWR_PROTECT_DBIWR_OPT_B0, 0, + DBIWR_PROTECT_DBIWR_PINMUX_EN, 0, + DBIWR_PROTECT_DBIWR_IMP_EN, en); +} + +void dramc_write_dbi_onoff(u8 onoff) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, onoff); + dramc_info("DramC Write-DBI %s\n", (onoff == DBI_ON) ? "on" : "off"); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 3273f28..11ec636 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,16 @@ #include <soc/pll_common.h> #include <soc/mt6359p.h> +static void dramc_write_shift_mck_write_DBI(const struct ddr_cali *cali, s8 shift_value) +{ + u8 div_shift = 0; + s8 ui_move = 0; + + div_shift = get_mck2ui_div_shift(cali); + ui_move = shift_value * (s8)(1 << div_shift); + shift_dq_ui(cali, cali->rank, ui_move); +} + static void dramc_ac_timing_optimize(const struct ddr_cali* cali) { u8 rf_group = 0, cab_id = 0; @@ -208,8 +218,57 @@ cali->density = max_density; } +static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) +{ + cali->chn = chn; + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { + u8 chn_bak, rank_bak; + dbi_mode w_dbi = get_write_dbi(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_calibration_single_channel(cali, chn); + + if (w_dbi == DBI_ON) { + chn_bak = cali->chn; + rank_bak = cali->rank; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rank = RANK_0; rank < RANK_MAX; rank++) { + cali->chn = chn; + cali->rank = rank; + dramc_write_shift_mck_write_DBI(cali, -1); + } + cali->chn = chn_bak; + cali->rank = rank_bak; + apply_write_dbi_power_improve(true); + } + + dramc_write_dbi_onoff(w_dbi); + + tx_picg_setting(cali); + if (cali->support_ranks == DUAL_RANK_DDR) + xrtrtr_shu_setting(cali); + freq_jump_ratio_calculation(cali); + + dramc_hmr4_presetting(cali); + dramc_enable_perbank_refresh(true); + dramc_modified_refresh_mode(); + dramc_cke_debounce(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_hw_dqsosc(cali, chn); } static void mem_pll_init(void) @@ -296,6 +355,7 @@ if (first_freq_k) dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); - first_freq_k= false; + first_freq_k = false; + dramc_info("frequency %d calibration finish\n", get_frequency(&cali)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 Gerrit-Change-Number: 44715 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020