coreboot-gerrit November 2020

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Change in coreboot[master]: nb/intel/haswell: Calculate TSEG limit from registers
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46991 ) Change subject: nb/intel/haswell: Calculate TSEG limit from registers ...................................................................... nb/intel/haswell: Calculate TSEG limit from registers Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46991/1 diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 02d120b..c19cfec 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,13 +4,13 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt_register.h> +#include <types.h> #include "haswell.h" @@ -19,9 +19,9 @@ return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); } -static size_t northbridge_get_tseg_size(void) +static uintptr_t northbridge_get_tseg_limit(void) { - return CONFIG_SMM_TSEG_SIZE; + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB); } union dpr_register txt_get_chipset_dpr(void) @@ -62,7 +62,9 @@ void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_limit(); + + *size -= *start; } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/46991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Gerrit-Change-Number: 46991 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/lynxpoint: Use correct port mask for LPT-LP
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47035 ) Change subject: sb/intel/lynxpoint: Use correct port mask for LPT-LP ...................................................................... sb/intel/lynxpoint: Use correct port mask for LPT-LP Lynxpoint LP only has 4 SATA ports. Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47035/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 167f4df..f4ad6cd 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -12,6 +12,12 @@ #include "iobp.h" #include "pch.h" +#if CONFIG(INTEL_LYNXPOINT_LP) +#define SATA_PORT_MASK 0x0f +#else +#define SATA_PORT_MASK 0x3f +#endif + typedef struct southbridge_intel_lynxpoint_config config_t; static inline u32 sir_read(struct device *dev, int idx) @@ -95,7 +101,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); + pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -121,7 +127,7 @@ /* SATA Initialization register */ reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0x3f) << 24; + reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); @@ -241,7 +247,7 @@ * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8); + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365 Gerrit-Change-Number: 47035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45690 ) Change subject: soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax ...................................................................... soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/pci_int.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sleepstates.asl M src/soc/amd/stoneyridge/acpi/usb.asl 5 files changed, 403 insertions(+), 345 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45690/1 diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index b2322ea..ca5f249 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -21,7 +21,7 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 4)) { + If (\PCNT >= 4) { Return (Package () { \_SB.P000, @@ -29,7 +29,7 @@ \_SB.P002, \_SB.P003 }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { + } ElseIf (\PCNT>= 2) { Return (Package () { \_SB.P000, diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 0f3d882..b0bd57b 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -133,9 +133,9 @@ Method(_STA, 0) { if (PIRA) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */ @@ -145,14 +145,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { @@ -162,9 +162,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -174,9 +174,9 @@ Method(_STA, 0) { if (PIRB) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */ @@ -186,14 +186,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { @@ -203,9 +203,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -215,9 +215,9 @@ Method(_STA, 0) { if (PIRC) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */ @@ -227,14 +227,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { @@ -244,9 +244,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -256,9 +256,9 @@ Method(_STA, 0) { if (PIRD) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */ @@ -268,14 +268,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { @@ -285,9 +285,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -297,9 +297,9 @@ Method(_STA, 0) { if (PIRE) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */ @@ -309,14 +309,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -338,9 +338,9 @@ Method(_STA, 0) { if (PIRF) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */ @@ -350,14 +350,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { @@ -367,9 +367,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -379,9 +379,9 @@ Method(_STA, 0) { if (PIRG) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */ @@ -391,14 +391,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { @@ -408,9 +408,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG= Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -420,9 +420,9 @@ Method(_STA, 0) { if (PIRH) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */ @@ -432,14 +432,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { @@ -449,8 +449,8 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 1820f7a..f302b04 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -9,14 +9,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -104,12 +104,12 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ /* @@ -142,8 +142,8 @@ CreateWordField(F1BF, 0, F1SZ) CreateByteField(F1BF, 2, F1DA) - Store(3, F1SZ) - Store(\PWRS, F1DA) + F1SZ = 3 + F1DA= \PWRS \_SB.ALIB(1, F1BF) @@ -151,23 +151,23 @@ Method(OSFL, 0){ - if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if (CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } - Return(OSVR) + Return (OSVR) } OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) @@ -356,74 +356,75 @@ { Acquire(FDAS, 0xffff) - if(LEqual(Arg1, 0)) { + if (Arg1 == 0) { Switch(ToInteger(Arg0)) { Case(Package() {5, 15, 24}) { - Store(One, PG1A) + PG1A = One } Case(Package() {6, 7, 8, 11, 12, 18}) { - Store(One, PG2_) + PG2_ = One } } /* put device into D0 */ Switch(ToInteger(Arg0)) { Case(5) { - Store(0x00, I0TD) - Store(One, I0PD) - Store(I0DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I0DS, Local0) + I0TD = 0x00 + I0PD = One + Local0 = I0DS + while(Local0 != 0x7) { + Local0 = I0DS } } Case(6) { - Store(0x00, I1TD) - Store(One, I1PD) - Store(I1DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I1DS, Local0) + I1TD = 0x00 + I1PD = One + Local0 = I1DS + while(Local0 != 0x7) { + Local0 = I1DS } } Case(7) { - Store(0x00, I2TD) - Store(One, I2PD) - Store(I2DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I2DS, Local0) + I2TD = 0x00 + I2PD = One + Local0 = I2DS + while(Local0 != 0x7) { + Local0 = I2DS } } - Case(8) {Store(0x00, I3TD) - Store(One, I3PD) - Store(I3DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I3DS, Local0) + Case(8) { + I3TD = 0x00 + I3PD = One + Local0 = I3DS + while(Local0 != 0x7) { + Local0 = I3DS } } Case(11) { - Store(0x00, U0TD) - Store(One, U0PD) - Store(U0DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(U0DS, Local0) + U0TD = 0x00 + U0PD = One + Local0 = U0DS + while(Local0 != 0x7) { + Local0 = U0DS } } Case(12) { - Store(0x00, U1TD) - Store(One, U1PD) - Store(U1DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(U1DS, Local0) + U1TD = 0x00 + U1PD = One + Local0 = U1DS + while(Local0 != 0x7) { + Local0 = U1DS } } /* todo Case(15) { STD0()} */ /* SATA */ Case(18) { U2D0()} /* EHCI */ Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ - Store(0x00, SDTD) - Store(One, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(SDDS, Local0) + SDTD = 0x00 + SDPD = One + Local0 = SDDS + while(Local0 != 0x7) { + Local0 = SDDS } } } @@ -432,77 +433,78 @@ Switch(ToInteger(Arg0)) { Case(5) { - Store(Zero, I0PD) - Store(I0DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I0DS, Local0) + I0PD = Zero + Local0 = I0DS + while(Local0 != 0x0) { + Local0 = I0DS } - Store(0x03, I0TD) + I0TD = 0x03 } Case(6) { - Store(Zero, I1PD) - Store(I1DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I1DS, Local0) + I1PD = Zero + Local0 = I1DS + while(Local0 != 0x0) { + Local0 = I1DS } - Store(0x03, I1TD) + I1TD = 0x03 } - Case(7) { - Store(Zero, I2PD) - Store(I2DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I2DS, Local0) + Case(7) { + I2PD = Zero + Local0 = I2DS + while(Local0 != 0x0) { + Local0 = I2DS } - Store(0x03, I2TD)} + I2TD = 0x03 + } Case(8) { - Store(Zero, I3PD) - Store(I3DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I3DS, Local0) + I3PD = Zero + Local0 = I3DS + while(Local0 != 0x0) { + Local0 = I3DS } - Store(0x03, I3TD) + I3TD = 0x03 } Case(11) { - Store(Zero, U0PD) - Store(U0DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(U0DS, Local0) + U0PD = Zero + Local0 = U0DS + while(Local0 != 0x0) { + Local0 = U0DS } - Store(0x03, U0TD) + U0TD = 0x03 } Case(12) { - Store(Zero, U1PD) - Store(U1DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(U1DS, Local0) + U1PD = Zero + Local0 = U1DS + while(Local0 != 0x0) { + Local0 = U1DS } - Store(0x03, U1TD) + U1TD = 0x03 } /* todo Case(15) { STD3()} */ /* SATA */ Case(18) { U2D3()} /* EHCI */ Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ - Store(Zero, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(SDDS, Local0) + SDPD = Zero + Local0 = SDDS + while(Local0 != 0x0) { + Local0 = SDDS } - Store(0x03, SDTD) + SDTD = 0x03 } } /* Turn off Power */ - if(LEqual(I0TD, 3)) { - if(LEqual(SATD, 3)) { - if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } + if (I0TD == 3) { + if (SATD == 3) { + if (SDTD == 3) { PG1A = Zero } } } - if(LEqual(I1TD, 3)) { - if(LEqual(I2TD, 3)) { - if(LEqual(I3TD, 3)) { - if(LEqual(U0TD, 3)) { - if(LEqual(U1TD, 3)) { - if(LEqual(U2TD, 3)) { - Store(Zero, PG2_) + if (I1TD == 3) { + if (I2TD == 3) { + if (I3TD == 3) { + if (U0TD == 3) { + if (U1TD == 3) { + if (U2TD == 3) { + PG2_ = Zero } } } @@ -515,53 +517,53 @@ Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { + if (\XHCE == one) { + if (U3TD != 0x03) { FDDC(23, 3) } } - if(LNotEqual(U2TD, 0x03)) { + if (U2TD != 0x03) { FDDC(18, 3) } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { + if (\XHCE == one) { + if (U3TD == 0x03) { FDDC(23, 0) } } - if(LEqual(U2TD, 0x03)) { + if (U2TD == 0x03) { FDDC(18, 0) } - if(LEqual(\UT0E, zero)) { - if(LNotEqual(U0TD, 0x03)) { + if (\UT0E == zero) { + if (U0TD != 0x03) { FDDC(11, 3) } } - if(LEqual(\UT1E, zero)) { - if(LNotEqual(U1TD, 0x03)) { + if (\UT1E == zero) { + if (U1TD != 0x03) { FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { + if (\IC0E == zero) { + if (I0TD != 0x03) { FDDC(5, 3) } } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { + if (\IC1E == zero) { + if (I1TD != 0x03) { FDDC(6, 3) } } - if(LEqual(\IC2E, zero)) { - if(LNotEqual(I2TD, 0x03)) { + if (\IC2E == zero) { + if (I2TD != 0x03) { FDDC(7, 3) } } - if(LEqual(\IC3E, zero)) { - if(LNotEqual(I3TD, 0x03)) { + if (\IC3E == zero) { + if (I3TD != 0x03) { FDDC(8, 3) } } @@ -574,20 +576,20 @@ */ Method(PWGC,2, Serialized) { - And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */ - if(Arg1) { - Or(Arg0, Local0, Local0) + Local0 = PGA3 & 0xdf /* do SwUsb3SlpShutdown below */ + if (Arg1) { + Local0 |= Arg0 } else { - Not(Arg0, Local1) - And(Local1, Local0, Local0) + Local1 = ~Arg0 + Local0 &= Local1 } Store(Local0, PGA3) - if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */ - Store(PGA3, Local0) - And(Arg0, Local0, Local0) - while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */ - Store(PGA3, Local0) - And(Arg0, Local0, Local0) + if (Arg0 == 0x20) { /* if SwUsb3SlpShutdown */ + Local0 = PGA3 + Local0 &= Arg0 + while(!Local0) { /* wait SwUsb3SlpShutdown to complete */ + Local0 = PGA3 + Local0 &= Arg0 } } } diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 88c6efc..03d28bb 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -3,25 +3,25 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) If (CONFIG(HAVE_ACPI_RESUME)) { - Store(0x0D, SSFG) + SSFG = 0x0D } If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSFG & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index 3c62b33..bf39c94 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -67,10 +67,10 @@ Return(XHD0) } Method(_ON) { - Store(0x01, XHD0) + XHD0 = 0x01 } Method(_OFF) { - Store(0x00, XHD0) + XHD0 = 0x00 } } PowerResource(P3U3, 0, 0) { @@ -78,10 +78,10 @@ Return(XHD3) } Method(_ON) { - Store(0x01, XHD3) + XHD3 = 0x01 } Method(_OFF) { - Store(0x00, XHD3) + XHD3 = 0x00 } } @@ -92,10 +92,10 @@ Return(EHD0) } Method(_ON) { - Store(0x01, EHD0) + EHD0 = 0x01 } Method(_OFF) { - Store(0x00, EHD0) + EHD0 = 0x00 } } PowerResource(P3U2, 0, 0) { @@ -103,10 +103,10 @@ Return(EHD3) } Method(_ON) { - Store(0x01, EHD3) + EHD3 = 0x01 } Method(_OFF) { - Store(0x00, EHD3) + EHD3 = 0x00 } } } @@ -121,33 +121,33 @@ Method(U2D3,0, Serialized) { - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (ESIM, SSIM) + if (EH10 != Zero) { + EHBA = EH10 + EHME = One + SSIM = ESIM } - if (LEqual(E_PS, 3)) { - Store (Zero, RQTY) - Store (One, RQ18) + if (E_PS == 3) { + RQTY = Zero + RQ18 = One - Store (U2SR, Local0) + Local0 = U2SR while (Local0) { - Store (U2SR, Local0) + Local0 = U2SR } - Store (Zero, U2PD) + U2PD = Zero - Store (U2DS, Local0) - while (LNotEqual(Local0, Zero)) { - Store (U2DS, Local0) + Local0 = U2DS + while (Local0 != Zero) { + Local0 = U2DS } - Store (0x03,U2TD) + U2TD = 0x03 - if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ + if (U3TD == 0x03) { /* Shutdown USB2 PLL */ PWGC (0x40, 0) - Store (One, U2RP) + U2RP = One } } } @@ -155,115 +155,115 @@ Method(U2D0,0, Serialized) { PWGC (0x40, 1) - Store (Zero, U2RP) - Store (0x00,U2TD) + U2RP = Zero + U2TD = 0x00 - Store (Zero, U2TD) - Store (One, U2PD) + U2TD = Zero + U2PD = One - Store (U2DS, Local0) - while (LNotEqual(Local0,0x7)) { - Store (U2DS, Local0) + Local0 = U2DS + while (Local0 != 0x7) { + Local0 = U2DS } - Store (One, RQTY) - Store (One, RQ18) - Store (U2SR, Local0) - while (LNot(Local0)) { - Store (U2SR, Local0) + RQTY = One + RQ18 = One + Local0 = U2SR + while (!Local0) { + Local0 = U2SR } - Store (EHID, EH2C) + EH2C = EHID - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (SSIM, ESIM) + if (EH10 != Zero) { + EHBA = EH10 + EHME = One + ESIM = SSIM } - Store (ES54, EH54) - Store (ES64, EH64) + EH54 = ES54 + EH64 = ES64 } Method(LXFW,3, Serialized) //Load Xhci FirmWare { - Store (One, FWLM) /* Firmware Load Mode */ - Store (Arg0, ROAM) /* ROM/RAM */ - Store (Arg1, UA04) - Store (Arg2, UA08) - Store (One, FPLS) /* Firmware Preload Start */ - Store (FPLC, Local0) /* Firmware Preload Complete */ - while (LNot(Local0)) { - Store (FPLC, Local0) + FWLM = One /* Firmware Load Mode */ + ROAM = Arg0 /* ROM/RAM */ + UA04 = Arg1 + UA08 = Arg2 + FPLS = One /* Firmware Preload Start */ + Local0 = FPLC /* Firmware Preload Complete */ + while (!Local0) { + Local0 = FPLC } - Store (Zero, FPLS) + FPLS = Zero } Method(U3D3,0, Serialized) { - if (LEqual(U_PS, 3)) { + if (U_PS == 3) { X0_S () - Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ - And (PGA3, 0x20, Local0) - while (LNot(Local0)) { /* wait for it to complete */ - And (PGA3, 0x20, Local0) + PGA3 |= 0x20 /* SwUsb3SlpShutdown */ + Local0 = PGA3 & 0x20 + while (!Local0) { /* wait for it to complete */ + Local0 = PGA3 & 0x20 } - Store (One, UD3P) /* U3P_D3Cold_PWRDN */ + UD3P = One /* U3P_D3Cold_PWRDN */ - Store (Zero, U3PD) /* PwrOnDev */ - Store (U3DS, Local0) + U3PD = Zero /* PwrOnDev */ + Local0 = U3DS while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ - Store (U3DS, Local0) + Local0 = U3DS } - Store (0x3, U3TD) /* TargetedDeviceState */ + U3TD = 0x3 /* TargetedDeviceState */ - Store (One, U3RP) /* USB3_RefClk_Pwdn */ + U3RP = One /* USB3_RefClk_Pwdn */ - if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ - And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ - Store (One, U2RP) /* USB2_RefClk_Pwdn */ + if (U2TD == 0x3) { /* If EHCI targeted in D3cold */ + PGA3 &= 0x9f /* SwUsb2S5RstB */ + U2RP = One /* USB2_RefClk_Pwdn */ } - Store (Zero, U3PG) /* XhcPwrGood */ - Store (One, U3PS) /* Usb3PowerSel */ + U3PG = Zero /* XhcPwrGood */ + U3PS = One /* Usb3PowerSel */ } } Method(U3D0,0, Serialized) { - Store (Zero, U3PS) /* Usb3PowerSel */ - Store (One, U3PG) /* XhcPwrGood */ + U3PS = Zero /* Usb3PowerSel */ + U3PG = One /* XhcPwrGood */ - Store (Zero, U2RP) - Store (Zero, U3RP) + U2RP = Zero + U3RP = Zero - And (PGA3, 0xdf, Local0) - Or (Local0, 0x40, Local0) - Store (Local0, PGA3) /* SwUsb2S5RstB */ + Local0 = PGA3 & 0xdf + Local0 |= 0x40 + PGA3 = Local0 /* SwUsb2S5RstB */ - Store (Zero, U3TD) /* TargetedDeviceState */ - Store (One, U3PD) /* PwrOnDev */ + U3TD = Zero /* TargetedDeviceState */ + U3PD = One /* PwrOnDev */ - Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ - while (LNot(Lequal(Local0, 0x7))) { - Store (U3DS, Local0) + Local0 = U3DS /* wait for RstBState, RefClkOkState, PwrRstBState */ + while (Local0 != 0x7) { + Local0 = U3DS } - Store (U3PY, Local0) /* USB3 PHY Lock */ - while (LNot(Local0)) { - Store (U3PY, Local0) + Local0 = U3PY /* USB3 PHY Lock */ + while (!Local0) { + Local0 = U3PY } - Store (Zero, U3PR) /* U3P_RESTORE_RESET */ + U3PR = Zero /* U3P_RESTORE_RESET */ - Store (AUSS, Local0) /* AutoSizeStart */ - if (LNotEqual(Local0,1)) { - Store(One, AUSS) + Local0 = AUSS /* AutoSizeStart */ + if (Local0 != 1) { + AUSS = One } - Store (AUSS, Local0) - while (LNotEqual(Local0,1)) { - Store (AUSS, Local0) + Local0 = AUSS + while (Local0 != 1) { + Local0 = AUSS } LXFW (1, FW00, FW01) @@ -271,9 +271,9 @@ X0_R () - Store (One, U3PR) /* U3P_RESTORE_RESET */ - Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ - Store (One, U3TD) /* TargetedDeviceState */ + U3PR = One /* U3P_RESTORE_RESET */ + UD3P = Zero /* U3P_D3Cold_PWRDN */ + U3TD = One /* TargetedDeviceState */ } Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ @@ -313,66 +313,122 @@ Method(X0_S,0) { - Store (XH2C, XHID) - Store (0x00000000, IDEX) Store (DATA, S000) - Store (0x00000004, IDEX) Store (DATA, S004) - Store (0x00000008, IDEX) Store (DATA, S008) - Store (0x0000000c, IDEX) Store (DATA, S00C) - Store (0x00000018, IDEX) Store (DATA, S018) - Store (0x0000001c, IDEX) Store (DATA, S01C) - Store (0x00000020, IDEX) Store (DATA, S020) - Store (0x00000030, IDEX) Store (DATA, S030) - Store (0x00000118, IDEX) Store (DATA, S118) - Store (0x00000158, IDEX) Store (DATA, S158) - Store (0x00000198, IDEX) Store (DATA, S198) - Store (0x000001d8, IDEX) Store (DATA, S1D8) - Store (0x00000300, IDEX) Store (DATA, S300) - Store (0x00000304, IDEX) Store (DATA, S304) - Store (0x00000308, IDEX) Store (DATA, S308) - Store (0x0000030c, IDEX) Store (DATA, S30C) - Store (0x00000310, IDEX) Store (DATA, S310) - Store (0x40000028, IDEX) Store (DATA, S428) - Store (0x40000038, IDEX) Store (DATA, S438) - Store (0x4000003c, IDEX) Store (DATA, S43C) - Store (0x40000058, IDEX) Store (DATA, S458) - Store (0x40000068, IDEX) Store (DATA, S468) - Store (0x4000006c, IDEX) Store (DATA, S46C) - Store (0x40000070, IDEX) Store (DATA, S470) - Store (0x40000080, IDEX) Store (DATA, S480) - Store (0x40000084, IDEX) Store (DATA, S484) - Store (0x40000088, IDEX) Store (DATA, S488) - Store (0x4000008c, IDEX) Store (DATA, S48C) + XHID = XH2C + IDEX = Zero + S000 = DATA + IDEX = 0x00000004 + S004 = DATA + IDEX = 0x00000008 + S008 = DATA + IDEX = 0x0000000C + S00C = DATA + IDEX = 0x00000018 + S018 = DATA + IDEX = 0x0000001C + S01C = DATA + IDEX = 0x00000020 + S020 = DATA + IDEX = 0x00000030 + S030 = DATA + IDEX = 0x00000118 + S118 = DATA + IDEX = 0x00000158 + S158 = DATA + IDEX = 0x00000198 + S198 = DATA + IDEX = 0x000001D8 + S1D8 = DATA + IDEX = 0x00000300 + S300 = DATA + IDEX = 0x00000304 + S304 = DATA + IDEX = 0x00000308 + S308 = DATA + IDEX = 0x0000030C + S30C = DATA + IDEX = 0x00000310 + S310 = DATA + IDEX = 0x40000028 + S428 = DATA + IDEX = 0x40000038 + S438 = DATA + IDEX = 0x4000003C + S43C = DATA + IDEX = 0x40000058 + S458 = DATA + IDEX = 0x40000068 + S468 = DATA + IDEX = 0x4000006C + S46C = DATA + IDEX = 0x40000070 + S470 = DATA + IDEX = 0x40000080 + S480 = DATA + IDEX = 0x40000084 + S484 = DATA + IDEX = 0x40000088 + S488 = DATA + IDEX = 0x4000008C + S48C = DATA } Method(X0_R,0) { - Store (XHID, XH2C) - Store (0x00000000, IDEX) Store (S000, DATA) - Store (0x00000004, IDEX) Store (S004, DATA) - Store (0x00000008, IDEX) Store (S008, DATA) - Store (0x0000000c, IDEX) Store (S00C, DATA) - Store (0x00000018, IDEX) Store (S018, DATA) - Store (0x0000001c, IDEX) Store (S01C, DATA) - Store (0x00000020, IDEX) Store (S020, DATA) - Store (0x00000030, IDEX) Store (S030, DATA) - Store (0x00000118, IDEX) Store (S118, DATA) - Store (0x00000158, IDEX) Store (S158, DATA) - Store (0x00000198, IDEX) Store (S198, DATA) - Store (0x000001d8, IDEX) Store (S1D8, DATA) - Store (0x00000300, IDEX) Store (S300, DATA) - Store (0x00000304, IDEX) Store (S304, DATA) - Store (0x00000308, IDEX) Store (S308, DATA) - Store (0x0000030c, IDEX) Store (S30C, DATA) - Store (0x00000310, IDEX) Store (S310, DATA) - Store (0x40000028, IDEX) Store (S428, DATA) - Store (0x40000038, IDEX) Store (S438, DATA) - Store (0x4000003c, IDEX) Store (S43C, DATA) - Store (0x40000058, IDEX) Store (S458, DATA) - Store (0x40000068, IDEX) Store (S468, DATA) - Store (0x4000006c, IDEX) Store (S46C, DATA) - Store (0x40000070, IDEX) Store (S470, DATA) - Store (0x40000080, IDEX) Store (S480, DATA) - Store (0x40000084, IDEX) Store (S484, DATA) - Store (0x40000088, IDEX) Store (S488, DATA) - Store (0x4000008c, IDEX) Store (S48C, DATA) + XH2C = XHID + IDEX = Zero + DATA = S000 + IDEX = 0x000000004 + DATA = S004 + IDEX = 0x000000008 + DATA = S008 + IDEX = 0x00000000C + DATA = S00C + IDEX = 0x000000018 + DATA = S018 + IDEX = 0x00000001C + DATA = S01C + IDEX = 0x000000020 + DATA = S020 + IDEX = 0x00000030 + DATA = S030 + IDEX = 0x00000118 + DATA = S118 + IDEX = 0x00000158 + DATA = S158 + IDEX = 0x00000198 + DATA = S198 + IDEX = 0x000001D8 + DATA = S1D8 + IDEX = 0x00000300 + DATA = S300 + IDEX = 0x00000304 + DATA = S304 + IDEX = 0x00000308 + DATA = S308 + IDEX = 0x0000030C + DATA = S30C + IDEX = 0x00000310 + DATA = S310 + IDEX = 0x40000028 + DATA = S428 + IDEX = 0x40000038 + DATA = S438 + IDEX = 0x4000003C + DATA = S43C + IDEX = 0x40000058 + DATA = S458 + IDEX = 0x40000068 + DATA = S468 + IDEX = 0x4000006C + DATA = S46C + IDEX = 0x40000070 + DATA = S470 + IDEX = 0x40000080 + DATA = S480 + IDEX = 0x40000084 + DATA = S484 + IDEX = 0x40000088 + DATA = S488 + IDEX = 0x4000008C + DATA = S48C } -- To view, visit https://review.coreboot.org/c/coreboot/+/45690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00 Gerrit-Change-Number: 45690 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/broadwell/sata.c: Don't enable Bus Master
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47026 ) Change subject: soc/intel/broadwell/sata.c: Don't enable Bus Master ...................................................................... soc/intel/broadwell/sata.c: Don't enable Bus Master Bus Master is not required and reference code does not set it. Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47026/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index ab73dbd..8b2c513 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -44,9 +44,8 @@ printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300 Gerrit-Change-Number: 47026 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: src: Remove unused include <cpu/x86/smm.h>
by HAOUAS Elyes (Code Review) 31 Jan '21

31 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43993 ) Change subject: src: Remove unused include <cpu/x86/smm.h> ...................................................................... src: Remove unused include <cpu/x86/smm.h> Change-Id: I866d9f72c866f22ec1b72ed90900ca11be98e267 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43993/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 458e2d5..5a0f210 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -7,7 +7,6 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <types.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index c76c8d2..eb6bad7 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -6,7 +6,6 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <console/console.h> #include <types.h> #include <string.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444a..9ae854d 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -4,7 +4,6 @@ #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866d9f72c866f22ec1b72ed90900ca11be98e267 Gerrit-Change-Number: 43993 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch: Drop some `config_of` uses
by Angel Pons (Code Review) 30 Jan '21

30 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46890 ) Change subject: soc/intel/broadwell/pch: Drop some `config_of` uses ...................................................................... soc/intel/broadwell/pch: Drop some `config_of` uses There's no need to die here. Also simplifies merging with Haswell. Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/lpc.c 2 files changed, 24 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46890/1 diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/soc/intel/broadwell/pch/early_pch.c index a6a8aff..0c4dd7b 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/soc/intel/broadwell/pch/early_pch.c @@ -53,7 +53,10 @@ /* Lookup device tree in romstage */ const struct device *const dev = pcidev_on_root(0x1f, 0); - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + if (!dev || !dev->chip_info) + return; + + const struct soc_intel_broadwell_pch_config *config = dev->chip_info; pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index ea3c702..2114a84 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -132,8 +132,6 @@ { u16 reg16; const char *state; - /* Get the chip configuration */ - const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? @@ -165,12 +163,16 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* GPE setup based on device tree configuration */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); + if (dev->chip_info) { + const struct soc_intel_broadwell_pch_config *config = dev->chip_info; - /* SMI setup based on device tree configuration */ - enable_alt_smi(config->alt_gp_smi_en); + /* GPE setup based on device tree configuration */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); + + /* SMI setup based on device tree configuration */ + enable_alt_smi(config->alt_gp_smi_en); + } } static void pch_misc_init(struct device *dev) @@ -339,7 +341,10 @@ static void pch_init_deep_sx(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + + if (!config) + return; if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -570,7 +575,6 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - const struct soc_intel_broadwell_pch_config *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); @@ -586,10 +590,13 @@ pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); /* LPC Generic IO Decode range. */ - pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); + if (dev->chip_info) { + const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); + } } static void pch_lpc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80 Gerrit-Change-Number: 46890 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable building for Chrome OS
by EricR Lai (Code Review) 29 Jan '21

29 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48111 ) Change subject: mb/google/brya: Enable building for Chrome OS ...................................................................... mb/google/brya: Enable building for Chrome OS Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/variants/baseboard/gpio.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 6 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/48111/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 4348ef5..1d29f90 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -3,6 +3,7 @@ select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_ALDERLAKE if BOARD_GOOGLE_BASEBOARD_BRYA @@ -11,6 +12,11 @@ def_bool n select SYSTEM_TYPE_LAPTOP +config CHROMEOS + bool + default y + select VBOOT_LID_SWITCH + config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index cdd0eb6..3735e20 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -1,7 +1,12 @@ bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c new file mode 100644 index 0000000..e222ca2 --- /dev/null +++ b/src/mainboard/google/brya/chromeos.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} + diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index f15f25e..5930430 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -26,4 +26,7 @@ } /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> } diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 0f5b298..8179e2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { @@ -25,3 +26,12 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 8531f7d..6e31712 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -10,5 +10,6 @@ * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Gerrit-Change-Number: 48111 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46241 ) Change subject: soc/intel/icelake: Convert to ASL 2.0 syntax ...................................................................... soc/intel/icelake: Convert to ASL 2.0 syntax Change-Id: I4fdc68e87c02681407430fcd2fbb61d0b0f1656e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/icelake/acpi/pch_hda.asl M src/soc/intel/icelake/acpi/scs.asl 2 files changed, 19 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46241/1 diff --git a/src/soc/intel/icelake/acpi/pch_hda.asl b/src/soc/intel/icelake/acpi/pch_hda.asl index f292901..13b4d3d 100644 --- a/src/soc/intel/icelake/acpi/pch_hda.asl +++ b/src/soc/intel/icelake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } diff --git a/src/soc/intel/icelake/acpi/scs.asl b/src/soc/intel/icelake/acpi/scs.asl index dbc61c8..5883e1e 100644 --- a/src/soc/intel/icelake/acpi/scs.asl +++ b/src/soc/intel/icelake/acpi/scs.asl @@ -37,22 +37,22 @@ Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us - Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG /* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_EMMC) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR } Device (CARD) @@ -90,23 +90,23 @@ Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */ /* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_SDX) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */ /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR } Device (CARD) -- To view, visit https://review.coreboot.org/c/coreboot/+/46241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdc68e87c02681407430fcd2fbb61d0b0f1656e Gerrit-Change-Number: 46241 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/butterfly: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46171 ) Change subject: mb/google/butterfly: Convert to ASL 2.0 syntax ...................................................................... mb/google/butterfly: Convert to ASL 2.0 syntax Change-Id: I85edf649a5170a1658fb135b797c1c6e1d2a9d70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/butterfly/acpi/mainboard.asl M src/mainboard/google/butterfly/acpi/platform.asl M src/mainboard/google/butterfly/acpi/thermal.asl 3 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46171/1 diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 02ef905..3552e29 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -8,7 +8,7 @@ Name (_HID, EisaId("PNP0C0D")) Method (_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.LIDF, \LIDS) + \LIDS = \_SB.PCI0.LPCB.EC0.LIDF Return (\LIDS) } } diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl index f59e485..7c8a815 100644 --- a/src/mainboard/google/butterfly/acpi/platform.asl +++ b/src/mainboard/google/butterfly/acpi/platform.asl @@ -15,16 +15,16 @@ { /* Update in case state changed while asleep */ /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ADPT + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDF, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDF + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.LID0, 0x80) } diff --git a/src/mainboard/google/butterfly/acpi/thermal.asl b/src/mainboard/google/butterfly/acpi/thermal.asl index 4c6f6d9..ed381cd 100644 --- a/src/mainboard/google/butterfly/acpi/thermal.asl +++ b/src/mainboard/google/butterfly/acpi/thermal.asl @@ -21,10 +21,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,13 +50,13 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from EC - Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTMP // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 // Adjust by offset to get Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85edf649a5170a1658fb135b797c1c6e1d2a9d70 Gerrit-Change-Number: 46171 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gizmosphere/gizmo2: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46168 ) Change subject: mb/gizmosphere/gizmo2: Convert to ASL 2.0 syntax ...................................................................... mb/gizmosphere/gizmo2: Convert to ASL 2.0 syntax Change-Id: I0a4af7ebe6114338c2e8fb5fdf39a1de2cd47138 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46168/1 diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl index 47dd146..fc26c30 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl @@ -30,9 +30,9 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4af7ebe6114338c2e8fb5fdf39a1de2cd47138 Gerrit-Change-Number: 46168 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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