coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 04 Feb '21

04 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48173 ) Change subject: HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64 ...................................................................... HACK: src/commonlib/fsp_relocate: Fix compilation under x86_64 Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/fsp_relocate.c M src/vendorcode/intel/Makefile.inc M src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h 4 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/48173/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 5d326b6..0e5556f 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -12,6 +12,8 @@ /* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ #include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> +#define UINTN size_t + #include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> /* Restore original packing policy. */ diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 23ae587..3a8d491 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -6,18 +6,38 @@ # ProcessorBind.h isn't just about types. There's compiler definitions as well # as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for # a fixed width type. +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include else ifeq ($(CONFIG_UDK_2015_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_2017_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_202005_BINDING),y) +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_32),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32 +endif +ifeq ($(CONFIG_ARCH_ALL_STAGES_X86_64),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64 +endif CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include endif diff --git a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h index 2f77042..0394e02 100644 --- a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h +++ b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32/ProcessorBind.h @@ -275,7 +275,7 @@ /// /// GCC specific method for EFIAPI calling convention. /// - #define EFIAPI __attribute__((cdecl)) + #define EFIAPI #else /// /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h index 69eba65..5d3ed0c 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h @@ -278,11 +278,15 @@ /// #define EFIAPI __cdecl #elif defined(__GNUC__) +#ifndef __x86_64__ /// /// GCC specific method for EFIAPI calling convention. /// #define EFIAPI __attribute__((cdecl)) #else + #define EFIAPI +#endif +#else /// /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI /// is the standard. -- To view, visit https://review.coreboot.org/c/coreboot/+/48173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Gerrit-Change-Number: 48173 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: drivers/intel/fsp2_0: Fix running on x86_64
by Patrick Rudolph (Code Review) 04 Feb '21

04 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48174 ) Change subject: drivers/intel/fsp2_0: Fix running on x86_64 ...................................................................... drivers/intel/fsp2_0: Fix running on x86_64 The FSP info header was using size_t instead of the native data type used to compile the binary. This caused the FSP-M to not being recognized by the loader. Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 6 files changed, 92 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/48174/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 03b9c2b..4e88795 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -1,5 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only +config PLATFORM_USES_FSP2_X86_32 + bool + default y + help + The FSP 2.0 build runs in x86_32 protected mode. + +config PLATFORM_USES_FSP2_X86_64 + bool + depends on !PLATFORM_USES_FSP2_X86_32 + default y + help + The FSP 2.0 build runs in x86_64 long mode. + config PLATFORM_USES_FSP2_0 bool default n diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f237a37..7f09cc6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -4,6 +4,7 @@ #define _FSP2_0_INFO_HEADER_H_ #include <types.h> +#include <commonlib/bsd/compiler.h> #define FSP_HDR_OFFSET 0x94 #if CONFIG(PLATFORM_USES_FSP2_2) @@ -16,24 +17,46 @@ #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t fsp_revision; - size_t image_size; - uintptr_t image_base; + uint32_t image_size; + uint32_t image_base; uint16_t image_attribute; uint8_t spec_version; uint16_t component_attribute; - size_t cfg_region_offset; - size_t cfg_region_size; - size_t temp_ram_init_entry; - size_t temp_ram_exit_entry; - size_t notify_phase_entry_offset; - size_t memory_init_entry_offset; - size_t silicon_init_entry_offset; - size_t multi_phase_si_init_entry_offset; + uint32_t cfg_region_offset; + uint32_t cfg_region_size; + uint32_t temp_ram_init_entry; + uint32_t temp_ram_exit_entry; + uint32_t notify_phase_entry_offset; + uint32_t memory_init_entry_offset; + uint32_t silicon_init_entry_offset; + uint32_t multi_phase_si_init_entry_offset; char image_id[sizeof(uint64_t) + 1]; uint8_t revision; -}; +} __packed; +#else +struct fsp_header { + uint32_t fsp_revision; + uint64_t image_size; + uint64_t image_base; + uint16_t image_attribute; + uint8_t spec_version; + uint16_t component_attribute; + uint64_t cfg_region_offset; + uint64_t cfg_region_size; + uint64_t temp_ram_init_entry; + uint64_t temp_ram_exit_entry; + uint64_t notify_phase_entry_offset; + uint64_t memory_init_entry_offset; + uint64_t silicon_init_entry_offset; + uint64_t multi_phase_si_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +} __packed; +#endif + enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 979cff3..370fcd3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -21,6 +21,7 @@ uint8_t Reserved[23]; } __packed; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct FSPM_ARCH_UPD { /// /// Revision of the structure. For FSP v2.0 value is 1. @@ -31,12 +32,12 @@ /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - void *NvsBufferPtr; + uint32_t NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - void *StackBase; + uint32_t StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -53,7 +54,40 @@ uint32_t BootMode; uint8_t Reserved1[8]; } __packed; - +#else +struct FSPM_ARCH_UPD { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + uint8_t Revision; + uint8_t Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + uint64_t NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + uint64_t StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + uint32_t StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + uint32_t BootLoaderTolumSize; + /// + /// Current boot mode. + /// + uint32_t BootMode; + uint8_t Reserved1[8]; +} __packed; +#endif struct FSPS_ARCH_UPD { /// /// Revision of the structure. For FSP v2.2 value is 1. diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 27e34fe..d62888e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -101,7 +101,7 @@ return; /* MRC cache found */ - arch_upd->NvsBufferPtr = data; + arch_upd->NvsBufferPtr = (uintptr_t)data; printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size); } @@ -142,7 +142,7 @@ stack_end) != CB_SUCCESS) return CB_ERR; - arch_upd->StackBase = (void *)stack_begin; + arch_upd->StackBase = stack_begin; return CB_SUCCESS; } @@ -237,7 +237,7 @@ fsp_version = fsp_memory_settings_version(hdr); - upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) die_with_post_code(POST_INVALID_VENDOR_BINARY, @@ -291,7 +291,7 @@ post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ - fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); post_code(POST_FSP_MEMORY_INIT); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index ee04630..73de605 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -15,7 +15,7 @@ if (!fsps_hdr.notify_phase_entry_offset) die("Notify_phase_entry_offset is zero!\n"); - fspnotify = (void *) (fsps_hdr.image_base + + fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, &notify_params); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..d180060 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -85,7 +85,7 @@ struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; - supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) die_with_post_code(POST_INVALID_VENDOR_BINARY, @@ -111,7 +111,7 @@ logo_entry = soc_load_logo(upd); /* Call SiliconInit */ - silicon_init = (void *) (hdr->image_base + + silicon_init = (void *) (uintptr_t)(hdr->image_base + hdr->silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); @@ -139,7 +139,7 @@ return; /* Call MultiPhaseSiInit */ - multi_phase_si_init = (void *) (hdr->image_base + + multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + hdr->multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Gerrit-Change-Number: 48174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 29

Change in coreboot[master]: nb/intel/haswell: Create RMRR for iGPU
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46990 ) Change subject: nb/intel/haswell: Create RMRR for iGPU ...................................................................... nb/intel/haswell: Create RMRR for iGPU Taken from Broadwell. Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46990/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 0e7967f..f48ef61 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -63,6 +63,21 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Gerrit-Change-Number: 46990 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/zork: C-state IO base address aligment
by chris wang (Code Review) 03 Feb '21

03 Feb '21

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44135 to review the following change. Change subject: mb/google/zork: C-state IO base address aligment ...................................................................... mb/google/zork: C-state IO base address aligment Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ib98d34af518439d338326446c20601867ad31690 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/iomap.h 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44135/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..039e3c2 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -257,6 +257,12 @@ help Base address for the ACPI registers. +config PICASSO_CSTATE_IO_BASE_ADDR + hex + default 0x413 + help + Base address for the CC6 State. + config PICASSO_CONSOLE_UART bool "Use Picasso UART controller for console" default n diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 6b9ad2a..360b348 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -64,12 +64,12 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 #define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define ACPI_CPU_CONTROL CONFIG_PICASSO_CSTATE_IO_BASE_ADDR #define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x0c) /* 6 bytes */ /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98d34af518439d338326446c20601867ad31690 Gerrit-Change-Number: 44135 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: ec/hp/kbc1126: Wait a longer time after the first command
by Pablo Stebler (Code Review) 03 Feb '21

03 Feb '21

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44750 ) Change subject: ec/hp/kbc1126: Wait a longer time after the first command ...................................................................... ec/hp/kbc1126: Wait a longer time after the first command This prevents the fans from running at full speed on ProBook 6360b and EliteBook 8470p (because the fan control command was not sent). Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb --- M src/ec/hp/kbc1126/ec.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44750/1 diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 5c11fed..ff47649 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -115,6 +115,13 @@ struct ec_hp_kbc1126_config *conf = dev->chip_info; ec_setports(conf->ec_data_port, conf->ec_cmd_port); kbc1126_kbdled(conf->ec_ctrl_reg, 0); + + /* The EC needs additional time to process the first command on a cold + boot. */ + int timeout = 0x17ff; + while ((inb(conf->ec_cmd_port) & KBD_IBF) && --timeout) + udelay(10); + if (kbc1126_thermalinit(conf->ec_ctrl_reg, conf->ec_fan_ctrl_value) < 0) printk(BIOS_DEBUG, "KBC1126: error when initializing fan control.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb Gerrit-Change-Number: 44750 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: soc/ti/am335x/header.c: Add missing include
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44738 ) Change subject: soc/ti/am335x/header.c: Add missing include ...................................................................... soc/ti/am335x/header.c: Add missing include Use of 'offsetof' needs stddef. Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/ti/am335x/header.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44738/1 diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index 9edfdd0..9ed9937 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <stddef.h> #include <stdint.h> #include <symbols.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Gerrit-Change-Number: 44738 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42521 ) Change subject: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references ...................................................................... mb/pcengines/apu2: Remove gpio1_ and gpio2_ references The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL also takes advantage of this property. Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c 1 file changed, 8 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42521/1 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index c249c2d..03eddce 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -10,27 +10,20 @@ static u32 gpio_read_wrapper(u32 iomux_gpio) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - return gpio0_read32(gpio & 0xff); - else if (gpio >= 0x100 && gpio < 0x200) - return gpio1_read32(gpio & 0xff); - else if (gpio >= 0x200 && gpio < 0x300) - return gpio2_read32(gpio & 0xff); + return gpio0_read32(gpio & 0x3ff); - die("Invalid GPIO"); } static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - gpio0_write32(gpio & 0xff, setting); - else if (gpio >= 0x100 && gpio < 0x200) - gpio1_write32(gpio & 0xff, setting); - else if (gpio >= 0x200 && gpio < 0x300) - gpio2_write32(gpio & 0xff, setting); + gpio0_write32(gpio & 0x3ff, setting); } void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) @@ -70,9 +63,9 @@ * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - if (gpio1_read8(0x02) & BIT0) + if (read_gpio(GPIO_49)) index |= BIT0; - if (gpio1_read8(0x06) & BIT0) + if (read_gpio(GPIO_50)) index |= BIT1; return index; -- To view, visit https://review.coreboot.org/c/coreboot/+/42521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Gerrit-Change-Number: 42521 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

5 29

Change in coreboot[master]: cpu/x86/name/name.c: Clean up includes
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44315 ) Change subject: cpu/x86/name/name.c: Clean up includes ...................................................................... cpu/x86/name/name.c: Clean up includes Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/name/name.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44315/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index a7d2c70..d4f50b6 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -2,8 +2,8 @@ #include <string.h> #include <arch/cpu.h> -#include <device/device.h> #include <cpu/x86/name.h> +#include <stdint.h> void fill_processor_name(char *processor_name) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Gerrit-Change-Number: 44315 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45815 ) Change subject: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> ...................................................................... mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/dedede/variants/drawcia/variant.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45815/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 88e9de7..321d165 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <fw_config.h> #include <sar.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Gerrit-Change-Number: 45815 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44737 ) Change subject: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include ...................................................................... soc/samsung/exynos5250/include/soc/cpu.h: Add missing include Use of 'KiB' needs <commonlib/bsd/helpers.h> Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/include/soc/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44737/1 diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index aa5a2e8..6d5c18a 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -3,6 +3,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H #define CPU_SAMSUNG_EXYNOS5250_CPU_H +#include <commonlib/bsd/helpers.h> #include <symbols.h> /* Base address registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Gerrit-Change-Number: 44737 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020