coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 26 Jan '21

26 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46166 ) Change subject: mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax ...................................................................... mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax Change-Id: Ibc7c1249e6d497a948d2c4b41e4d163d031d37f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46166/1 diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl index 2544617..ae4ef30 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl @@ -21,10 +21,10 @@ Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc7c1249e6d497a948d2c4b41e4d163d031d37f2 Gerrit-Change-Number: 46166 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/51nb/x210: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 26 Jan '21

26 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46074 ) Change subject: mb/51nb/x210: Convert to ASL 2.0 syntax ...................................................................... mb/51nb/x210: Convert to ASL 2.0 syntax Change-Id: I02bfc5207ef584bc259407b5bdb14fae4c470bcd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/acpi/ec.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46074/1 diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index 78e156c..581e1e7 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -45,10 +45,10 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACIN, \PWRS) + \PWRS = ACIN /* Initialize LID switch state */ - Store (LIDC, \LIDS) + \LIDS = LIDC } /* KEY_BRIGHTNESSUP */ @@ -72,14 +72,14 @@ /* AC event */ Method (_Q0D) { - Store (ACIN, \PWRS) + \PWRS = ACIN Notify (AC, 0x80) } /* Lid event */ Method (_Q0E) { - Store (LIDC, \LIDS) + \LIDS = LIDC Notify (LID0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02bfc5207ef584bc259407b5bdb14fae4c470bcd Gerrit-Change-Number: 46074 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44904 ) Change subject: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads Update microcode using a core specific semaphore. The SDM and most of the BWGs suggest doing this. Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44904/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..4c4de09 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -25,6 +25,7 @@ #include <symbols.h> #include <timer.h> #include <thread.h> +#include <lib.h> #include <security/intel/stm/SmmStm.h> @@ -97,6 +98,9 @@ uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; + uint32_t microcode_lock_ht; /* 1 special microcode locking for Intel HT CPUs */ + uint32_t apic_core_id_mask; + uint32_t hyperthreading_lock[CONFIG_MAX_CPUS/2]; } __packed; /* This also needs to match the assembly code for saved MSR encoding. */ @@ -216,6 +220,31 @@ sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); + sp->microcode_lock_ht = !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + if (sp->microcode_lock_ht) { + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + + sp->apic_core_id_mask = 1UL << log2_ceil(core_ids); + sp->apic_core_id_mask <<= log2_ceil(threads); + } else { + sp->apic_core_id_mask = 0; + } + memset(sp->hyperthreading_lock, 0, sizeof(sp->hyperthreading_lock)); } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..abf0549 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -3,6 +3,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> /* The SIPI vector is responsible for initializing the APs in the system. It @@ -33,6 +34,12 @@ .long 0 ap_count: .long 0 +apic_core_id_mask: +.long 0 +hyperthreading_lock: +.space CONFIG_MAX_CPUS/2 +microcode_lock_ht: +.long 0 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) #define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) @@ -115,6 +122,35 @@ test %edx, %edx jnz microcode_done + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + je load_microcode + + /* Get this CPU's LAPIC ID */ + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl (%esi), %ecx + shr $24, %ecx + + movl apic_core_id_mask, %eax + andl %eax, %ecx +1: + bt $0, %eax + jc 1f + shr $1, %eax + shr $1, %ecx + jmp 1b +1: + /* ecx now contains the core ID */ + movl $(hyperthreading_lock), %ebx + shl $2, %ecx + addl %ecx, %ebx + +lock_ht_semaphore: + /* Lock the core specific semaphore */ + lock bts $0, (%ebx) + jc lock_ht_semaphore + jmp load_microcode + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode @@ -136,6 +172,15 @@ wrmsr popa + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + jne 1f + + xor %eax, %eax + mov %eax, (%ebx) + je microcode_done + +1: /* Unconditionally unlock microcode loading. */ cmpl $0xffffffff, microcode_lock je microcode_done -- To view, visit https://review.coreboot.org/c/coreboot/+/44904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Gerrit-Change-Number: 44904 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: cpu/x86/sipi_vector: Use spinlock
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47710 ) Change subject: cpu/x86/sipi_vector: Use spinlock ...................................................................... cpu/x86/sipi_vector: Use spinlock Change-Id: I3ea5ea370dc75af3544ec903bd9b18399113dec1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/sipi_vector_c_handler.c 1 file changed, 6 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47710/1 diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c index fa11748..47cd11a 100644 --- a/src/cpu/x86/sipi_vector_c_handler.c +++ b/src/cpu/x86/sipi_vector_c_handler.c @@ -6,11 +6,14 @@ #include <arch/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/amd/mtrr.h> +#include <smp/spinlock.h> asmlinkage void sipi_secondary_early_entry(struct sipi_params *const params, int cpu_num); #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) +DECLARE_SPIN_LOCK(microcode_lock) + static void sipi_update_microcode(struct sipi_params *params) { /* Determine if one should check microcode versions. */ @@ -25,23 +28,15 @@ return; /* Determine if parallel microcode loading is allowed. */ - if (params->microcode_lock != 0xffffffff) { - - /* Protect microcode loading. */ - asm volatile( - "\tlock_microcode:\n" - "\tlock bts $0, %0\n" - "\tjc lock_microcode\n" - : "=m"(params->microcode_lock) - : "m"(params->microcode_lock)); - } + if (params->microcode_lock != 0xffffffff) + spin_lock(&microcode_lock); /* Load new microcode. */ intel_microcode_load_unlocked((void *)((uintptr_t)params->microcode_ptr)); /* Unconditionally unlock microcode loading. */ if (params->microcode_lock != 0xffffffff) - params->microcode_lock = 0; + spin_unlock(&microcode_lock); } static void sipi_set_mtrrs(const struct sipi_params *const params) -- To view, visit https://review.coreboot.org/c/coreboot/+/47710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea5ea370dc75af3544ec903bd9b18399113dec1 Gerrit-Change-Number: 47710 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: cpu/x86/sipi_vector: Only run microcode update on Intel CPUs
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47708 ) Change subject: cpu/x86/sipi_vector: Only run microcode update on Intel CPUs ...................................................................... cpu/x86/sipi_vector: Only run microcode update on Intel CPUs AMD CPUs do not update the microcode as part of the AP bringup. Only run microcode updates on Intel. This will reduce the size of the sipi vector on AMD CPUs. Change-Id: Ifb750c62ad80283ad4b486f9f8533ef41497084f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/sipi_vector_c_handler.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47708/1 diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c index 4d06535..fa11748 100644 --- a/src/cpu/x86/sipi_vector_c_handler.c +++ b/src/cpu/x86/sipi_vector_c_handler.c @@ -103,7 +103,12 @@ */ asmlinkage void sipi_secondary_early_entry(struct sipi_params *const params, int cpu_num) { - sipi_update_microcode(params); + /* + * For Intel CPUs refer to Intel SDM: + * Chapter 8.4.4.2 Typical AP Initialization Sequence + */ + if (cpu_is_intel()) + sipi_update_microcode(params); sipi_set_mtrrs(params); sipi_enable_caches(params); sipi_enable_sse(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/47708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb750c62ad80283ad4b486f9f8533ef41497084f Gerrit-Change-Number: 47708 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cpu/x86/mpinit/sipi_vector: Move code to C
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46821 ) Change subject: cpu/x86/mpinit/sipi_vector: Move code to C ...................................................................... cpu/x86/mpinit/sipi_vector: Move code to C Use a C helper function to do early x86 CPU init. The code is compiled without SSE and without optimizations. Use existing code to update microcode. Tested on Supermicro X11SSH: * The microcode is still updated on all core * All cores call into MPinit code Change-Id: Ib6c2ffa2ce8c42eee9f3fe8ec8cff933942207ca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S A src/cpu/x86/sipi_vector_c_handler.c M src/include/cpu/x86/mp.h 5 files changed, 150 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46821/1 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 66b1a68..54e2397 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -26,8 +26,11 @@ $(eval $(call create_class_compiler,sipi_vec,$(ARCH-$(TARGET_STAGE)-y))) sipi_vec-generic-ccopts = $(rmodule_$(ARCH-$(TARGET_STAGE)-y)-generic-ccopts) +sipi_vec-generic-ccopts += -mno-sse -O0 sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector.S +sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector_c_handler.c +sipi_vec-$(CONFIG_PARALLEL_MP) += $(top)/src/cpu/intel/microcode/microcode.c $(SIPI_DOTO): $$(sipi_vec-objs) $(COMPILER_RT_sipi_vec) $(LD_sipi_vec) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_sipi_vec) --whole-archive --start-group $(sipi_vec-objs) --no-whole-archive $(COMPILER_RT_sipi_vec) --end-group diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4870529..83d71190 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -83,29 +83,6 @@ int num_records; }; -/* This needs to match the layout in the .module_parametrs section. */ -struct sipi_params { - uint16_t gdtlimit; - uint32_t gdt; - uint16_t unused; - uint32_t idt_ptr; - uint32_t stack_top; - uint32_t stack_size; - uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ - uint32_t microcode_ptr; - uint32_t msr_table_ptr; - uint32_t msr_count; - uint32_t c_handler; - atomic_t ap_count; -} __packed; - -/* This also needs to match the assembly code for saved MSR encoding. */ -struct saved_msr { - uint32_t index; - uint32_t lo; - uint32_t hi; -} __packed; - /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ extern char _binary_sipi_vector_start[]; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..52ca6ba 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,10 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/cr.h> -#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> #include <arch/ram_segs.h> +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) +#define CR0_CLEAR_FLAGS \ + (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | CR0_MP) +#define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -34,11 +38,6 @@ ap_count: .long 0 -#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) -#define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) -#define CR0_CLEAR_FLAGS \ - (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | CR0_MP) - .text .code16 .global _start @@ -101,102 +100,13 @@ /* Save CPU number. */ mov %ecx, %esi - /* Determine if one should check microcode versions. */ - mov microcode_ptr, %edi - test %edi, %edi - jz microcode_done /* Bypass if no microde exists. */ + /* sipi_secondary_early_entry(ap_start_params), preserve proper stack alignment */ + sub $8, %esp + push %esi + leal ap_start_params, %eax + push %eax + call sipi_secondary_early_entry - /* Get the Microcode version. */ - mov $1, %eax - cpuid - mov $IA32_BIOS_SIGN_ID, %ecx - rdmsr - /* If something already loaded skip loading again. */ - test %edx, %edx - jnz microcode_done - - /* Determine if parallel microcode loading is allowed. */ - cmpl $0xffffffff, microcode_lock - je load_microcode - - /* Protect microcode loading. */ -lock_microcode: - lock bts $0, microcode_lock - jc lock_microcode - -load_microcode: - /* Load new microcode. */ - mov $IA32_BIOS_UPDT_TRIG, %ecx - xor %edx, %edx - mov %edi, %eax - /* The microcode pointer is passed in pointing to the header. Adjust - * pointer to reflect the payload (header size is 48 bytes). */ - add $48, %eax - pusha - wrmsr - popa - - /* Unconditionally unlock microcode loading. */ - cmpl $0xffffffff, microcode_lock - je microcode_done - - xor %eax, %eax - mov %eax, microcode_lock - -microcode_done: - /* - * Load MSRs. Each entry in the table consists of: - * 0: index, - * 4: value[31:0] - * 8: value[63:32] - */ - mov msr_table_ptr, %edi - mov msr_count, %ebx - test %ebx, %ebx - jz 1f - -#if CONFIG(X86_AMD_FIXED_MTRRS) - /* Allow modification of RdDram and WrDram bits */ - mov $SYSCFG_MSR, %ecx - rdmsr - or $SYSCFG_MSR_MtrrFixDramModEn, %eax - wrmsr -#endif - -load_msr: - mov (%edi), %ecx - mov 4(%edi), %eax - mov 8(%edi), %edx - wrmsr - add $12, %edi - dec %ebx - jnz load_msr - -#if CONFIG(X86_AMD_FIXED_MTRRS) - mov $SYSCFG_MSR, %ecx - rdmsr - and $~SYSCFG_MSR_MtrrFixDramModEn, %eax - wrmsr -#endif - -1: - /* Enable caching. */ - mov %cr0, %eax - and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax - mov %eax, %cr0 - -#if CONFIG(SSE) - /* Enable sse instructions. */ - mov %cr4, %eax - orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax - mov %eax, %cr4 -#endif - - /* c_handler(cpu_num), preserve proper stack alignment */ - sub $12, %esp - push %esi /* cpu_num */ - mov c_handler, %eax - call *%eax halt_jump: hlt jmp halt_jump diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c new file mode 100644 index 0000000..dab6c65 --- /dev/null +++ b/src/cpu/x86/sipi_vector_c_handler.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> +#include <arch/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/amd/mtrr.h> + +asmlinkage void sipi_secondary_early_entry(struct sipi_params *params, int cpu_num); + +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) + +static void sipi_update_microcode(struct sipi_params *params) +{ + /* Determine if one should check microcode versions. */ + if (!params->microcode_ptr) + return; + + /* Get the Microcode version. */ + const uint32_t rev = get_current_microcode_rev(); + + /* If something already loaded skip loading again. */ + if (rev) + return; + + /* Determine if parallel microcode loading is allowed. */ + if (params->microcode_lock != 0xffffffff) { + + /* Protect microcode loading. */ + asm volatile( + "\tlock_microcode:\n" + "\tlock bts $0, %0\n" + "\tjc lock_microcode\n" + : "=m"(params->microcode_lock) + : "m"(params->microcode_lock)); + } + + /* Load new microcode. */ + intel_microcode_load_unlocked((void *)((uintptr_t)params->microcode_ptr)); + + /* Unconditionally unlock microcode loading. */ + if (params->microcode_lock != 0xffffffff) + params->microcode_lock = 0; +} + +static void sipi_set_mtrrs(struct sipi_params *params) +{ + struct saved_msr *smsr; + if (!params->msr_count) + return; + + if (CONFIG(X86_AMD_FIXED_MTRRS)) { + msr_t msr; + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + } + + /* Load MSRs */ + smsr = (struct saved_msr *)params->msr_table_ptr; + for (size_t i = 0; i < params->msr_count; i++) { + msr_t msr = {.lo = smsr->lo, .hi = smsr->hi}; + wrmsr(smsr->index, msr); + } + + if (CONFIG(X86_AMD_FIXED_MTRRS)) { + msr_t msr; + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + } +} + +static void sipi_enable_caches(struct sipi_params *params) +{ + /* Enable caches */ + CRx_TYPE cr0 = read_cr0(); + cr0 &= ~(CR0_CLEAR_FLAGS_CACHE_ENABLE); + write_cr0(cr0); +} + +static void sipi_enable_sse(struct sipi_params *params) +{ + /* Enable sse instructions. */ + if (CONFIG(SSE)) { + CRx_TYPE cr4 = read_cr4(); + cr4 &= (CR4_OSFXSR | CR4_OSXMMEXCPT); + write_cr4(cr4); + } +} + +/* + * Early CPU bringup hook. + * - No Microcode has been loaded + * - Caches are disabled + * - SSE is disabled + * - MTRR haven't been set up + * + * You have been warned, expect the unexpected! + */ +asmlinkage void sipi_secondary_early_entry(struct sipi_params *params, int cpu_num) +{ + sipi_update_microcode(params); + sipi_set_mtrrs(params); + sipi_enable_caches(params); + sipi_enable_sse(params); + + void (*doit)(int) = (void (*)(int))params->c_handler; + doit(cpu_num); +} \ No newline at end of file diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b2704eb..75cbe26 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -143,4 +143,27 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* This needs to match the layout in the .module_parametrs section. */ +struct sipi_params { + uint16_t gdtlimit; + uint32_t gdt; + uint16_t unused; + uint32_t idt_ptr; + uint32_t stack_top; + uint32_t stack_size; + uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ + uint32_t microcode_ptr; + uint32_t msr_table_ptr; + uint32_t msr_count; + uint32_t c_handler; + atomic_t ap_count; +} __packed; + +/* This also needs to match the assembly code for saved MSR encoding. */ +struct saved_msr { + uint32_t index; + uint32_t lo; + uint32_t hi; +} __packed; + #endif /* _X86_MP_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c2ffa2ce8c42eee9f3fe8ec8cff933942207ca Gerrit-Change-Number: 46821 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: cpu/x86: Use class for sipi module
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46820 ) Change subject: cpu/x86: Use class for sipi module ...................................................................... cpu/x86: Use class for sipi module This removes the hardcoded single assembly file and allows to add more source files to the SIPI rmodule. This can be used to link C code for reusing existing code. Change-Id: I701eb340688e43591dfca77f55106c5b2f1a7735 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Makefile.inc M src/cpu/x86/Makefile.inc 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46820/1 diff --git a/Makefile.inc b/Makefile.inc index bf33f8b..6b015f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -93,7 +93,7 @@ ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_microcode verstage +classes-y := ramstage romstage bootblock decompressor postcar sipi_vec smm smmstub cpu_microcode verstage # Add a special 'all' class to add sources to all stages $(call add-special-class,all) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..66b1a68 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -23,10 +23,14 @@ ifeq ($(CONFIG_PARALLEL_MP),y) $(TARGET_STAGE)-srcs += $(SIPI_BIN).manual endif -rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S -$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ +$(eval $(call create_class_compiler,sipi_vec,$(ARCH-$(TARGET_STAGE)-y))) +sipi_vec-generic-ccopts = $(rmodule_$(ARCH-$(TARGET_STAGE)-y)-generic-ccopts) + +sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $$(sipi_vec-objs) $(COMPILER_RT_sipi_vec) + $(LD_sipi_vec) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_sipi_vec) --whole-archive --start-group $(sipi_vec-objs) --no-whole-archive $(COMPILER_RT_sipi_vec) --end-group $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) -- To view, visit https://review.coreboot.org/c/coreboot/+/46820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I701eb340688e43591dfca77f55106c5b2f1a7735 Gerrit-Change-Number: 46820 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: cpu/x86/mp_init: Move BSP microcode update to MPINIT
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47712 ) Change subject: cpu/x86/mp_init: Move BSP microcode update to MPINIT ...................................................................... cpu/x86/mp_init: Move BSP microcode update to MPINIT Unify when microcode loading is done on Intel platforms. Update the microcode of the BSP on Intel CPUs as part of the MP init code. On most CPUs this does nothing as microcodes have been loaded earlier already. Change-Id: Id626a48b68523b7f9488c004ac4cb88342671b65 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/xeon_sp/cpx/cpu.c 4 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47712/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index eddff53..b8d2008 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -521,11 +521,20 @@ return ret; } -static void init_bsp(struct bus *cpu_bus) +static void init_bsp(struct bus *cpu_bus, struct mp_params *p) { struct device_path cpu_path; struct cpu_info *info; + /* + * Make sure BSP is using the microcode from cbfs. + * + * On recent Intel platform this is does nothing as the microcode + * is loaded using FIT or in previous stages. + */ + if (cpu_is_intel()) + intel_microcode_load_unlocked(p->microcode_pointer); + /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); @@ -573,7 +582,7 @@ int num_cpus; atomic_t *ap_count; - init_bsp(cpu_bus); + init_bsp(cpu_bus, p); if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { printk(BIOS_CRIT, "Invalid MP parameters\n"); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 0ae170b..b6a83d7 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -176,9 +176,6 @@ { *microcode = intel_microcode_find(); *parallel = 1; - - /* Make sure BSP is using the microcode from cbfs */ - intel_microcode_load_unlocked(*microcode); } #endif diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c3fe40b..cf9756d 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -151,7 +151,6 @@ return; microcode_patch = intel_microcode_find(); - intel_microcode_load_unlocked(microcode_patch); init_cpus(); } diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d1bcbd7..b87a98a 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -193,8 +193,6 @@ if (!microcode_patch) printk(BIOS_ERR, "microcode not found in CBFS!\n"); - intel_microcode_load_unlocked(microcode_patch); - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id626a48b68523b7f9488c004ac4cb88342671b65 Gerrit-Change-Number: 47712 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: /cpu/x86/mp_init: Rename c_handler to ap_handler
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47713 ) Change subject: /cpu/x86/mp_init: Rename c_handler to ap_handler ...................................................................... /cpu/x86/mp_init: Rename c_handler to ap_handler Change-Id: I434fba031581b8acb685c82c5219238fe5b5cab2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S M src/cpu/x86/sipi_vector_c_handler.c M src/include/cpu/x86/mp.h 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47713/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index b8d2008..0eee001 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -324,7 +324,7 @@ sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uintptr_t)&ap_init; + sp->ap_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index cb5641a..394c03a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -13,7 +13,7 @@ * The SIPI vector is responsible for initializing the APs in the system. It * sets up protected mode and assigns a stack to each AP before it calls into * C code. The C handler loads microcode, sets up MSRs, and enables caching - * before calling into the MP init provided 'c_handler' + * before calling into the MP init provided 'ap_handler' */ #if ENV_X86_64 #define uintptr_t quad @@ -41,7 +41,7 @@ .uintptr_t 0 msr_count: .long 0 -c_handler: +ap_handler: .uintptr_t 0 ap_count: .long 0 diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c index 47cd11a..25e4587 100644 --- a/src/cpu/x86/sipi_vector_c_handler.c +++ b/src/cpu/x86/sipi_vector_c_handler.c @@ -108,6 +108,6 @@ sipi_enable_caches(params); sipi_enable_sse(params); - void (*doit)(int) = (void (*)(int))params->c_handler; + void (*doit)(int) = (void (*)(int))params->ap_handler; doit(cpu_num); } diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index ed6e91f..26c3e05 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -155,7 +155,7 @@ uintptr_t microcode_ptr; uintptr_t msr_table_ptr; uint32_t msr_count; - uintptr_t c_handler; + uintptr_t ap_handler; atomic_t ap_count; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/47713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fba031581b8acb685c82c5219238fe5b5cab2 Gerrit-Change-Number: 47713 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/auron: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 25 Jan '21

25 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46169 ) Change subject: mb/google/auron: Convert to ASL 2.0 syntax ...................................................................... mb/google/auron: Convert to ASL 2.0 syntax Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/auron/acpi/mainboard.asl M src/mainboard/google/auron/acpi/thermal.asl M src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl 8 files changed, 60 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46169/1 diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 746efa2..1be0a47 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -19,8 +19,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_WLAN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_WLAN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index 4be4fe5..fd05e73 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -24,10 +24,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,56 +53,56 @@ Method (TCHK, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } Method (_TMP, 0, Serialized) { // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for EC to re-poll Sleep (1000) // Re-read temperature from EC - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) @@ -110,7 +110,7 @@ /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (CTL_TDP_THRESHOLD_OFF)) } Else { Return (CTOK (CTL_TDP_THRESHOLD_ON)) @@ -119,7 +119,7 @@ /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) } Else { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) @@ -132,14 +132,14 @@ PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 /* Enable Power Limit */ \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT) @@ -147,7 +147,7 @@ Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 /* Disable Power Limit */ \_SB.PCI0.MCHC.CTLD () @@ -159,18 +159,18 @@ PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index b3dc42c..4b0ac45 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -24,7 +24,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -59,7 +59,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -70,8 +70,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -96,7 +96,7 @@ { Store (BUDDY_NIC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl index 76e1f2e..35f0d3c 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl @@ -31,17 +31,17 @@ Method(_DSM, 0x4, NotSerialized) { - If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */ + If (Arg0 == ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")) /* I2C-HID UUID */ { - If (LEqual(Arg2, Zero)) /* DSM Function */ + If (Arg2 == 0) /* DSM Function */ { /* Function 0: Query function, return based on revision */ - If (LEqual(Arg1, One)) /* Arg1 DSM Revision */ + If (Arg1 == 1) /* Arg1 DSM Revision */ { /* Revision 1: Function 0 supported */ Return(Buffer(One) { 0x03 }) } - } ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */ + } ElseIf (Arg2 == 1) /* Function 1 : HID Function */ { Return(0x0020) /* HID Descriptor Address */ } @@ -52,7 +52,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -63,8 +63,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -100,7 +100,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -111,8 +111,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 4329d5f..9ca592f 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -30,8 +30,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -39,7 +39,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -141,8 +141,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -150,7 +150,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -188,8 +188,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -198,7 +198,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Gerrit-Change-Number: 46169 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020