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Change in coreboot[master]: Documentation: Add documentation on jenkins builders
by Martin Roth (Code Review) 25 Jan '21

25 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43984 ) Change subject: Documentation: Add documentation on jenkins builders ...................................................................... Documentation: Add documentation on jenkins builders Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 --- A Documentation/community/builders.md 1 file changed, 391 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43984/1 diff --git a/Documentation/community/builders.md b/Documentation/community/builders.md new file mode 100644 index 0000000..bc35bcc --- /dev/null +++ b/Documentation/community/builders.md @@ -0,0 +1,391 @@ +# Jenkins builder setup and configuration + +## How to set up a new jenkins builder + +### Contact a jenkins admin + +Let a jenkins admin know that you’re interested in setting up a jenkins +build system. + +For a permanent build system, this should generally be a dedicated +machine that is not generally being used for other purposes. The +coreboot builds are very intensive. + +It's also best to be aware that although we don't know of any security +issues, the jenkins-node image is run with the privileged flag which +gives the container root access to the build machine. See +[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-ru… +about why this is discouraged. + +It's recommended that you give an admin root access on your machine so +that they can reset it in case of a failure. This is not a requirement, +as the system can just be disabled until someone is available to fix any +issues. + +Currently active Jenkins admins: +* Patrick Georgi: + * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de) + * IRC: pgeorgi + + +### Build Machine requirements + +For a builder, we need a fast system with lots of threads and plenty of +RAM. The builder builds and stores the git repos and output in tmpfs +along with the ccache save area, so if there isn't enough memory, the +builds will slow down because of smaller ccache areas and can run into +"out of storage space" errors. + +#### Current Build Machines + +To give an idea of what a suitable build machine might be, currently the +coreboot project has 3 active jenkins build machines. + +* Congenialbuilder - 128 threads, 256GiB RAM + * Fastest Passing coreboot gerrit build: 4 min, 30 sec + * Slowest Passing coreboot gerrit build: 9 min, 56 sec + + +* Gleeful builder - 64 thread, 64GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 6 sec + * Slowest Passing coreboot gerrit build, 34 min + + +* Ultron (9elements) - 48 threads, 128GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 32 sec + * Slowest Passing coreboot gerrit build: 44 min + + +### Jenkins Builds + +There are a number of builds handled by the coreboot jenkins builders, +for a number of different projects - coreboot, flashrom, memtest86+, +em100, etc. Many of these have builders for their current master branch +as well as gerrit and coverity builds. + +You can see all the builds here: +[https://qa.coreboot.org/](https://qa.coreboot.org/) + +Most of the time on the builders is taken up by the coreboot master and +gerrit builds. + +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) + + +* [coreboot master build](https://qa.coreboot.org/job/coreboot/) + ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) + + +### Stress test the machine + +Test the machine to make sure that building won't stress the hardware +too much. Install stress-ng, then run the stress test for at least an +hour. + +On a system with 32 cores, it was tested with this command: + +``` +$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +``` + +You can watch the temperature with the sensors package or with ‘acpi -t’ +if your machine supports that. + +You can check for thermal throttling by running this command and seeing +if the values go down on any of the cores after it's been running for a +while. + +``` +$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +``` + +If the machine throttles or resets, you probably need to upgrade the +cooling system. + + +## jenkins-server docker installation + + +### Manual Installation + +If you’ve met all the above requirements, and an admin has agreed to set +up the builder in jenkins, you’re ready to go on to the next steps. + + +### Set up your network so jenkins can talk to the container + +Expose a local port through any firewalls you might have on your router. +This would generally be in the port forwarding section, and you'd just +forward a port (typically 49151) from the internet directly to the +builder’s IP address. + +You might also want to set up a port to forward to port 22 on your +machine and set up openssh so you can manage the machine remotely. + + +### Install and set up docker + +Install docker by following the directions on the docker site. These +instructions keep changing, so just check the latest information. + +[https://docs.docker.com/engine/install/](https://docs.docker.com/engine/install/) + + +#### Set up environment variables + +To make configuration and the later commands easier, these should go in +your shell's .rc file. Note that you only need to set them if you're +using something other than the default. + +``` +# Set the port used on your machine to connect to jenkins. +export COREBOOT_JENKINS_PORT=49151 + +# Set the revision of the container from docker hub +export DOCKER_COMMIT=65718760fa + +# Set the location of where the jenkins cache directory will be. +export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache" + +# Set the name of the container +export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins" +``` + +Make sure any variables needed are set in your environment before +continuing to the next step. + + +### Using the Makefile for docker installation + +From the coreboot directory, run + +``` +make -C util/docker help +``` + +This will show you the available targets and variables needed: + +``` +Commands for working with docker images: + coreboot-sdk - Build coreboot-sdk container + upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com + coreboot-jenkins-node - Build coreboot-jenkins-node container + upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com + doc.coreboot.org - Build doc.coreboot.org container + clean-coreboot-containers - Remove all docker coreboot containers + clean-coreboot-images - Remove all docker coreboot images + docker-clean - Remove docker coreboot containers & images + +Commands for using docker images + docker-build-coreboot - Build coreboot under coreboot-sdk + <BUILD_CMD=target> + docker-abuild - Run abuild under coreboot-sdk + <ABUILD_ARGS='-a -B'> + docker-what-jenkins-does - Run 'what-jenkins-does' target + docker-shell - Bash prompt in coreboot-jenkins-node + <USER=root or USER=coreboot> + docker-jenkins-server - Run coreboot-jenkins-node image (for server) + docker-jenkins-attach - Open shell in running jenkins server + docker-build-docs - Build the documentation + docker-livehtml-docs - Run sphinx-autobuild + +Variables: + COREBOOT_JENKINS_PORT=49151 + COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache + COREBOOT_JENKINS_CONTAINER=coreboot_jenkins + COREBOOT_IMAGE_TAG=f2741aa632f + DOCKER_COMMIT=65718760fa +``` + +### Set up the system for the jenkins builder + +As a regular user - *Not root*, run: + +``` +sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} +sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR} +wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar +mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR} +``` + +### Install the coreboot jenkins builder + +``` +make -C util/docker docker-jenkins-server +``` + +Your installation is complete on your side. + +### Tell the Admins that the machine is set up +Let the admins know that the builder is set up so they can set up the +machine profile on qa.coreboot.org. + +They need to know: +* Your external IP address or domain name. If you don’t have a static +IP, make sure you have a dynamic dns hostname configured. +* The port on your machine and firewall that’s exposed for jenkins: +`$COREBOOT_JENKINS_PORT` +* The core count of the machine. +* How much memory is available on the machine. This helps determine +the amount of memory used for ccache. + + +### First build +On the first build after a machine is reset, it will frequently take +20-25 minutes to do the entire what-jenkins-does build while the ccache +is getting filled up and the entire coreboot repo gets downloaded. As +the ccache gets populated, the build time will drop. + + +## Additional Information + + +### How to log in to the docker instance for debugging +``` + $ make -C util/docker docker-jenkins-attach + $ su coreboot + $ cd ~/slave-root/workspace + $ bash +``` + + +WARNING: This should not be used to make changes to the build system, +but just to debug issues. Changes to the build system are highly +discouraged as it leads to situations where patches can pass the build +testing on one builder and fail on another builder. Any changes that are +made in the image will be lost on the next update, so if you +accidentally change something, you can remove the containers and images +and update to get a fresh installation. + + +### How to download containers/images for a fresh installation and remove old containers + +To delete the old containers & images: + +``` +$ docker stop $COREBOOT_JENKINS_CONTAINER +$ docker rm $COREBOOT_JENKINS_CONTAINER +$ docker images # lists all existing images +$ docker rmi XXXX # Use the image ID found in the above command. +``` + +To get and run the new coreboot-jenkins image, change the value in the +`DOCKER_COMMIT` variable to the new image value. + +``` +$ make -C util/docker docker-jenkins-server +``` + +#### Getting ready to push the docker images + +Set up an account on hub.docker.com + +Get an admin to add the account to the coreboot team on hub.docker.com + +[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners) + +Make sure your credentials are configured on your host machine by +running + +``` +$ docker login +``` + +This will prompt you for your docker username, password, and your email +address, and write out to ~/.docker/config.json. Without this file, you +won’t be able to push the images. + +#### Updating the Dockerfiles: + +The coreboot-sdk Dockerfile will need to be updated when any additional +dependencies are added. Both the coreboot-sdk and the +coreboot-jenkins-node Dockerfiles will need to be updated to the new +version number and git commit id anytime the toolchain is updated. Both +files are stored in the coreboot repo under coreboot/util/docker. + +Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) +page before updating the files. + +#### Rebuilding the coreboot-sdk docker image to update the toolchain: + +``` +$ make -C util/docker coreboot-sdk +``` + +This takes a relatively long time. + +#### Test the coreboot-sdk docker image: + +There are two methods of running the docker image - interactively as a +shell, or doing the build directly. Running interactively as a shell is +useful for early testing, because it allows you to update the image +(without any changes getting saved) and re-test builds. This saves the +time of having to rebuild the image for every issue you find. + +#### Running the docker image interactively: + +Run: + +``` +$ make -C util/docker docker-jenkins-server +$ make -C util/docker docker-jenkins-attach +``` + +#### Running the build directly: + +From the coreboot directory: + +``` +$ make -C util/docker docker-build-coreboot +``` + +You’ll also want to test building the other projects and payloads: +ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, +nvramcui, tint... + +#### Pushing the coreboot-sdk image to hub.docker.com for use: + +When you’re satisfied with the testing, push the coreboot-sdk image to +the hub.docker.com + +``` +$ make -C util/docker upload-coreboot-sdk +``` + +#### Building and pushing the coreboot-jenkins-node docker image: + +This docker image is pretty simple, so there’s not really any testing +that needs to be done. + +``` +$ make -C util/docker coreboot-jenkins-node +$ make -C util/docker upload-coreboot-jenkins-node +``` + +### Coverity Setup + +To run coverity jobs, the builder needs to have the tools available, and +to be marked as a coverity builder. + + +#### Set up the Coverity tools + +Download the Linux-64 coverity build tool and decompress it into your +cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable + +[https://scan.coverity.com/download](https://scan.coverity.com/download) + +Rename the directory from its original name +(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a +symlink: + +``` +ln -s cov-analysis-linux64-7.7.0.4 coverity +``` + + +Let the admins know that the ‘coverity’ label can be added to the +builder. -- To view, visit https://review.coreboot.org/c/coreboot/+/43984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 Gerrit-Change-Number: 43984 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Drop enable check from LPD0/LPD3
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46966 ) Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ...................................................................... soc/intel/broadwell: Drop enable check from LPD0/LPD3 When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL. Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 14 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46966/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 91fa758..b03bcdd 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -7,14 +7,8 @@ // Put SerialIO device in D0 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD0, 2, Serialized) +Method (LPD0, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -30,14 +24,8 @@ // Put SerialIO device in D3 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD3, 2, Serialized) +Method (LPD3, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -240,12 +228,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1, \S1EN) + ^^LPD0 (\S1B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1, \S1EN) + ^^LPD3 (\S1B1) } } @@ -311,12 +299,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1, \S2EN) + ^^LPD0 (\S2B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1, \S2EN) + ^^LPD3 (\S2B1) } } @@ -367,12 +355,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1, \S3EN) + ^^LPD0 (\S3B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1, \S3EN) + ^^LPD3 (\S3B1) } } @@ -435,12 +423,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1, \S4EN) + ^^LPD0 (\S4B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1, \S4EN) + ^^LPD3 (\S4B1) } } @@ -503,12 +491,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1, \S5EN) + ^^LPD0 (\S5B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1, \S5EN) + ^^LPD3 (\S5B1) } } @@ -559,12 +547,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1, \S6EN) + ^^LPD0 (\S6B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1, \S6EN) + ^^LPD3 (\S6B1) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Gerrit-Change-Number: 46966 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/poppy: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46221 ) Change subject: mb/google/poppy: Convert to ASL 2.0 syntax ...................................................................... mb/google/poppy: Convert to ASL 2.0 syntax Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl 3 files changed, 55 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46221/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5ad10ef..374c0aa 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -25,7 +25,7 @@ Method (PMOF, 0, Serialized) { /* Make Sure all PMIC outputs are off. */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { CTXS(EN_PP3300_DX_CAM) } } @@ -39,7 +39,7 @@ Method (_ON, 0, Serialized) { PMON() /* Do not reset PMIC across S3 and S0ix cycle */ - if (Lequal (RSTO, 1)) { + if (RSTO == 1) { CTXS(EN_CAM_PMIC_RST_L) Sleep(1) STXS(EN_CAM_PMIC_RST_L) @@ -64,46 +64,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP & ((AVB0 & AVB1) & (AVB2 & AVB3))) { /* Marks the availability of all opregions */ - Store (1, AVBL) + AVBL = 1 } Else { - Store (0, AVBL) + AVBL = 0 } } @@ -321,12 +320,12 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Enable clocks only when a sensor is turned on and both the clocks are disabled */ - If (LNot (LOr (CLE0, CLE1))) { + If (!(CLE0 |CLE1)) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -365,10 +364,10 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - If (LNot (LOr (CLE0, CLE1))) { + If (Local0 == 0) { + If (!(CLE0 |CLE1)) { BODI = 0 BUDI = 0 PSWR = 0 @@ -390,37 +389,37 @@ Name (VSIC, 0) Method (DOVD, 1, Serialized) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 Sleep(1) PMOF() } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 4 */ - If (LLess (VSIC, 4)) { + If (VSIC < 4) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { PMON() VSIO = 3 - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 } Sleep(3) } - Increment (VSIC) + VSIC++ } } } @@ -430,8 +429,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -470,8 +469,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { Sleep(2) CLE0 = 0 \_SB.PCI0.I2C2.PMIC.CLKD() @@ -497,8 +496,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -537,8 +536,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { Sleep(2) CLE1 = 0 \_SB.PCI0.I2C2.PMIC.CLKD() @@ -566,8 +565,8 @@ PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -584,8 +583,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -603,8 +602,8 @@ PowerResource (NVMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -614,8 +613,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { DOVD(0) /* Disable regulator */ STA = 0 } diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index 17fb82b..c3449a7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -6,7 +6,7 @@ { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_FCAM_RST_L) STXS (GPIO_FCAM_PWR_EN) STXS (GPIO_PCH_FCAM_CLK_EN) @@ -22,15 +22,15 @@ * sequence completes */ Sleep (11) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_FCAM_CLK_EN) CTXS (GPIO_FCAM_RST_L) CTXS (GPIO_FCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index a934901..0e31eee 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -6,7 +6,7 @@ { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_RCAM_RST_L) STXS (GPIO_RCAM_PWR_EN) STXS (GPIO_PCH_RCAM_CLK_EN) @@ -21,15 +21,15 @@ * on sequence completes */ Sleep (12) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_RCAM_CLK_EN) CTXS (GPIO_RCAM_RST_L) CTXS (GPIO_RCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6 Gerrit-Change-Number: 46221 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: google/wilco: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46098 ) Change subject: google/wilco: Convert to ASL 2.0 syntax ...................................................................... google/wilco: Convert to ASL 2.0 syntax Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/lid.asl 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46098/1 diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 705988a..6de72e8 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -96,7 +96,7 @@ Printf ("Sensor trip mask: %o", Local0) - If (LNot (Acquire (^PATM, 1000))) { + If (!Acquire (^PATM, 1000)) { /* Handle bits that are set */ While (FindSetRightBit (Local1, Local2)) diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 7531dbf..d552604 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -50,7 +50,7 @@ ^UCSI.INIT () // Initialize LID switch state - Store (R (P1LC), \LIDS) + \LIDS = R (P1LC) } /* diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 3fae71f..c381499 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -8,7 +8,7 @@ Method (_LID, 0, NotSerialized) { - Store (R (P1LC), \LIDS) + \LIDS = R (P1LC) Return (\LIDS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1 Gerrit-Change-Number: 46098 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: ec/compal: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46096 ) Change subject: ec/compal: Convert to ASL 2.0 syntax ...................................................................... ec/compal: Convert to ASL 2.0 syntax Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/compal/ene932/acpi/ac.asl M src/ec/compal/ene932/acpi/battery.asl M src/ec/compal/ene932/acpi/ec.asl 3 files changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46096/1 diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl index b086bf5..cc14b33 100644 --- a/src/ec/compal/ene932/acpi/ac.asl +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -9,7 +9,7 @@ Method (_PSR) { - Store(ADPT, Local0) + Local0 = ADPT Return(Local0) } diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index b3bf157..18c5f89 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -38,13 +38,13 @@ // Method to enable full battery workaround Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } // Method to disable full battery workaround Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } Method (_STA, 0, Serialized) @@ -59,22 +59,22 @@ Method (_BIF, 0, Serialized) { // Update fields from EC - Store (BAM0, Index (PBIF, 0)) - Store (BDC0, Index (PBIF, 1)) - Store (BFC0, Index (PBIF, 2)) - Store (BDV0, Index (PBIF, 4)) - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x0A, Local1) - Store(Local1, Index(PBIF, 5)) - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x03, Local1) - Store (Local1, Index (PBIF, 6)) + PBIF [0] = BAM0 + PBIF [1] = BDC0 + PBIF [2] = BFC0 + PBIF [4] = BDV0 + Local1 = BFC0 / 100 + Local1 *= 10 + PBIF [5] = Local1 + Local1 = BFC0 / 100 + Local1 *= 3 + PBIF [6] = Local1 - Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // model - Store (ToHexString(BSN0), Index (PBIF, 10)) // serial - Store (ToString(BMFN), Index (PBIF, 12)) // vendor + PBIF [9] = ToString (Concatenate (BATD, 0x00)) // model + PBIF [10] = ToHexString (BSN0) // serial + PBIF [12] = ToString (BMFN) // vendor - Store(BDN0, BTNM) // Save the battery number + BTNM = BDN0 // Save the battery number Return (PBIF) } @@ -90,47 +90,47 @@ // // Get battery state from EC and save it for the charging workaround - Store (BST0, Local0) - Store (Local0, Index (PBST, 0)) + Local0 = BST0 + PBST [0] = Local0 // // 1: BATTERY PRESENT RATE/CURRENT // - Store (BAC0, Local1) - Subtract(0xFFFF, Local1, Local1) - Store (Local1, Index (PBST, 1)) + Local1 = BAC0 + Local1 = 0xFFFF - Local1 + PBST [1] = Local1 // // 2: BATTERY REMAINING CAPACITY // - Multiply(BFC0, GAU0, Local1) - Divide(Local1, 0x64, Local2, Local1) + Local1 = BFC0 * GAU0 + Local2 = Local1 % 100 + Local1 /= 100 - If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + If (BFWK && ADPT && !Local0)) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. // https://bugzilla.kernel.org/show_bug.cgi?id=12632 - Store (GAU0, Local2) + Local2 = GAU0 // See if within ~3% of full - ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + Local3 = Local2 >> 5 + If ((Local1 > (Local2 - Local3)) && (Local1 < (Local2+ Local3))) { - Store (Local2, Local1) + Local1 = Local2 } } - Store (Local1, Index (PBST, 2)) + PBST [2] = Local1 // // 3: BATTERY PRESENT VOLTAGE // - Store (BPV0, Index (PBST, 3)) + PBST [3] = BPV0 // Check the Battery Number - If(LNotEqual(BDN0, BTNM)) { + If(BDN0 != BTNM) { Notify(BATX, 0x81) } diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 6b0997e..6370c64 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -253,12 +253,12 @@ Method (_REG, 2, NotSerialized) { // Initialize AC power state - Store (ADPT, \PWRS) + \PWRS = ADPT // Force a read of CPU temperature - Store (CTML, Local0) + Local0 = CTML /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } @@ -323,7 +323,7 @@ // AC Power Connected Method (_Q37, 0, NotSerialized) { - Store (One, \PWRS) + \PWRS = 1 Notify (AC, 0x80) Notify (BATX, 0x80) // TODO ADD CPU power profile @@ -333,7 +333,7 @@ // AC Power Removed Method (_Q38, 0, NotSerialized) { - Store (Zero, \PWRS) + \PWRS = 0 Notify (AC, 0x80) Notify (BATX, 0x80) // TODO ADD CPU power profile @@ -364,7 +364,7 @@ { IF(WLEX) //if Wlan exist { - //TODO Store(WLAT, LANE) + //TODO LANE = WLAT } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21 Gerrit-Change-Number: 46096 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: ec/acpi: Convert 'ec.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46095 ) Change subject: ec/acpi: Convert 'ec.asl' to ASL 2.0 syntax ...................................................................... ec/acpi: Convert 'ec.asl' to ASL 2.0 syntax Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/acpi/ec.asl 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46095/1 diff --git a/src/ec/acpi/ec.asl b/src/ec/acpi/ec.asl index 47c74bd..dd3efac 100644 --- a/src/ec/acpi/ec.asl +++ b/src/ec/acpi/ec.asl @@ -45,8 +45,8 @@ */ Method (WAIT_EC_SC, 2) { - Store (0x7ff, Local0) /* Timeout */ - While (LAnd (LNotEqual (And (EC_SC, Arg0), Arg1), Decrement (Local0))) { + Local0 = 0x7ff /* Timeout */ + While (((EC_SC & Arg0) != Arg1) && Local0--) { Stall (10) } If (Local0) { @@ -66,8 +66,8 @@ */ Method (SEND_EC_COMMAND, 1) { - Store (WAIT_EC_SC (EC_IBF, 0), Local0) - If (LNot (Local0)) { + Local0 = WAIT_EC_SC (EC_IBF, 0) + If (!Local0) { Store (Arg0, EC_SC) } Return (Local0) @@ -83,9 +83,9 @@ */ Method (SEND_EC_DATA, 1) { - Store (WAIT_EC_SC (EC_IBF, 0), Local0) - If (LNot (Local0)) { - Store (Arg0, EC_DATA) + Local0 = WAIT_EC_SC (EC_IBF, 0) + If (!Local0) { + EC_DATA = Arg0 } Return (Local0) } @@ -100,8 +100,8 @@ */ Method (RECV_EC_DATA) { - Store (WAIT_EC_SC (EC_OBF, EC_OBF), Local0) - If (LNot (Local0)) { + Local0 = WAIT_EC_SC (EC_OBF, EC_OBF) + If (!Local0) { Return (EC_DATA) } Else { Return (Local0) @@ -117,12 +117,12 @@ Method (EC_READ, 1) { Acquire (EC_MUTEX, 0xffff) - Store (SEND_EC_COMMAND (EC_READ_CMD), Local0) - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg0), Local0) + Local0 = SEND_EC_COMMAND (EC_READ_CMD) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg0) } - If (LNot (Local0)) { - Store (RECV_EC_DATA (), Local0) + If (!Local0) { + Local0 = RECV_EC_DATA () } Release (EC_MUTEX) @@ -139,12 +139,12 @@ Method (EC_WRITE, 2) { Acquire (EC_MUTEX, 0xffff) - Store (SEND_EC_COMMAND (EC_WRITE_CMD), Local0) - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg0), Local0) + Local0 = SEND_EC_COMMAND (EC_WRITE_CMD) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg0) } - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg1), Local0) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg1) } Release (EC_MUTEX) -- To view, visit https://review.coreboot.org/c/coreboot/+/46095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348 Gerrit-Change-Number: 46095 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/razer: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46085 ) Change subject: mb/razer: Convert to ASL 2.0 syntax ...................................................................... mb/razer: Convert to ASL 2.0 syntax Change-Id: I9c7cbc4ee874657a7381b1b220872c4ebecd0821 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl M src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl 2 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46085/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl index 241d090..8f19555 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl @@ -40,21 +40,21 @@ Method (_BIF, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BFCP, Index (PBIF, 2)) + PBIF [2] = BFCP /* Design Voltage */ - Store (BDVT, Index (PBIF, 4)) + PBIF [4] = BDVT /* Design Capacity */ - Store (BDCP, Index (PBIF, 1)) + PBIF [1] = BDCP /* Design Capacity of Warning */ - Store (BDCP / 0x32, Index (PBIF, 5)) + PBIF [5] = BDCP / 50 /* Design Capacity of Low */ - Store (BDCP / 0x64, Index (PBIF, 6)) + PBIF [6] = BDCP / 100 - Store (ToString (BSER, Ones), Index (PBIF, 0x0A)) + PBIF [10] = ToString (BSER, Ones) Return (PBIF) } @@ -72,34 +72,34 @@ /* Check if AC is present */ If (ACEX) { /* Read battery status from EC */ - Store (BCST, Local0) + Local0 = BCST } Else { /* Always discharging when on battery power */ - Store (0x01, Local0) + Local0 = 0x01 } - Store (Local0, Index (PBST, 0)) + PBST [0] = Local0 /* Notify if battery state has changed since last time */ - If (LNotEqual (Local0, BSTP)) { - Store (Local0, BSTP) + If (Local0 != BSTP) { + BSTP = Local0 Notify (BAT, 0x80) } /* * 1: BATTERY PRESENT RATE */ - Store (BCRT, Index (PBST, 1)) + PBST [1] = BCRT /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRCP, Index (PBST, 2)) + PBST [2] = BRCP /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BCVT, Index (PBST, 3)) + PBST [3] = BCVT Return (PBST) } diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 5698dcb..72eaca4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -56,24 +56,24 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (PWRS - 0x82, ACEX) + ACEX = PWRS - 0x82 /* Initialize LID switch state */ - Store (LIDS, \LIDS) + \LIDS = LIDS } // Close ? Method (_Q14, 0, NotSerialized) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } //Open Method (_Q15, 0, NotSerialized) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } @@ -81,7 +81,7 @@ // AC plugged Method (_Q13, 0, NotSerialized) { - Store (PWRS - 0x82, ACEX) + ACEX = PWRS - 0x82 Notify (BAT, 0x80) // Status Change Notify (BAT, 0x81) // Information Change Notify (AC, 0x80) // Status Change -- To view, visit https://review.coreboot.org/c/coreboot/+/46085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c7cbc4ee874657a7381b1b220872c4ebecd0821 Gerrit-Change-Number: 46085 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/packardbell: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46084 ) Change subject: mb/packardbell: Convert to ASL 2.0 syntax ...................................................................... mb/packardbell: Convert to ASL 2.0 syntax Change-Id: I5f1dbb2595c3ee8cb35bb8a6431288f4a96ce978 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/thermal.asl 2 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46084/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 297eeb4..9ec8e6e 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -46,47 +46,47 @@ */ /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) + OSYS = 2000 If (CondRefOf(_OSI)) { If (_OSI("Windows 2001")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + OSYS = 2002 } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2006")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + OSYS = 2009 } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + OSYS = 2012 } } } diff --git a/src/mainboard/packardbell/ms2290/acpi/thermal.asl b/src/mainboard/packardbell/ms2290/acpi/thermal.asl index 8d24127..913df61 100644 --- a/src/mainboard/packardbell/ms2290/acpi/thermal.asl +++ b/src/mainboard/packardbell/ms2290/acpi/thermal.asl @@ -6,13 +6,13 @@ Method(C2K, 1, NotSerialized) { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { + Local0 = Arg0 * 10 + Local0 += 2732 + if (Local0 <= 2732) { Return (3000) } - if (LGreater(Local0, 4012)) { + if (Local0 > 4012) { Return (3000) } Return (Local0) @@ -25,10 +25,10 @@ } Method(_TMP) { /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + If (!MEBT & (\_SB.PCI0.LPCB.EC.TMP0 == 128)) { Return (C2K(40)) } - Store (1, MEBT) + MEBT = 1 Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f1dbb2595c3ee8cb35bb8a6431288f4a96ce978 Gerrit-Change-Number: 46084 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lippert: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46083 ) Change subject: mb/lippert: Convert to ASL 2.0 syntax ...................................................................... mb/lippert: Convert to ASL 2.0 syntax Change-Id: I61d8af98e2003547e332f463b23c1e1cf79f7f00 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lippert/frontrunner-af/acpi/usb.asl 1 file changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46083/1 diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index ca9e002..59f7d92 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -2,134 +2,134 @@ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61d8af98e2003547e332f463b23c1e1cf79f7f00 Gerrit-Change-Number: 46083 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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