coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/broadwell/chip.h: Drop unused fields
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46995 ) Change subject: soc/intel/broadwell/chip.h: Drop unused fields ...................................................................... soc/intel/broadwell/chip.h: Drop unused fields Broadwell boards now use the CPU code for Haswell. Therefore, these devicetree options are no longer used anywhere and can be removed. Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/chip.h 1 file changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46995/1 diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 81c9780..6540273 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -42,34 +42,6 @@ int cdclk; struct i915_gpu_controller_info gfx; - - /* - * Minimum voltage for C6/C7 state: - * 0x67 = 1.6V (full swing) - * ... - * 0x79 = 1.7V - * ... - * 0x83 = 1.8V (no swing) - */ - int vr_cpu_min_vid; - - /* - * Set slow VR ramp rate on C-state exit: - * 0 = Fast VR ramp rate / 2 - * 1 = Fast VR ramp rate / 4 - * 2 = Fast VR ramp rate / 8 - * 3 = Fast VR ramp rate / 16 - */ - int vr_slow_ramp_rate_set; - - /* Enable slow VR ramp rate */ - int vr_slow_ramp_rate_enable; - - /* Enable S0iX support */ - int s0ix_enable; - - /* TCC activation offset */ - uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/46995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Gerrit-Change-Number: 46995 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/broadwell: Select CPU_INTEL_HASWELL
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46953 ) Change subject: soc/intel/broadwell: Select CPU_INTEL_HASWELL ...................................................................... soc/intel/broadwell: Select CPU_INTEL_HASWELL This allows us to drop many now-redundant Kconfig options. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. The default configuration file also remains identical, as expected. Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/purism/librem_bdw/Kconfig M src/soc/intel/broadwell/Kconfig 5 files changed, 1 insertion(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46953/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 9c705e1..5301e32 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC @@ -59,10 +58,6 @@ default "samus" if BOARD_GOOGLE_SAMUS default "" -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7d6ff8d..e65b21f 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F @@ -40,10 +39,6 @@ default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index bb0fdf4..7ac5f1c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES @@ -26,11 +25,6 @@ string default "WHITETIP MOUNTAIN 2" - -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0166.rom" diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 173874c..ad764b7 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -1,6 +1,5 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW def_bool n - select CPU_INTEL_HASWELL select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_RESUME @@ -53,10 +52,6 @@ default "1.0" if BOARD_PURISM_LIBREM13_V1 default "2.0" if BOARD_PURISM_LIBREM15_V2 -config MAX_CPUS - int - default 8 - config PRE_GRAPHICS_DELAY int default 50 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5eebe59..22173d2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,14 +8,10 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_HASWELL select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -26,13 +22,8 @@ select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT - select PARALLEL_MP select RTC select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT @@ -84,18 +75,6 @@ hex default 0xf0000000 -config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406" -- To view, visit https://review.coreboot.org/c/coreboot/+/46953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Gerrit-Change-Number: 46953 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/broadwell: Move romstage.c to Haswell
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46951 ) Change subject: soc/intel/broadwell: Move romstage.c to Haswell ...................................................................... soc/intel/broadwell: Move romstage.c to Haswell Broadwell no longer has CPU code. Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc R src/cpu/intel/haswell/romstage.c M src/soc/intel/broadwell/Makefile.inc 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46951/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 3c4db4f..bfb5011 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,4 +1,6 @@ ramstage-y += haswell_init.c + +romstage-y += romstage.c romstage-y += ../car/romstage.c ramstage-y += acpi.c diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/cpu/intel/haswell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/cpu/romstage.c rename to src/cpu/intel/haswell/romstage.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7f42b1d..3f06913 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -2,8 +2,6 @@ subdirs-y += pch -romstage-y += cpu/romstage.c - bootblock-y += bootblock.c romstage-y += early_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Gerrit-Change-Number: 46951 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: broadwell: Drop now-unused CPU code
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46950 ) Change subject: broadwell: Drop now-unused CPU code ...................................................................... broadwell: Drop now-unused CPU code All boards now use Haswell's CPU code, which also supports Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ia0b8f7bf64334dd965baad0a30a7bb0ed81c4cac Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/cpu/Makefile.inc D src/soc/intel/broadwell/cpu/acpi.c D src/soc/intel/broadwell/cpu/bootblock.c D src/soc/intel/broadwell/cpu/cpu.c D src/soc/intel/broadwell/cpu/haswell.h D src/soc/intel/broadwell/cpu/smmrelocate.c D src/soc/intel/broadwell/cpu/tsc_freq.c 8 files changed, 2 insertions(+), 1,544 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46950/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ac5eeb6..7f42b1d 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,13 +1,9 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -ifeq ($(CONFIG_CPU_INTEL_HASWELL),y) -romstage-y += cpu/romstage.c -else -subdirs-y += cpu -endif - subdirs-y += pch +romstage-y += cpu/romstage.c + bootblock-y += bootblock.c romstage-y += early_init.c diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc deleted file mode 100644 index 803696a..0000000 --- a/src/soc/intel/broadwell/cpu/Makefile.inc +++ /dev/null @@ -1,30 +0,0 @@ -subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/mtrr -subdirs-y += ../../../../cpu/x86/smm -subdirs-y += ../../../../cpu/x86/tsc -subdirs-y += ../../../../cpu/intel/microcode -subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/intel/common - -bootblock-y += bootblock.c -bootblock-y += ../../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../../cpu/x86/early_reset.S - -romstage-y += romstage.c -romstage-y += ../../../../cpu/intel/car/romstage.c - -postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S - -ramstage-y += acpi.c -ramstage-y += cpu.c -ramstage-y += smmrelocate.c - -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c - -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c deleted file mode 100644 index 56a4e99..0000000 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ /dev/null @@ -1,392 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> -#include <acpi/acpigen.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cbmem.h> -#include <device/pci_ops.h> -#include <cpu/x86/smm.h> -#include <console/console.h> -#include <types.h> -#include <string.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> -#include <soc/intel/broadwell/chip.h> - -#include <soc/intel/broadwell/haswell.h> -#include "haswell.h" - -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_s0ix[3] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -static int cstate_set_non_s0ix[3] = { - C_STATE_C1E, - C_STATE_C3, - C_STATE_C7S_LONG_LAT -}; - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} diff --git a/src/soc/intel/broadwell/cpu/bootblock.c b/src/soc/intel/broadwell/cpu/bootblock.c deleted file mode 100644 index c774664..0000000 --- a/src/soc/intel/broadwell/cpu/bootblock.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/bootblock.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <halt.h> -#include <delay.h> - -#include "haswell.h" -#include "../pch/rcba.h" - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - -void bootblock_early_cpu_init(void) -{ - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); -} diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c deleted file mode 100644 index 10db364..0000000 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ /dev/null @@ -1,638 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/cpu.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/intel/microcode.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/speedstep.h> -#include <cpu/intel/turbo.h> -#include <cpu/x86/name.h> -#include <delay.h> -#include <cpu/intel/common/common.h> - -#include <soc/intel/broadwell/chip.h> -#include <soc/intel/broadwell/haswell.h> -#include "../pch/rcba.h" -#include "haswell.h" - -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10; - - wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); - - return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} - -static int pcode_mailbox_write(u32 command, u32 data) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return -1; - } - - MCHBAR32(BIOS_MAILBOX_DATA) = data; - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return -1; - } - - return 0; -} - -static void initialize_vr_config(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - printk(BIOS_DEBUG, "Initializing VR config.\n"); - - /* Configure VR_CURRENT_CONFIG. */ - msr = rdmsr(MSR_VR_CURRENT_CONFIG); - /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid - * on ULT systems. */ - msr.hi &= 0xc0000000; - msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ - msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ - msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ - /* Leave the max instantaneous current limit (12:0) to default. */ - wrmsr(MSR_VR_CURRENT_CONFIG, msr); - - /* Configure VR_MISC_CONFIG MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG); - /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ - msr.hi &= ~(0x3ff << (40 - 32)); - msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ - /* Set IOUT_OFFSET to 0. */ - msr.hi &= ~0xff; - /* Set entry ramp rate to slow. */ - msr.hi &= ~(1 << (51 - 32)); - /* Enable decay mode on C-state entry. */ - msr.hi |= (1 << (52 - 32)); - /* Set the slow ramp rate */ - msr.hi &= ~(0x3 << (53 - 32)); - /* Configure the C-state exit ramp rate. */ - if (conf->vr_slow_ramp_rate_enable) { - /* Configured slow ramp rate. */ - msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32)); - /* Set exit ramp rate to slow. */ - msr.hi &= ~(1 << (50 - 32)); - } else { - /* Fast ramp rate / 4. */ - msr.hi |= (0x01 << (53 - 32)); - /* Set exit ramp rate to fast. */ - msr.hi |= (1 << (50 - 32)); - } - /* Set MIN_VID (31:24) to allow CPU to have full control. */ - msr.lo &= ~0xff000000; - msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24; - wrmsr(MSR_VR_MISC_CONFIG, msr); - - /* Configure VR_MISC_CONFIG2 MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage in 10mV steps. */ - if (cpu_family_model() == BROADWELL_FAMILY_ULT) - msr.lo |= 0x006a; /* 1.56V */ - else - msr.lo |= 0x006f; /* 1.60V */ - wrmsr(MSR_VR_MISC_CONFIG2, msr); - - /* Set C9/C10 VCC Min */ - pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); -} - -static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} - -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on server SKU */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - -static void configure_c_states(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 31); // Timed MWAIT Enable - msr.lo |= (1 << 30); // Package c-state Undemotion Enable - msr.lo |= (1 << 29); // Package c-state Demotion Enable - msr.lo |= (1 << 28); // C1 Auto Undemotion Enable - msr.lo |= (1 << 27); // C3 Auto Undemotion Enable - msr.lo |= (1 << 26); // C1 Auto Demotion Enable - msr.lo |= (1 << 25); // C3 Auto Demotion Enable - msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination - wrmsr(MSR_MISC_PWR_MGMT, msr); - - msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 - msr.lo |= (1 << 1); // C1E Enable - msr.lo |= (1 << 0); // Bi-directional PROCHOT# - wrmsr(MSR_POWER_CTL, msr); - - /* C-state Interrupt Response Latency Control 0 - package C3 latency */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); - - /* C-state Interrupt Response Latency Control 1 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - -static void configure_thermal_target(void) -{ - config_t *conf; - struct device *lapic; - msr_t msr; - - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } -} - -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void set_max_ratio(void) -{ - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} - -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - -/* All CPUs including BSP will run the following function. */ -static void cpu_core_init(struct device *cpu) -{ - /* Clear out pending MCEs */ - configure_mca(); - - /* Enable the local CPU APICs */ - enable_lapic_tpr(); - setup_lapic(); - - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - - /* Configure C States */ - configure_c_states(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - /* Thermal throttle activation offset */ - configure_thermal_target(); - - /* Enable Direct Cache Access */ - configure_dca_cap(); - - /* Set energy policy */ - set_energy_perf_bias(ENERGY_POLICY_NORMAL); - - /* Enable Turbo */ - enable_turbo(); -} - -/* MP initialization support. */ -static const void *microcode_patch; - -static void pre_mp_init(void) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - - initialize_vr_config(); - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); -} - -static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - set_max_ratio(); - - /* Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. */ - global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, -}; - -void mp_init_cpus(struct bus *cpu_bus) -{ - if (mp_init_with_smm(cpu_bus, &mp_ops)) - printk(BIOS_ERR, "MP initialization failure.\n"); -} - -static struct device_operations cpu_dev_ops = { - .init = cpu_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, CPUID_HASWELL_ULT }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_D0 }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_E0 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/soc/intel/broadwell/cpu/haswell.h b/src/soc/intel/broadwell/cpu/haswell.h deleted file mode 100644 index 26077a7..0000000 --- a/src/soc/intel/broadwell/cpu/haswell.h +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CPU_BROADWELL_H_ -#define _CPU_BROADWELL_H_ - -#include <arch/cpu.h> -#include <stdint.h> - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_POWER_CTL 0x1fc -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* Long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - -#define MSR_VR_CURRENT_CONFIG 0x601 -#define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 -#define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - -void set_max_freq(void); - -/* CPU identification */ -static inline u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -static inline u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -#endif diff --git a/src/soc/intel/broadwell/cpu/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c deleted file mode 100644 index 5628403..0000000 --- a/src/soc/intel/broadwell/cpu/smmrelocate.c +++ /dev/null @@ -1,263 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <smp/node.h> - -#include <soc/intel/broadwell/haswell.h> -#include "haswell.h" - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/broadwell/cpu/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c deleted file mode 100644 index fab1909..0000000 --- a/src/soc/intel/broadwell/cpu/tsc_freq.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "haswell.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b8f7bf64334dd965baad0a30a7bb0ed81c4cac Gerrit-Change-Number: 46950 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/broadwell: Use Haswell CPU headers
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46949 ) Change subject: soc/intel/broadwell: Use Haswell CPU headers ...................................................................... soc/intel/broadwell: Use Haswell CPU headers Now that the boards use Haswell's CPU code, Broadwell can be updated. Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 8 files changed, 25 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 09cab17..481a593 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -168,12 +168,19 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +void set_max_freq(void); + /* CPU identification */ static inline u32 cpu_family_model(void) { return cpuid_eax(1) & 0x0fff0ff0; } +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP) || CONFIG(SOC_INTEL_BROADWELL); diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c index 959a123..f4b913f 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/soc/intel/broadwell/cpu/romstage.c @@ -3,8 +3,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/intel/broadwell/romstage.h> -#include "haswell.h" +#include <cpu/intel/haswell/haswell.h> void set_max_freq(void) { diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index a448237..8370167 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <bootmode.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -20,7 +21,6 @@ #include <security/vboot/vbnv.h> #include <types.h> -#include "cpu/haswell.h" #include "haswell.h" #define GT_RETRY 1000 @@ -524,7 +524,7 @@ reg_script_run_on_dev(dev, broadwell_early_init_script); /* Set GFXPAUSE based on stepping */ - if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && + if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) && systemagent_revision() <= 9) { gtt_write(0xa000, 0x300ff); } else { diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 73c6e83..33293a4 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -10,8 +10,8 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/intel/broadwell/memmap.h> +#include <cpu/intel/haswell/haswell.h> -#include "cpu/haswell.h" #include "haswell.h" #include "ramstage.h" diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index f43fa78..8bf7d3d 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -11,7 +11,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <delay.h> -#include "../cpu/haswell.h" +#include <cpu/intel/haswell/haswell.h> #include "gpio.h" #include "iobp.h" #include "pch.h" diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index 50c69d2..5679ff3 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -8,8 +8,8 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/cpu.h> +#include <cpu/intel/haswell/haswell.h> -#include "../cpu/haswell.h" #include "xhci.h" #ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index b649ebb..ad5a109 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -7,25 +7,26 @@ #include <string.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> +#include <cpu/intel/haswell/haswell.h> #include <soc/intel/broadwell/romstage.h> #include <soc/intel/broadwell/haswell.h> -#include "cpu/haswell.h" #include "pch/pch.h" +/* FIXME: Needs an update */ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_HASWELL_A0, "Haswell A0" }, - { CPUID_HASWELL_B0, "Haswell B0" }, - { CPUID_HASWELL_C0, "Haswell C0" }, - { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, - { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, - { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, - { CPUID_BROADWELL_C0, "Broadwell C0" }, - { CPUID_BROADWELL_D0, "Broadwell D0" }, - { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, + { CPUID_HASWELL_A0, "Haswell A0" }, + { CPUID_HASWELL_B0, "Haswell B0" }, + { CPUID_HASWELL_C0, "Haswell C0" }, + { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, + { CPUID_HASWELL_ULT_C0, "Haswell ULT C0 or D0" }, + { CPUID_CRYSTALWELL_C0, "Haswell Perf Halo" }, + { CPUID_BROADWELL_ULT_C0, "Broadwell C0" }, + { CPUID_BROADWELL_ULT_D0, "Broadwell D0" }, + { CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" }, }; static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 165d649..f9242fd 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/romstage.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <elog.h> #include <romstage_handoff.h> #include <soc/intel/broadwell/pch/pm.h> @@ -10,7 +11,6 @@ #include <stdint.h> #include <timestamp.h> -#include "cpu/haswell.h" #include "haswell.h" #include "pei_data.h" #include "pch/gpio.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/46949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Gerrit-Change-Number: 46949 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/google/auron: Use Haswell CPU code
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46945 ) Change subject: mb/google/auron: Use Haswell CPU code ...................................................................... mb/google/auron: Use Haswell CPU code The VR config and S0ix options are now specified for the CPU chip. Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 4 files changed, 28 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46945/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 8e49255..9c705e1 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 26a5336..6aa9582 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,10 +15,13 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - register "s0ix_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + register "s0ix_enable" = "1" + + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 60fb08c..1fd9e86 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,7 +7,14 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "s0ix_enable" = "0" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index d8aec0a..d7bc611 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,11 +10,20 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0" - # Disable S0ix for now - register "s0ix_enable" = "0" + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch -- To view, visit https://review.coreboot.org/c/coreboot/+/46945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Gerrit-Change-Number: 46945 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/google/jecht: Use Haswell CPU code
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46946 ) Change subject: mb/google/jecht: Use Haswell CPU code ...................................................................... mb/google/jecht: Use Haswell CPU code Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/jecht/Kconfig M src/mainboard/google/jecht/devicetree.cb 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46946/1 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 4851bd7..7d6ff8d 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,5 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 94fd804..08b2c95 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -10,7 +10,10 @@ register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/46946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475 Gerrit-Change-Number: 46946 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/intel/wtm2: Use Haswell CPU code
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46947 ) Change subject: mb/intel/wtm2: Use Haswell CPU code ...................................................................... mb/intel/wtm2: Use Haswell CPU code Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/wtm2/Kconfig M src/mainboard/intel/wtm2/devicetree.cb 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46947/1 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 2f6b21e..61d7657 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,6 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 29041aa..9090999 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -10,7 +10,10 @@ register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on device pci 00.0 on end # host bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/46947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff Gerrit-Change-Number: 46947 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/purism/librem_bdw: Use Haswell CPU code
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46948 ) Change subject: mb/purism/librem_bdw: Use Haswell CPU code ...................................................................... mb/purism/librem_bdw: Use Haswell CPU code Change-Id: I736bff90305952d279a10dfe90a2ee3a533220b5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_bdw/Kconfig M src/mainboard/purism/librem_bdw/devicetree.cb 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46948/1 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 275594b..173874c 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -1,5 +1,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW def_bool n + select CPU_INTEL_HASWELL select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_RESUME diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0d0fc72..0575a98 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -17,7 +17,10 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on device pci 00.0 on end # host bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/46948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I736bff90305952d279a10dfe90a2ee3a533220b5 Gerrit-Change-Number: 46948 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: broadwell: Allow to use Haswell CPU code instead
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46944 ) Change subject: broadwell: Allow to use Haswell CPU code instead ...................................................................... broadwell: Allow to use Haswell CPU code instead This allows individual boards to be adapted to use Haswell CPU code. Also rename the CPU_SPECIFIC_OPTIONS symbol to avoid any collisions. Tested on out-of-tree Acer Aspire E5-573 with i5-5200U, still boots. Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc 3 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46944/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e45acd5..09cab17 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -176,7 +176,7 @@ static inline int haswell_is_ult(void) { - return CONFIG(INTEL_LYNXPOINT_LP); + return CONFIG(INTEL_LYNXPOINT_LP) || CONFIG(SOC_INTEL_BROADWELL); } #endif diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index ecb8299..5eebe59 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,7 +5,7 @@ if SOC_INTEL_BROADWELL -config CPU_SPECIFIC_OPTIONS +config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index cda69e8..ac5eeb6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,11 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_CPU_INTEL_HASWELL),y) +romstage-y += cpu/romstage.c +else subdirs-y += cpu +endif + subdirs-y += pch bootblock-y += bootblock.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588 Gerrit-Change-Number: 46944 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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