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Change in coreboot[master]: mb/lenovo/x60: Convert *.asl to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46011 ) Change subject: mb/lenovo/x60: Convert *.asl to ASL 2.0 syntax ...................................................................... mb/lenovo/x60: Convert *.asl to ASL 2.0 syntax Change-Id: I305561625d973093645236c77ef13a96ab780f94 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x60/acpi/dock.asl M src/mainboard/lenovo/x60/acpi/gpe.asl M src/mainboard/lenovo/x60/acpi/platform.asl 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46011/1 diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index 26f555f..5fd6978 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -27,7 +27,7 @@ TRAP(SMI_DOCK_DISCONNECT) } - Xor(Arg0, DSTA, Local0) + Local0 = Arg0 ^ DSTA Return (Local0) } diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 62e7b37..9984636 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -5,8 +5,8 @@ Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index c9551b5..ca52e5d 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -24,12 +24,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -60,7 +60,7 @@ * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } -- To view, visit https://review.coreboot.org/c/coreboot/+/46011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I305561625d973093645236c77ef13a96ab780f94 Gerrit-Change-Number: 46011 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/lenovo/x220: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46205 ) Change subject: mb/lenovo/x220: Convert to ASL 2.0 syntax ...................................................................... mb/lenovo/x220: Convert to ASL 2.0 syntax Change-Id: I4c5c67d70e004eeece61e66d427d6f9df9cab4ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x220/acpi/platform.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46205/1 diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 40b9a53..c4becaf 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c5c67d70e004eeece61e66d427d6f9df9cab4ec Gerrit-Change-Number: 46205 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/x201: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46204 ) Change subject: mb/lenovo/x201: Convert to ASL 2.0 syntax ...................................................................... mb/lenovo/x201: Convert to ASL 2.0 syntax Change-Id: I3b553e1b68ee8f236fcab311a076001b94a47975 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x201/acpi/dock.asl M src/mainboard/lenovo/x201/acpi/gpe.asl M src/mainboard/lenovo/x201/acpi/platform.asl 3 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46204/1 diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index 0bf5a25..311e620 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -12,18 +12,18 @@ { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 + \_SB.PCI0.LPCB.EC.DKR2 = 1 + \_SB.PCI0.LPCB.EC.DKR3 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 + \_SB.PCI0.LPCB.EC.DKR2 = 0 + \_SB.PCI0.LPCB.EC.DKR3 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 62e7b37..9984636 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -5,8 +5,8 @@ Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index b03f45f..44b06c6 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) @@ -56,47 +56,47 @@ */ /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) + OSYS = 2000 If (CondRefOf(_OSI)) { If (_OSI("Windows 2001")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + OSYS = 2002 } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2006")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + OSYS = 2009 } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + OSYS = 2012 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b553e1b68ee8f236fcab311a076001b94a47975 Gerrit-Change-Number: 46204 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/lenovo/x200: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46203 ) Change subject: mb/lenovo/x200: Convert to ASL 2.0 syntax ...................................................................... mb/lenovo/x200: Convert to ASL 2.0 syntax Change-Id: I0767afcb0ffdd6f9a8d83209955d42d9e89325e9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x200/acpi/dock.asl M src/mainboard/lenovo/x200/acpi/gpe.asl M src/mainboard/lenovo/x200/acpi/platform.asl 3 files changed, 23 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46203/1 diff --git a/src/mainboard/lenovo/x200/acpi/dock.asl b/src/mainboard/lenovo/x200/acpi/dock.asl index b612f06..ba8f46e 100644 --- a/src/mainboard/lenovo/x200/acpi/dock.asl +++ b/src/mainboard/lenovo/x200/acpi/dock.asl @@ -12,14 +12,14 @@ { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } @@ -32,16 +32,15 @@ /* Returns 0x7 (dock absent) or 0x3 (dock present) */ Method(GGID, 0, NotSerialized) { - Store(G_ID, Local0) - if (LEqual(Local0, 0xFFFFFFFF)) + Local0 = G_ID + if (Local0 == 0xFFFFFFFF) { - Store(Or (Or (GP02, ShiftLeft(GP03, 1)), - ShiftLeft(GP04, 2)), Local0) - If (LEqual(Local0, 0x00)) + Local0 = GP02 | (GP03 << 1) | (GP04 << 2) + If (Local0 == 0x00) { - Store(0x03, Local0) + Local0 = 0x03 } - Store(Local0, G_ID) + G_ID = Local0 } return (Local0) } @@ -68,8 +67,8 @@ /* Undock button on dock */ Method(_Q50, 0, NotSerialized) { - Store(\_SB.DOCK.GGID (), Local0) - if (LNotEqual(Local0, 0x07)) + Local0 = \_SB.DOCK.GGID () + if (Local0 != 0x07) { Notify(\_SB.DOCK, 3) } @@ -83,16 +82,16 @@ /* Unplug power: only disconnect dock on force eject */ Method(_Q5A, 0, NotSerialized) { - Store(\_SB.DOCK.GGID (), Local0) - if (LEqual(Local0, 0x07)) + Local0 = \_SB.DOCK.GGID () + if (Local0 == 0x07) { Notify(\_SB.DOCK, 3) } - if (LEqual(Local0, 0x03)) + if (Local0 == 0x03) { Sleep(0x64) - Store(DKR1, Local1) - if (LEqual(Local1, 1)) + Local1 = DKR1 + if (Local1 == 1) { Notify(\_SB.DOCK, 0) } diff --git a/src/mainboard/lenovo/x200/acpi/gpe.asl b/src/mainboard/lenovo/x200/acpi/gpe.asl index 62e7b37..9984636 100644 --- a/src/mainboard/lenovo/x200/acpi/gpe.asl +++ b/src/mainboard/lenovo/x200/acpi/gpe.asl @@ -5,8 +5,8 @@ Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 10cadf2..95e594c 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -26,12 +26,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -65,7 +65,7 @@ * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } -- To view, visit https://review.coreboot.org/c/coreboot/+/46203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0767afcb0ffdd6f9a8d83209955d42d9e89325e9 Gerrit-Change-Number: 46203 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/biostar/am1ml: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46161 ) Change subject: mb/biostar/am1ml: Convert to ASL 2.0 syntax ...................................................................... mb/biostar/am1ml: Convert to ASL 2.0 syntax Change-Id: Ifdd5008bcb9c7e41e637a30f70316c7926f927b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/am1ml/acpi/ide.asl M src/mainboard/biostar/am1ml/acpi/sata.asl M src/mainboard/biostar/am1ml/acpi/sio.asl M src/mainboard/biostar/am1ml/acpi/sleep.asl M src/mainboard/biostar/am1ml/acpi/superio.asl 5 files changed, 94 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46161/1 diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 56f760d..766fcb3 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -52,11 +52,11 @@ Method(GTTM, 1) /* get total time*/ { - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) + Local0 = Arg0 & 0x0F /* Recovery Width */ + Local0++ + Local1 = Arg0 >> 4 /* Command Width */ + Local1++ + Return(30 * (Local0 + Local1)) } Device(PRID) @@ -78,32 +78,32 @@ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ + If (PPCR & 0x01) { /* primary PIO control */ Return(OTBF) } /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) + BFFG |= 0x1A /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) + PSD0 = GTTM (PPTM) /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) + PSD1 = GTTM (PPTS) - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) + If (PDCR & 0x01) { /* It's under UDMA mode */ + BFFG |= 0x01 + DSD0 = DerefOf(UDTT [PDMM]) } Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing, DmaSpd0 */ } - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) + If (PDCR & 0x02) { /* It's under UDMA mode */ + BFFG |= 0x04 + DSD1 = DerefOf(UDTT [PDSM]) } Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing, DmaSpd0 */ } Return(OTBF) /* out buffer */ @@ -124,35 +124,35 @@ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0) + PPMM = Local0 % 5 /* Primary PIO master Mode */ + Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0) + PPSM = Local1 % 5 /* Primary PIO slave Mode */ - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */ + PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */ - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) + If (BFFG & 0x01) { /* Drive 0 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0) + PDMM = Local0 % 7 + PDCR |= 0x01 } Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) + If (DSD0 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0) + PMTM = DerefOf(MDRT [Local0]) } } - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) + If (BFFG & 0x04) { /* Drive 1 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0) + PDSM = Local0 % 7 + PDCR |= 0x02 } Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) + If (DSD1 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0) + PMTS = DerefOf(MDRT [Local0]) } } /* Return(INBF) */ @@ -172,21 +172,19 @@ CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) + CMDA = 0xA0 + CMDB = 0xA0 + CMDC = 0xA0 - Or(PPMM, 0x08, POMD) + POMD = PPMM | 0x08 - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) + If (PDCR & 0x01) { + DMMD = PDMM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) @@ -208,21 +206,19 @@ CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) + CMDA = 0xB0 + CMDB = 0xB0 + CMDC = 0xB0 - Or(PPSM, 0x08, POMD) + POMD = PPSM | 0x08 - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) + If (PDCR & 0x02) { + DMMD = PDSM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index d1a4ee7..31b9374 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -33,7 +33,7 @@ Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -46,7 +46,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -68,7 +68,7 @@ { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -81,7 +81,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -95,35 +95,35 @@ Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl index ef0bca5..bf4ff3d 100644 --- a/src/mainboard/biostar/am1ml/acpi/sio.asl +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -26,17 +26,17 @@ /* Enter the 8728 Config */ Method (EPNP) { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) + SIOI = 0x87 + SIOI = 0x01 + SIOI = 0x55 + SIOI = 0x55 } /* Exit the 8728 Config */ Method (XPNP) { - Store (0x02, SIOI) - Store (0x02, SIOD) + SIOI = 0x02 + SIOD = 0x02 } /* @@ -46,20 +46,20 @@ Method (SIOS, 1) { /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) + If (Arg0 < 0x05) { EPNP() /* DBGO("8728F\n") */ - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ + LDN = 0x4 + ACTR = 1 /* Enable EC */ /* - Store (0x4, LDN) - Store (0x04, APC4) + LDN = 0x4 + APC4 = 0x04 */ /* falling edge. which mode? Not sure. */ - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC1 = 0x08 /* clear PME status, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC0 = 0x08 /* enable PME, Use 0x18 for mouse & KBD */ XPNP() } } diff --git a/src/mainboard/biostar/am1ml/acpi/sleep.asl b/src/mainboard/biostar/am1ml/acpi/sleep.asl index 47dd146..fc26c30 100644 --- a/src/mainboard/biostar/am1ml/acpi/sleep.asl +++ b/src/mainboard/biostar/am1ml/acpi/sleep.asl @@ -30,9 +30,9 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) diff --git a/src/mainboard/biostar/am1ml/acpi/superio.asl b/src/mainboard/biostar/am1ml/acpi/superio.asl index a4eda2b..03683b3 100644 --- a/src/mainboard/biostar/am1ml/acpi/superio.asl +++ b/src/mainboard/biostar/am1ml/acpi/superio.asl @@ -12,8 +12,8 @@ IRQNoFlags () {12} }) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -24,8 +24,8 @@ Device (PS2K) { Name (_HID, EisaId ("PNP0303")) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -42,8 +42,8 @@ Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -65,8 +65,8 @@ Name (_HID, EISAID ("PNP0400")) Name (_UID, 1) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) -- To view, visit https://review.coreboot.org/c/coreboot/+/46161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdd5008bcb9c7e41e637a30f70316c7926f927b5 Gerrit-Change-Number: 46161 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/lenovo/t400: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46192 ) Change subject: mb/lenovo/t400: Convert to ASL 2.0 syntax ...................................................................... mb/lenovo/t400: Convert to ASL 2.0 syntax Change-Id: I4e6d5048ca9e949a70f3619f05b74870c1f1fe30 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/t400/acpi/dock.asl M src/mainboard/lenovo/t400/acpi/gpe.asl M src/mainboard/lenovo/t400/acpi/graphics.asl 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46192/1 diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index 9a6d354..dce1d1a 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -12,14 +12,14 @@ { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl index 62e7b37..9984636 100644 --- a/src/mainboard/lenovo/t400/acpi/gpe.asl +++ b/src/mainboard/lenovo/t400/acpi/gpe.asl @@ -5,8 +5,8 @@ Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 8780e2f..5559bfc 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -26,19 +26,19 @@ Method(SHYB, 1) { /* Switch hybrid graphics */ - if (LEqual(Arg0, One)) + if (Arg0 == One) { /* Discrete graphics requested */ - Or(GPLV, HYG1, GPLV) - Or(GQLV, HYG2, GQLV) + GPLV |= HYG1 + GQLV |= HYG2 } else { /* Integrated graphics requested */ - Xor(HYG1, 0xFFFFFFFF, Local0) - And(GPLV, Local0, GPLV) - Xor(HYG2, 0xFFFFFFFF, Local0) - And(GQLV, Local0, GQLV) + Local0 = HYG1 ^ 0xFFFFFFFF + GPLV &= Local0 + Local0 = HYG2 ^ 0xFFFFFFFF + GQLV &= Local0 } } @@ -53,21 +53,21 @@ CreateDWordField (ATPR, 0x04, FUNC) /* Version request */ - if (LEqual(Arg0, 0x0)) + if (Arg0 == 0x0) { /* Assemble and return version information */ - Store (0x08, SIZE) /* Response length */ - Store (0x01, VERS) /* Version number */ - Store (0x0F, FUNC) /* Supported functions? */ + SIZE = 0x08 /* Response length */ + VERS = 0x01 /* Version number */ + FUNC = 0x0F /* Supported functions? */ Return (ATPR) } /* Mux select */ - if (LEqual(Arg0, 0x2)) + if (Arg0 == 0x2) { CreateByteField (Arg1, 0x02, PWST) - Store (PWST, Local0) - And (Local0, 0x01, Local0) + Local0 = PWST + Local0 &= 0x01 If (Local0) { /* Enable discrete graphics */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6d5048ca9e949a70f3619f05b74870c1f1fe30 Gerrit-Change-Number: 46192 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/s230u: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 24 Jan '21

24 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46191 ) Change subject: mb/lenovo/s230u: Convert to ASL 2.0 syntax ...................................................................... mb/lenovo/s230u: Convert to ASL 2.0 syntax Change-Id: I8843d418bd9c34a4f079444bc6ce8ecd4559e36d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/platform.asl 2 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46191/1 diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 888feac..a1e7379 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -128,7 +128,7 @@ /* Switched to AC power */ Method (_Q26, 0, NotSerialized) { - Store (One, PWRS) + PWRS = 1 Notify (^AC, 0x80) Notify (^BAT0, 0x80) \PNOT () @@ -138,7 +138,7 @@ /* Switched to battery power */ Method (_Q27, 0, NotSerialized) { - Store (Zero, PWRS) + PWRS = 0 Notify (^AC, 0x80) Notify (^BAT0, 0x80) \PNOT () @@ -148,7 +148,7 @@ /* Lid openend */ Method (_Q2A, 0, NotSerialized) { - Store (One, LIDS) + LIDS = 1 Notify(^LID, 0x80) ^HKEY.MHKQ (0x5002) } @@ -156,7 +156,7 @@ /* Lid closed */ Method (_Q2B, 0, NotSerialized) { - Store (Zero, LIDS) + LIDS = 0 Notify(^LID, 0x80) ^HKEY.MHKQ (0x5001) } @@ -237,7 +237,7 @@ /* FN+Esc pressed / FN row mode switch */ Method (_Q74, 0, NotSerialized) { - XOr(One, HKFA, HKFA) + HKFA = 1 ^ HKFA ^HKEY.MHKQ (0x6060) } @@ -271,11 +271,11 @@ { Acquire (XDHK, 0xFFFF) - ShiftLeft (One, Decrement (Arg0), Local0) + Local0 = 1 << Arg0-- If (Arg1) { - Or (Local0, DHKN, DHKN) + DHKN |= Local0 } Else { - And (Not(Local0), DHKN, DHKN) + DHKN &= ~Local0 } Release (XDHK) @@ -285,7 +285,7 @@ { Acquire (XDHK, 0xFFFF) - Store (Arg0, DHKC) + DHKC = Arg0 Release (XDHK) } @@ -294,11 +294,11 @@ { Acquire (XDHK, 0xFFFF) - Store (Zero, Local0) + Local0 = 0 if (DHKV) { - Store (DHKV, Local0) - Store (Zero, DHKV) + Local0 = DHKV + DHKV = 0 } Release (XDHK) @@ -310,7 +310,7 @@ { Acquire (XDHK, 0xFFFF) - Store (Arg0, DHKV) + DHKV = Arg0 Release (XDHK) @@ -321,7 +321,7 @@ /* LED support for thinkpad-acpi */ Method (LED, 2, NotSerialized) { - Or (Arg0, Arg1, HLCL) + HLCL = Arg0 | Arg1 } Device (AC) diff --git a/src/mainboard/lenovo/s230u/acpi/platform.asl b/src/mainboard/lenovo/s230u/acpi/platform.asl index 149fb3a..9ad3ff1 100644 --- a/src/mainboard/lenovo/s230u/acpi/platform.asl +++ b/src/mainboard/lenovo/s230u/acpi/platform.asl @@ -3,8 +3,8 @@ Method(_WAK,1) { /* Turn on radios */ - Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ - Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + GP33 = 1 /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + GP36 = 1 /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ /* There also is RF_OFF# on pin 20, controlled by the EC */ Return(Package(){0,0}) @@ -13,8 +13,8 @@ Method(_PTS,1) { /* Turn off radios */ - Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ - Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + GP33 = 0 /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + GP36 = 0 /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ /* There also is RF_OFF# on pin 20, controlled by the EC */ } @@ -22,7 +22,7 @@ { Method(_SST, 1, NotSerialized) { - If (LLess(Arg0, 2)) + If (Arg0 < 2) { /* Thinkpad LED on */ \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80) -- To view, visit https://review.coreboot.org/c/coreboot/+/46191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8843d418bd9c34a4f079444bc6ce8ecd4559e36d Gerrit-Change-Number: 46191 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/broadwell/chip.h: Drop unused fields
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46995 ) Change subject: soc/intel/broadwell/chip.h: Drop unused fields ...................................................................... soc/intel/broadwell/chip.h: Drop unused fields Broadwell boards now use the CPU code for Haswell. Therefore, these devicetree options are no longer used anywhere and can be removed. Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/chip.h 1 file changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46995/1 diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 81c9780..6540273 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -42,34 +42,6 @@ int cdclk; struct i915_gpu_controller_info gfx; - - /* - * Minimum voltage for C6/C7 state: - * 0x67 = 1.6V (full swing) - * ... - * 0x79 = 1.7V - * ... - * 0x83 = 1.8V (no swing) - */ - int vr_cpu_min_vid; - - /* - * Set slow VR ramp rate on C-state exit: - * 0 = Fast VR ramp rate / 2 - * 1 = Fast VR ramp rate / 4 - * 2 = Fast VR ramp rate / 8 - * 3 = Fast VR ramp rate / 16 - */ - int vr_slow_ramp_rate_set; - - /* Enable slow VR ramp rate */ - int vr_slow_ramp_rate_enable; - - /* Enable S0iX support */ - int s0ix_enable; - - /* TCC activation offset */ - uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/46995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Gerrit-Change-Number: 46995 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/broadwell: Select CPU_INTEL_HASWELL
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46953 ) Change subject: soc/intel/broadwell: Select CPU_INTEL_HASWELL ...................................................................... soc/intel/broadwell: Select CPU_INTEL_HASWELL This allows us to drop many now-redundant Kconfig options. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. The default configuration file also remains identical, as expected. Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/purism/librem_bdw/Kconfig M src/soc/intel/broadwell/Kconfig 5 files changed, 1 insertion(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46953/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 9c705e1..5301e32 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC @@ -59,10 +58,6 @@ default "samus" if BOARD_GOOGLE_SAMUS default "" -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7d6ff8d..e65b21f 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F @@ -40,10 +39,6 @@ default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index bb0fdf4..7ac5f1c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES @@ -26,11 +25,6 @@ string default "WHITETIP MOUNTAIN 2" - -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0166.rom" diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 173874c..ad764b7 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -1,6 +1,5 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW def_bool n - select CPU_INTEL_HASWELL select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_RESUME @@ -53,10 +52,6 @@ default "1.0" if BOARD_PURISM_LIBREM13_V1 default "2.0" if BOARD_PURISM_LIBREM15_V2 -config MAX_CPUS - int - default 8 - config PRE_GRAPHICS_DELAY int default 50 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5eebe59..22173d2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,14 +8,10 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_HASWELL select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -26,13 +22,8 @@ select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT - select PARALLEL_MP select RTC select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT @@ -84,18 +75,6 @@ hex default 0xf0000000 -config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406" -- To view, visit https://review.coreboot.org/c/coreboot/+/46953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Gerrit-Change-Number: 46953 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Move romstage.c to Haswell
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46951 ) Change subject: soc/intel/broadwell: Move romstage.c to Haswell ...................................................................... soc/intel/broadwell: Move romstage.c to Haswell Broadwell no longer has CPU code. Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc R src/cpu/intel/haswell/romstage.c M src/soc/intel/broadwell/Makefile.inc 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46951/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 3c4db4f..bfb5011 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,4 +1,6 @@ ramstage-y += haswell_init.c + +romstage-y += romstage.c romstage-y += ../car/romstage.c ramstage-y += acpi.c diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/cpu/intel/haswell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/cpu/romstage.c rename to src/cpu/intel/haswell/romstage.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7f42b1d..3f06913 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -2,8 +2,6 @@ subdirs-y += pch -romstage-y += cpu/romstage.c - bootblock-y += bootblock.c romstage-y += early_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Gerrit-Change-Number: 46951 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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