coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: WIP: soc/amd/picasso/acpi: Add power resources for UART0
by Raul Rangel (Code Review) 22 Jan '21

22 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42474 ) Change subject: WIP: soc/amd/picasso/acpi: Add power resources for UART0 ...................................................................... WIP: soc/amd/picasso/acpi: Add power resources for UART0 BUG=b:153001807 TEST=suspend and resume with trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec --- M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42474/1 diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 6577cfc..036ebc0 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -140,6 +140,7 @@ AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) AOAC_DEVICE(I2C4, 9, 5) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 00774fd..cb186c4 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,17 @@ Return (Local0) } } + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec Gerrit-Change-Number: 42474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/mediatek/mt8183: Fix pq module size config
by Yu-Ping Wu (Code Review) 22 Jan '21

22 Jan '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46626 ) Change subject: soc/mediatek/mt8183: Fix pq module size config ...................................................................... soc/mediatek/mt8183: Fix pq module size config For pq module size registers such as DISP_AAL_SIZE, the high bits should be HSIZE, while low bits should be VSIZE. BUG=b:171167210 TEST=none BRANCH=kukui Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/ddp.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46626/1 diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index eba3f5e..395c821 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -34,7 +34,7 @@ static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, int enable_relay) { - write32(&regs->size, height << 16 | width); + write32(&regs->size, width << 16 | height); if (enable_relay) write32(&regs->cfg, PQ_RELAY_MODE); write32(&regs->en, PQ_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/46626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Gerrit-Change-Number: 46626 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: cpu/intel/haswell: Enable timed MWAIT if supported
by Angel Pons (Code Review) 22 Jan '21

22 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46916 ) Change subject: cpu/intel/haswell: Enable timed MWAIT if supported ...................................................................... cpu/intel/haswell: Enable timed MWAIT if supported Broadwell unconditionally enables it, but not all Haswell steppings support it. Thus, check the capability bit before attempting to set it. Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46916/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index b23fbac..2352489 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -36,6 +36,7 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) +#define TIMED_MWAIT_SUPPORTED (1 << (37 - 32)) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 438a317..21f3f4a 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -433,7 +433,9 @@ static void configure_c_states(void) { - msr_t msr; + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + + const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 30); // Package c-state Undemotion Enable @@ -443,6 +445,10 @@ msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection + + if (timed_mwait_capable) + msr.lo |= (1 << 31); // Timed MWAIT Enable + /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/46916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a Gerrit-Change-Number: 46916 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 22 Jan '21

22 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45554 ) Change subject: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/battery.asl 1 file changed, 81 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45554/1 diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 7924edf..33b19ae 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope(\_SB) { +Scope(_SB) { Name(NIMH, "NiMH") Name(LION, "Lion") @@ -10,7 +10,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -18,7 +18,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT) { + If (^^PCI0.LPCB.EC0.BAT) { Return(0x1f) } Else { Return(0x0f) @@ -45,28 +45,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC0 + PBIF [4] = ^^PCI0.LPCB.EC0.BDV0 - Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC0 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTYP) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTYP) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -75,33 +75,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT) { - Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT) { + PBST [3] = ^^PCI0.LPCB.EC0.BPV0 - Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 * 0x64 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BFC0 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BFC0) + Local3 = ^^PCI0.LPCB.EC0.BFC0 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [0x02] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 + Local0 = ^^PCI0.LPCB.EC0.BPR0 + Local0 = (~Local0 & 0xFFFF) + PBST [1] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CHRG) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CHRG) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 0 } } } @@ -115,7 +117,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -123,7 +125,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT2) { + If (^^PCI0.LPCB.EC0.BAT2) { Return(0x1f) } Else { Return(0x0f) @@ -150,28 +152,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC2 + PBIF [0x04] = ^^PCI0.LPCB.EC0.BDV2 - Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC2 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTY2) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTY2) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -180,33 +182,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT2) { - Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT2) { + PBST [0x03] = ^^PCI0.LPCB.EC0.BPV2 - Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 * 100 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BRC2 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BRC2) + Local3 = ^^PCI0.LPCB.EC0.BFC2 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [2] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 + Local0 = ^^PCI0.LPCB.EC0.BPR2 + Local0 = (~Local0 & 0xFFFF) + PBST [One] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CRG2) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CRG2) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 1 } } } @@ -223,19 +227,19 @@ Name (ACST, 0x00) Method (_PSR, 0) { - If(ACFG) { - Store(ACST, Local0) + If (ACFG) { + Local0 = ACST } Else { - Store(\_SB.PCI0.LPCB.EC0.ADP, Local0) - Store(Local0, ACST) - Store(1, ACFG) + Local0 = ^^PCI0.LPCB.EC0.ADP + ACST = Local0 + ACFG = 1 } Sleep(120) Return (Local0) } Name(_PCL, Package(){ - \_SB, + _SB, BAT0, BAT1 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/45554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Gerrit-Change-Number: 45554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 25

Change in coreboot[master]: mb/google/dedede: remove unuse I2C1
by Alec Wang (Code Review) 22 Jan '21

22 Jan '21

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46486 ) Change subject: mb/google/dedede: remove unuse I2C1 ...................................................................... mb/google/dedede: remove unuse I2C1 remove unuse I2C1 BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: I88b6f12728d9ae25882c141d6a8558f76591d3a2 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46486/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 2ba6d9d..fd532d1 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -9,7 +9,6 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | #| I2C2 | Touchscreen | #| I2C4 | Audio | #+-------------------+---------------------------+ @@ -21,9 +20,6 @@ .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, @@ -39,7 +35,7 @@ register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/46486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88b6f12728d9ae25882c141d6a8558f76591d3a2 Gerrit-Change-Number: 46486 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: cpu/intel/haswell: Clean up CPUID definitions
by Angel Pons (Code Review) 21 Jan '21

21 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46915 ) Change subject: cpu/intel/haswell: Clean up CPUID definitions ...................................................................... cpu/intel/haswell: Clean up CPUID definitions The `mobile` suffix is misleading, since desktop CPUs share the same CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead. Finally, add Broadwell CPUIDs in preparation for merging CPU code. Note that steppings for Haswell in various comments are incorrect. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 31 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46915/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 284ff01..b23fbac 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -5,19 +5,32 @@ #include <stdint.h> -/* Haswell CPU types */ -#define HASWELL_FAMILY_MOBILE 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 -/* Haswell CPU steppings */ -#define HASWELL_STEPPING_MOBILE_A0 1 -#define HASWELL_STEPPING_MOBILE_B0 2 -#define HASWELL_STEPPING_MOBILE_C0 3 -#define HASWELL_STEPPING_MOBILE_D0 4 -#define HASWELL_STEPPING_ULT_B0 0 -#define HASWELL_STEPPING_ULT_C0 1 +/* Haswell CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 -/* Haswell bus clock is fixed at 100MHz */ +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 + +/* Crystalwell CPUIDs */ +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 + +/* Broadwell CPUIDs */ +#define CPUID_BROADWELL_C0 0x40671 + +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 + +/* Haswell and Broadwell bus clock is fixed at 100MHz */ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 44bbbfd..438a317 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -694,13 +694,13 @@ }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ - { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ - { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ - { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ - { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ + { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Gerrit-Change-Number: 46915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: cpu/intel/haswell: Add s0ix support
by Angel Pons (Code Review) 21 Jan '21

21 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46924 ) Change subject: cpu/intel/haswell: Add s0ix support ...................................................................... cpu/intel/haswell: Add s0ix support Backported from Broadwell. This only matters for ULT variants. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h 2 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46924/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 7c99df3..0f11e5f 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,12 @@ #include <southbridge/intel/lynxpoint/pch.h> +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10, +}; + static int cstate_set_lp[3] = { C_STATE_C1E, C_STATE_C3, @@ -94,6 +100,21 @@ ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static bool is_s0ix_enabled(void) +{ + if (!haswell_is_ult()) + return false; + + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (!lapic || !lapic->chip_info) + return false; + + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + return conf->s0ix_enable; +} + static void generate_C_state_entries(void) { acpi_cstate_t map[3]; @@ -111,7 +132,9 @@ if (!cpu || !cpu->cstates) return; - if (haswell_is_ult()) + if (is_s0ix_enabled()) + set = cstate_set_s0ix; + else if (haswell_is_ult()) set = cstate_set_lp; else set = cstate_set_trad; diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 16f1079..776e239 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -34,4 +34,7 @@ int tcc_offset; /* TCC Activation Offset */ struct cpu_vr_config vr_config; + + /* Enable S0iX support */ + bool s0ix_enable; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b Gerrit-Change-Number: 46924 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/broadwell/igd.c: Add missing "break"
by HAOUAS Elyes (Code Review) 20 Jan '21

20 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45165 ) Change subject: soc/intel/broadwell/igd.c: Add missing "break" ...................................................................... soc/intel/broadwell/igd.c: Add missing "break" Change-Id: I29dd96a7e00ddf73bb281e6fbbf256e439bce2f1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/igd.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45165/1 diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1..39c551d 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -467,6 +467,7 @@ dpdiv = 338; reg_em4 = 8; reg_em5 = 225; + break; default: return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29dd96a7e00ddf73bb281e6fbbf256e439bce2f1 Gerrit-Change-Number: 45165 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/amd/pi/*/northbridge.c: Reduce difference
by HAOUAS Elyes (Code Review) 20 Jan '21

20 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46263 ) Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ...................................................................... nb/amd/pi/*/northbridge.c: Reduce difference Change-Id: I8d173916f38701d710a735cc12237bac6236ebab Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 122 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46263/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 90d5603..ce0b23a 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -43,14 +43,14 @@ dev = __f1_dev[0]; u32 temp; temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; return d; } @@ -60,10 +60,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 /*| (3<<4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -133,7 +133,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn<<12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -148,8 +148,8 @@ * @retval 0 resource exists, but is not usable * @retval 1 resource exists, but has been allocated before */ -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; unsigned int nodeid, link = 0; @@ -250,10 +250,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -262,10 +264,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -299,23 +303,21 @@ char buf[50]; /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { + if (!(resource->flags & IORESOURCE_ASSIGNED)) return; - } /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { + if (resource->flags & IORESOURCE_STORED) return; - } /* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return; /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { + if ((resource->index & 0xffff) < 0x1000) return; - } + /* Get the base address */ rbase = resource->base; @@ -382,7 +384,8 @@ /* Find the nodeid */ nodeid = amdfam15_nodeid(dev); - create_vga_resource(dev, nodeid); //TODO: do we need this? + /* TODO: do we need this? */ + create_vga_resource(dev, nodeid); /* Set each resource we have found */ for (res = dev->resource_list; res; res = res->next) { @@ -569,18 +572,18 @@ /* Find the already assigned resource pairs */ get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { u32 base, limit; - base = f1_read_config32(reg); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); + nodeid = (limit & 0xf) + (base & 0x30); } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); } reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; @@ -597,8 +600,7 @@ /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - pci_domain_read_resources(dev); - + pci_domain_read_resources(dev); } static void domain_enable_resources(struct device *dev) @@ -622,7 +624,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 1) { // we find the hole + if (hole & 1) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -638,7 +640,8 @@ dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; + if (!(d.base & 1)) + continue; base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -675,8 +678,9 @@ /* Round mmio_basek to something the processor can support */ mmio_basek &= ~((1 << 6) -1); - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1); @@ -689,7 +693,7 @@ mem_hole = get_hw_mem_hole_info(); - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; } @@ -702,7 +706,8 @@ d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; + if (!(d.mask & 1)) + continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; @@ -717,8 +722,6 @@ } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { @@ -766,7 +769,7 @@ static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] } static void cpu_bus_scan(struct device *dev) @@ -849,7 +852,8 @@ siblings &= 0xFF; } } else { - siblings = 0; //default one core + /* default one core */ + siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 09bdd82..594aebd 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -160,8 +160,9 @@ dev = __f0_dev[nodeid]; if (!dev) continue; - for (link = 0; !res && (link < 8); link++) + for (link = 0; !res && (link < 8); link++) { res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } } if (!res) @@ -226,10 +227,12 @@ /* Initialize the io space constraints on the current bus */ resource = amdfam15_find_iopair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; } @@ -237,10 +240,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -249,10 +254,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -336,14 +343,16 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) + break; + } + else break; } } @@ -365,7 +374,7 @@ /* Find the nodeid */ nodeid = amdfam15_nodeid(dev); - /* do we need this? */ + /* TODO: do we need this? */ create_vga_resource(dev, nodeid); /* Set each resource we have found */ @@ -624,8 +633,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { - /* we find the hole */ + if (hole & 2) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -882,7 +890,7 @@ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 75e1f02..16a98b7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -50,14 +50,14 @@ dev = __f1_dev[0]; u32 temp; temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; return d; } @@ -67,10 +67,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 /*| (3<<4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -140,7 +140,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn<<12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -155,8 +155,8 @@ * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; unsigned int nodeid, link = 0; @@ -257,10 +257,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam16_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -269,10 +271,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam16_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -313,23 +317,21 @@ char buf[50]; /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { + if (!(resource->flags & IORESOURCE_ASSIGNED)) return; - } /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { + if (resource->flags & IORESOURCE_STORED) return; - } /* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return; /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { + if ((resource->index & 0xffff) < 0x1000) return; - } + /* Get the base address */ rbase = resource->base; @@ -365,14 +367,16 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) + break; + } + else break; } } @@ -394,7 +398,8 @@ /* Find the nodeid */ nodeid = amdfam16_nodeid(dev); - create_vga_resource(dev, nodeid); //TODO: do we need this? + /* TODO: do we need this? */ + create_vga_resource(dev, nodeid); /* Set each resource we have found */ for (res = dev->resource_list; res; res = res->next) { @@ -925,18 +930,18 @@ /* Find the already assigned resource pairs */ get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { u32 base, limit; - base = f1_read_config32(reg); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); + nodeid = (limit & 0xf) + (base & 0x30); } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); } reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; @@ -952,6 +957,7 @@ } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ + pci_domain_read_resources(dev); } @@ -976,7 +982,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { // we find the hole + if (hole & 2) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -992,7 +998,8 @@ dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; + if (!(d.base & 1)) + continue; base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -1029,8 +1036,9 @@ /* Round mmio_basek to something the processor can support */ mmio_basek &= ~((1 << 6) -1); - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1); @@ -1043,7 +1051,7 @@ mem_hole = get_hw_mem_hole_info(); - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; } @@ -1056,7 +1064,8 @@ d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; + if (!(d.mask & 1)) + continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; @@ -1071,8 +1080,6 @@ } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { @@ -1129,7 +1136,7 @@ static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] } static void cpu_bus_scan(struct device *dev) @@ -1195,7 +1202,6 @@ /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - add_more_links(cdb_dev, 4); } @@ -1213,7 +1219,8 @@ siblings &= 0xFF; } } else { - siblings = 0; //default one core + /* default one core */ + siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", @@ -1238,7 +1245,7 @@ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/46263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d173916f38701d710a735cc12237bac6236ebab Gerrit-Change-Number: 46263 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 20 Jan '21

20 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45816 ) Change subject: soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h> ...................................................................... soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h> Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/mrc_cache.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45816/1 diff --git a/src/soc/amd/picasso/mrc_cache.c b/src/soc/amd/picasso/mrc_cache.c index ad0d964..24d86e0 100644 --- a/src/soc/amd/picasso/mrc_cache.c +++ b/src/soc/amd/picasso/mrc_cache.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <assert.h> #include <boot_device.h> -#include <bootstate.h> #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Gerrit-Change-Number: 45816 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020