coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/roda: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 19 Jan '21

19 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46086 ) Change subject: mb/roda: Convert to ASL 2.0 syntax ...................................................................... mb/roda: Convert to ASL 2.0 syntax Change-Id: I4d91b02244bdfca122b60c389d81a8fe7999a232 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/roda/rk886ex/acpi/battery.asl M src/mainboard/roda/rk886ex/acpi/ec.asl M src/mainboard/roda/rk886ex/acpi/superio.asl M src/mainboard/roda/rk9/acpi/battery.asl M src/mainboard/roda/rk9/acpi/ec.asl M src/mainboard/roda/rv11/acpi/alsd.asl 6 files changed, 251 insertions(+), 251 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46086/1 diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index de13049..b2ce57d 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -69,76 +69,76 @@ /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat1", Index(PBIF, 9)) - Store ("001", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat1" + PBIF [10] = "001" + PBIF [11] = "LION" + PBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (!Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA1) + Local0 = GP38 + If (!Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA1 = Local0 } } } } - Store (CBA1, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA1 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P63S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0x0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } @@ -209,85 +209,85 @@ /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat2", Index(PBIF, 9)) - Store ("002", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat2" + PBIF [10] = "002" + PBIF [11] = "LION" + PBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (!Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA2) + Local0 = GP38 + If (!Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA2 = Local0 } } } } - Store (CBA2, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA2 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P62S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0x0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } Method (RDW, 1) { - Store (0x16, \_SB.PCI0.LPCB.EC0.SMAD) - Store (Arg0, \_SB.PCI0.LPCB.EC0.SMCM) - Store (0x09, \_SB.PCI0.LPCB.EC0.SMPR) - While (LNotEqual(\_SB.PCI0.LPCB.EC0.SMPR, 0x00)) { + \_SB.PCI0.LPCB.EC0.SMAD = 0x16 + \_SB.PCI0.LPCB.EC0.SMCM = Arg0 + \_SB.PCI0.LPCB.EC0.SMPR = 0x09 + While (\_SB.PCI0.LPCB.EC0.SMPR != 0x00) { Stall (1) } @@ -300,11 +300,11 @@ Method (_PSR, 0) { If (\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.P60S, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.P60S If (Local0) { - Store (0, PWRS) + PWRS = 0 } Else { - Store (1, PWRS) + PWRS = 1 } } diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 9ec0c36..ace6ab2 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -63,8 +63,8 @@ // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - If (LEqual(Arg0, 0x03)) { - Store (Arg1, ECON) + If (Arg0 == 0x03) { + ECON = Arg1 } } @@ -72,20 +72,20 @@ Method (_Q11, 0) { - Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Debug = "_Q11: Fn-F8 (Sleep Button) pressed" Notify(SLPB, 0x80) } Method (_Q12, 0) { - Store("_Q12: Fn-F9 (Display Switch) pressed", Debug) + Debug = "_Q12: Fn-F9 (Display Switch) pressed" Notify (\_SB.PCI0.GFX0, 0x82) - // Store(1, TLST) + // TLST = 1 } Method (_Q30, 0) { - Store("_Q30: AC In/Out", Debug) + Debug = "_Q30: AC In/Out" Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery // Notify the Batteries @@ -95,16 +95,16 @@ Method (_Q31, 0) { - Store("_Q31: LID Open/Close", Debug) + Debug = "_Q31: LID Open/Close" Notify(LID0, 0x80) } Method (_Q32, 0) { - Store("_Q32: Battery 1 In/Out", Debug) + Debug = "_Q32: Battery 1 In/Out" If (ECON) { - Store (P62S, Local0) - If (Not(Local0)) { + Local0 = P62S + If (!Local0) { Notify(BAT1, 0x80) } } @@ -112,10 +112,10 @@ Method (_Q33, 0) { - Store("_Q33: Battery 2 In/Out", Debug) + Debug = "_Q33: Battery 2 In/Out" If (ECON) { - Store (P63S, Local0) - If (Not(Local0)) { + Local0 = P63S + If (!Local0) { Notify(BAT2, 0x80) } } @@ -123,33 +123,33 @@ Method (_Q34, 0) { - Store("_Q34: LPT/FDD", Debug) + Debug = "_Q34: LPT/FDD" // PHSS(0x70) } Method (_Q35, 0) { - Store("_Q35: Processor is hot", Debug) + Debug = "_Q35: Processor is hot" } Method (_Q36, 0) { - Store("_Q36: Thermal Warning", Debug) + Debug = "_Q36: Thermal Warning" } Method (_Q37, 0) { - Store("_Q37: PME", Debug) + Debug = "_Q37: PME" } Method (_Q38, 0) { - Store("_Q38: Thermal", Debug) + Debug = "_Q38: Thermal" } Method (_Q39, 0) { - Store("_Q39: Thermal", Debug) + Debug = "_Q39: Thermal" } // TODO Scope _SB devices for AC power, LID, Power button diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 6f356e9..e11f7c4 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -19,13 +19,13 @@ Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -52,18 +52,18 @@ Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMAP, 0)) { + If (CMAP == 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff), + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -76,12 +76,12 @@ { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -106,8 +106,8 @@ IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -119,15 +119,15 @@ \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x24, 0xfe), + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -140,29 +140,29 @@ WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff), + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -170,22 +170,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff), + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -200,24 +200,24 @@ Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMBP, 0)) { + If (CMBP == 0) { Return (0) } /* IRDA? */ - Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + Local0 = READ (0, 0x0c, 0x38) + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -230,12 +230,12 @@ { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -260,8 +260,8 @@ IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -273,14 +273,14 @@ \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + IRQ = 1 << Local0 Return(RSRC) } @@ -293,55 +293,55 @@ WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff), + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff), + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl index 72475d6..88e8aca 100644 --- a/src/mainboard/roda/rk9/acpi/battery.asl +++ b/src/mainboard/roda/rk9/acpi/battery.asl @@ -59,9 +59,9 @@ Method(_BIF, 0) { If(\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1)) - Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2)) - Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4)) + PBIF [1] = \_SB.PCI0.LPCB.EC0.B1DW + PBIF [2] = \_SB.PCI0.LPCB.EC0.B1FW + PBIF [4] = \_SB.PCI0.LPCB.EC0.B1DV } Return(PBIF) @@ -71,26 +71,26 @@ Method(_BST, 0) { If(\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0) - If (LGreaterEqual (Local0, 0x8000)) { - Subtract (0x10000, Local0, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.B1PW + If (Local0 >= 0x8000) { + Local0 = 0x10000 - Local0 } - Store (Local0, Index(PBST, 1)) - Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3)) + PBST [1] = Local0 + PBST [3] = \_SB.PCI0.LPCB.EC0.B1PV - Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2)) + PBST [2] = \_SB.PCI0.LPCB.EC0.B1RW If (\_SB.PCI0.LPCB.EC0.ACCH) { If (\_SB.PCI0.LPCB.EC0.B1CH) { If (\_SB.PCI0.LPCB.EC0.B1CG) { - Store (2, Index(PBST, 0)) + PBST [0] = 2 } } } Else { If (\_SB.PCI0.LPCB.EC0.B1LO) { - Store (5, Index(PBST, 0)) + PBST [0] = 5 } Else { - Store (1, Index(PBST, 0)) + PBST [0] = 1 } } } @@ -153,9 +153,9 @@ Method(_BIF, 0) { If(\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1)) - Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2)) - Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4)) + PBIF [1] = \_SB.PCI0.LPCB.EC0.B2DW + PBIF [2] = \_SB.PCI0.LPCB.EC0.B2FW + PBIF [4] = \_SB.PCI0.LPCB.EC0.B2DV } Return(PBIF) @@ -165,26 +165,26 @@ Method(_BST, 0) { If(\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0) - If (LGreaterEqual (Local0, 0x8000)) { - Subtract (0x10000, Local0, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.B2PW + If (Local0 >= 0x8000) { + Local0 = 0x10000 - Local0 } - Store (Local0, Index(PBST, 1)) - Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3)) + PBST [1] = Local0 + PBST [3] = \_SB.PCI0.LPCB.EC0.B2PV - Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2)) + PBST [2] = \_SB.PCI0.LPCB.EC0.B2RW If (\_SB.PCI0.LPCB.EC0.ACCH) { If (\_SB.PCI0.LPCB.EC0.B2CH) { If (\_SB.PCI0.LPCB.EC0.B2CG) { - Store (2, Index(PBST, 0)) + PBST [0] = 2 } } } Else { If (\_SB.PCI0.LPCB.EC0.B2LO) { - Store (5, Index(PBST, 0)) + PBST [0] = 5 } Else { - Store (1, Index(PBST, 0)) + PBST [0] = 1 } } } @@ -199,7 +199,7 @@ Name (_HID, "ACPI0003") Method (_PSR, 0) { - Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS) + PWRS = \_SB.PCI0.LPCB.EC0.ACCH Stall (0x02) Return (PWRS) } diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 7284ccd..fa90686 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -70,8 +70,8 @@ // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - If (LEqual(Arg0, 0x03)) { - Store (Arg1, ECON) + If (Arg0 == 0x03) { + ECON = Arg1 } } @@ -79,98 +79,98 @@ Method (_Q11, 0) { - Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Debug = "_Q11: Fn-F8 (Sleep Button) pressed" Notify(SLPB, 0x80) } Method (_Q30, 0) { - Store("_Q30: AC In", Debug) + Debug = "_Q30: AC In" Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery } Method (_Q31, 0) { - Store("_Q31: AC Out", Debug) + Debug = "_Q31: AC Out" Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery } Method (_Q32, 0) { - Store("_Q32: Bat1 In", Debug) + Debug = "_Q32: Bat1 In" Notify(BAT1, 0x81) } Method (_Q33, 0) { - Store("_Q33: Bat1 Out", Debug) + Debug = "_Q33: Bat1 Out" Notify(BAT1, 0x81) } Method (_Q34, 0) { - Store("_Q34: Bat2 In", Debug) + Debug = "_Q34: Bat2 In" Notify(BAT2, 0x81) } Method (_Q35, 0) { - Store("_Q35: Bat2 Out", Debug) + Debug = "_Q35: Bat2 Out" Notify(BAT2, 0x81) } Method (_Q36, 0) { - Store("_Q36: Bat1 Low Power", Debug) + Debug = "_Q36: Bat1 Low Power" Notify(BAT1, 0x80) } Method (_Q37, 0) { - Store("_Q37: Bat1 Full Charge", Debug) + Debug = "_Q37: Bat1 Full Charge" Notify(BAT1, 0x80) } Method (_Q38, 0) { - Store("_Q38: Bat2 Low Power", Debug) + Debug = "_Q38: Bat2 Low Power", Notify(BAT2, 0x80) } Method (_Q39, 0) { - Store("_Q39: Bat2 Full Charge", Debug) + Debug = "_Q39: Bat2 Full Charge" Notify(BAT2, 0x80) } Method (_Q40, 0) { - Store("_Q40: LID Open/Close", Debug) + Debug = "_Q40: LID Open/Close" Notify(LID0, 0x80) } Method (_Q41, 0) { - Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug) + Debug = "_Q41: Floppy on Parallel Port: Call the Museum!" } Method (_Q50, 0) { - Store("_Q50: Processor is hot", Debug) + Debug = "_Q50: Processor is hot" Notify(\_TZ.THRM, 0x80) } Method (_Q51, 0) { - Store("_Q51: Processor is boiling", Debug) + Debug = "_Q51: Processor is boiling" Notify(\_TZ.THRM, 0x80) } Method (_Q52, 0) { - Store("_Q52: Processor is burning", Debug) + Debug = "_Q52: Processor is burning" Notify(\_TZ.THRM, 0x80) } diff --git a/src/mainboard/roda/rv11/acpi/alsd.asl b/src/mainboard/roda/rv11/acpi/alsd.asl index f910dc6..b3028e3 100644 --- a/src/mainboard/roda/rv11/acpi/alsd.asl +++ b/src/mainboard/roda/rv11/acpi/alsd.asl @@ -10,12 +10,12 @@ Method (_ALI, 0, NotSerialized) // _ALI: Ambient Light Illuminance { - Store (\_SB.PCI0.LPCB.EC0.LUXH, Local0) - Or (ShiftLeft (Local0, 8), \_SB.PCI0.LPCB.EC0.LUXL, Local0) - Store ("-----> _ALI: ", Debug) - Store (Local0, Debug) - Store (\_SB.PCI0.LPCB.EC0.LUXH, Debug) - Store (\_SB.PCI0.LPCB.EC0.LUXL, Debug) + Local0 = \_SB.PCI0.LPCB.EC0.LUXH + Local0 = (Local0 << 8) | \_SB.PCI0.LPCB.EC0.LUXL + Debug = "-----> _ALI: " + Debug = Local0 + Debug = \_SB.PCI0.LPCB.EC0.LUXH + Debug = \_SB.PCI0.LPCB.EC0.LUXL Return (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91b02244bdfca122b60c389d81a8fe7999a232 Gerrit-Change-Number: 46086 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/google/volteer: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 19 Jan '21

19 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46222 ) Change subject: mb/google/volteer: Convert to ASL 2.0 syntax ...................................................................... mb/google/volteer: Convert to ASL 2.0 syntax Change-Id: I84bd93970e363bed4c4da616b5c16ac7e2332861 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46222/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 51034c3..91f4e8f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -178,12 +178,12 @@ #endif Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -202,7 +202,7 @@ /* Pull SNRPWR_EN low */ CTXS(GPP_H14) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -479,12 +479,12 @@ STXS(GPP_D4) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -499,7 +499,7 @@ /* Pull SNRPWR_EN low */ CTXS(GPP_D18) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bd93970e363bed4c4da616b5c16ac7e2332861 Gerrit-Change-Number: 46222 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver
by Roger Lu (Code Review) 19 Jan '21

19 Jan '21

Hello Roger Lu, Ran Bi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46878 to review the following change. Change subject: soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver ...................................................................... soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver Add clkbuf and srclken_rc init for low power. TEST=boot asurada Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> Change-Id: I947bf14df7a307bf359c590c2a20265882b3f1be --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/clkbuf.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/clkbuf.h M src/soc/mediatek/mt8192/include/soc/pmif.h M src/soc/mediatek/mt8192/include/soc/rtc.h A src/soc/mediatek/mt8192/include/soc/srclken_rc.h M src/soc/mediatek/mt8192/pmif.c M src/soc/mediatek/mt8192/rtc.c A src/soc/mediatek/mt8192/srclken_rc.c 11 files changed, 1,381 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46878/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d695824..6890910 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += clkbuf.c srclken_rc.c bootblock-y += ../common/rtc.c rtc.c bootblock-y += mt6315.c bootblock-y += mt6359p.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c old mode 100755 new mode 100644 index dac9a37..5d1380a --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -1,14 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/clkbuf.h> +#include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pll.h> #include <soc/pmif.h> -#include <soc/wdt.h> #include <soc/rtc.h> -#include <soc/eint_event.h> +#include <soc/srclken_rc.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { @@ -19,5 +21,7 @@ mt6359p_init(); mt6315_init(); unmask_eint_event_mask(); + srclken_rc_init(); + clk_buf_init(); rtc_boot(); } diff --git a/src/soc/mediatek/mt8192/clkbuf.c b/src/soc/mediatek/mt8192/clkbuf.c new file mode 100644 index 0000000..937a227 --- /dev/null +++ b/src/soc/mediatek/mt8192/clkbuf.c @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/clkbuf.h> +#include <soc/pmif.h> +#include <soc/srclken_rc.h> + + +#define BUFTAG "[CLKBUF]" +#define buf_info(fmt, arg ...) printk(BIOS_INFO, BUFTAG "%s,%d: " fmt, \ + __func__, __LINE__, ## arg) + +//#define clkbuf_readl_ap(addr) read32(addr) +//#define clkbuf_writel_ap(addr, val) write32(addr, val) + + +#define PMIC_REG_MASK 0xFFFF +#define PMIC_REG_SHIFT 0 + +/* #define CLKBUF_CONN_SUPPORT_CTRL_FROM_I1 */ + +#if 0 +#if MTK_SRCLKEN_RC_FULL_SET +#define PMIC_CW00_INIT_VAL 0x4A4D /* 0100 1010 0100 1101 */ +#define PMIC_CW09_INIT_VAL 0x51F0 /* 0101 0001 1111 0000 */ +#else +#define PMIC_CW00_INIT_VAL 0x4E1D /* 0100 1110 0001 1101 */ +#define PMIC_CW09_INIT_VAL 0x31F0 /* 0011 0001 1111 0000 */ +#endif +#endif + +#define PMIC_CW00_INIT_VAL 0x4005 /* 0100 0000 0000 0101 */ +#define PMIC_CW09_INIT_VAL 0x01F0 /* 0000 0001 1111 0000 */ + +static struct pmif *pmif_arb = NULL; + +static int buf_read(u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + return pmif_arb->read_cmd(pmif_arb, 0, addr, rdata); +} + +static int buf_write(u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + return pmif_arb->write_cmd(pmif_arb, 0, addr, wdata); +} + +static u32 buf_read_field(u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + buf_read(reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +static void buf_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + buf_read(reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + buf_write(reg, new); +} + +static void clk_buf_dump_clkbuf_log(void) +{ + u32 pmic_cw00 = 0, pmic_cw09 = 0, pmic_cw12 = 0, pmic_cw13 = 0, + pmic_cw15 = 0, pmic_cw19 = 0, top_spi_con1 = 0, + ldo_vrfck_op_en = 0, ldo_vbbck_op_en = 0, ldo_vrfck_en = 0, + ldo_vbbck_en = 0; + /*u32 vrfck_vosel = 0, vrfck_votrim = 0;*/ + u32 vrfck_hv_en = 0; + + pmic_cw00 = buf_read_field(PMIC_RG_DCXO_CW00, 0xffff, 0); + pmic_cw09 = buf_read_field(PMIC_RG_DCXO_CW09, 0xffff, 0); + pmic_cw12 = buf_read_field(PMIC_RG_DCXO_CW12, 0xffff, 0); + pmic_cw13 = buf_read_field(PMIC_RG_DCXO_CW13, 0xffff, 0); + pmic_cw15 = buf_read_field(PMIC_RG_DCXO_CW15, 0xffff, 0); + pmic_cw19 = buf_read_field(PMIC_RG_DCXO_CW19, 0xffff, 0); + top_spi_con1 = buf_read_field(PMIC_RG_TOP_SPI_CON1, 0x1, 0); + ldo_vrfck_op_en = buf_read_field(PMIC_RG_LDO_VRFCK_OP_EN, 0x1, 14); + ldo_vbbck_op_en = buf_read_field(PMIC_RG_LDO_VBBCK_OP_EN, 0x1, 14); + ldo_vrfck_en = buf_read_field(PMIC_RG_LDO_VRFCK_CON0, 0x1, 0); + ldo_vbbck_en = buf_read_field(PMIC_RG_LDO_VBBCK_CON0, 0x1, 0); + buf_info("DCXO_CW00/09/12/13/15/19=0x%x %x %x %x %x %x\n", + pmic_cw00, pmic_cw09, pmic_cw12, + pmic_cw13, pmic_cw15, pmic_cw19); + buf_info("spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x%x %x %x %x %x\n", + top_spi_con1, ldo_vrfck_op_en, ldo_vbbck_op_en, + ldo_vrfck_en, ldo_vbbck_en); + + vrfck_hv_en = buf_read_field(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, 0x1, 9); + buf_info("clk buf vrfck_hv_en=0x%x\n", vrfck_hv_en); +} + +static void clk_buf_init_pmic_clkbuf(void) +{ + /* Dump registers before setting */ + clk_buf_dump_clkbuf_log(); + +#if 1 + /* 1.0 XO_WCN/XO_RF switch from VS1 to LDO VRFCK_1 */ + /* unlock pmic key */ + buf_write_field(PMIC_TOP_TMA_KEY, 0x9CA6, 0xFFFF, 0); + + /* 1.1 set VRFCK input supply(11.ac mode) */ + buf_write_field(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, 0x0, + PMIC_RG_VRFCK_HV_EN_MASK, PMIC_RG_VRFCK_HV_EN_SHIFT); + + /* 1.2.0 Set VRFCK En = 0 */ + buf_write_field(PMIC_RG_LDO_VRFCK_CON0, 0x0, + PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT); + /* 1.2.1 set VRFCK1 as power src */ + buf_write_field(PMIC_RG_LDO_VRFCK_ELR, 0x1, + PMIC_RG_LDO_VRFCK_ANA_SEL_MASK, PMIC_RG_LDO_VRFCK_ANA_SEL_SHIFT); + + /* 1.2.2 switch LDO-RFCK to LDO-RFCK1 */ + buf_write_field(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, 0x0, + PMIC_RG_VRFCK_NDIS_EN_MASK, PMIC_RG_VRFCK_NDIS_EN_SHIFT); + buf_write_field(PMIC_RG_DCXO_ADLDO_BIAS_ELR_1, 0x1, + PMIC_RG_VRFCK_1_NDIS_EN_MASK, PMIC_RG_VRFCK_1_NDIS_EN_SHIFT); + + /* 1.2.0 Set VRFCK En = 1 */ + buf_write_field(PMIC_RG_LDO_VRFCK_CON0, 0x1, + PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT); + + /* 1.2.3 lock pmic key */ + buf_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + + /* enable XO LDO */ + buf_write_field(PMIC_RG_LDO_VRFCK_OP_EN_SET, 0x1, + PMIC_RG_LDO_VRFCK_HW14_OP_EN_MASK, PMIC_RG_LDO_VRFCK_HW14_OP_EN_SHIFT); + buf_write_field(PMIC_RG_LDO_VBBCK_OP_EN_SET, 0x1, + PMIC_RG_LDO_VBBCK_HW14_OP_EN_MASK, PMIC_RG_LDO_VBBCK_HW14_OP_EN_SHIFT); + buf_write_field(PMIC_RG_LDO_VRFCK_CON0, 0x0, + PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT); + buf_write_field(PMIC_RG_LDO_VBBCK_CON0, 0x0, + PMIC_RG_LDO_VBBCK_EN_MASK, PMIC_RG_LDO_VBBCK_EN_SHIFT); + +#endif + +#if 0 + /* Setup initial PMIC clock buffer setting */ + /* 1.1 Buffer de-sense setting */ + /* FIXME: read dts and set to SRSEL and HD */ + buf_write_field(PMIC_RG_DCXO_CW13, PMIC_CLK_BUF2_CONTROLS_FOR_DESENSE, + 0x7, 0); + buf_write_field(PMIC_RG_DCXO_CW13, PMIC_CLK_BUF3_CONTROLS_FOR_DESENSE, + 0x3, 10); + buf_write_field(PMIC_RG_DCXO_CW13, PMIC_CLK_BUF4_CONTROLS_FOR_DESENSE, + 0x7, 4); +#endif + +#if 0 + /* 1.2 Buffer setting for trace impedance */ + /* FIXME: read dts and set to RSEL */ + buf_write_field(PMIC_RG_DCXO_CW19, PMIC_CLK_BUF1_OUTPUT_IMPEDANCE, + 0x7, 1); + buf_write_field(PMIC_RG_XO_EXTBUF2_RSEL_ADDR, PMIC_CLK_BUF2_OUTPUT_IMPEDANCE, + PMIC_RG_XO_EXTBUF2_RSEL_MASK, PMIC_RG_XO_EXTBUF2_RSEL_SHIFT); + buf_write_field(PMIC_RG_XO_EXTBUF3_RSEL_ADDR, PMIC_CLK_BUF3_OUTPUT_IMPEDANCE, + PMIC_RG_XO_EXTBUF3_RSEL_MASK, PMIC_RG_XO_EXTBUF3_RSEL_SHIFT); + buf_write_field(PMIC_RG_XO_EXTBUF4_RSEL_ADDR, PMIC_CLK_BUF4_OUTPUT_IMPEDANCE, + PMIC_RG_XO_EXTBUF4_RSEL_MASK, PMIC_RG_XO_EXTBUF4_RSEL_SHIFT); + buf_write_field(PMIC_RG_XO_EXTBUF7_RSEL_ADDR, PMIC_CLK_BUF7_OUTPUT_IMPEDANCE, + PMIC_RG_XO_EXTBUF7_RSEL_MASK, PMIC_RG_XO_EXTBUF7_RSEL_SHIFT); +#endif + + /* 1.4 26M enable control */ +#ifndef MTK_SRCLKEN_RC_SUPPORT + + /*Legacy co-clock mode */ +#ifdef CLKBUF_CONN_SUPPORT_CTRL_FROM_I1 + buf_write_field(PMIC_RG_DCXO_CW12, 0x1, 0x1, 12); +#else + buf_write_field(PMIC_RG_TOP_SPI_CON1, 0, 0x1, 0); +#endif + + buf_write_field(PMIC_RG_DCXO_CW00, PMIC_CW00_INIT_VAL, 0xFFFF, 0); + buf_write_field(PMIC_RG_DCXO_CW09, PMIC_CW09_INIT_VAL, 0xFFFF, 0); + +#else /* MTK_SRCLKEN_RC_SUPPORT */ + +#if MTK_SRCLKEN_RC_FULL_SET + + /* fully new co-clock mode */ + + /* All XO mode should set to 2'b01 */ + buf_write_field(PMIC_RG_DCXO_CW00, PMIC_CW00_INIT_VAL, 0xFFFF, 0); + buf_info("part2.1 done\n"); + buf_write_field(PMIC_RG_DCXO_CW09, PMIC_CW09_INIT_VAL, 0xFFFF, 0); + buf_info("part2.2 done\n"); + + /* 1.update control mapping table */ + /* + * XO_SOC_VOTE=11'h005 + */ + buf_write_field(PMIC_RG_XO_BUF_CTL0, 0x005, 0x7FF, 0); + + /* 2.switch to new control mode */ + /* + * XO_PMIC_TOP_DIG_SW=0 + * XO_MODE_CONN_BT_MASK=0 (BTonly : 1) + * XO_BUF_CONN_BT_MASK=0 (BTonly : 1 ) + */ + buf_write_field(PMIC_RG_DCXO_CW08, 0x0, + 0x1, 2); + buf_info("part2.3 done\n"); + buf_write_field(PMIC_RG_XO_CONN_BT0, 0x0, + 0x1, 0); + buf_info("part2.4 done\n"); + buf_write_field(PMIC_RG_XO_CONN_BT0, 0x0, + 0x1, 1); + buf_info("part2.5 done\n"); + +#endif +#endif /* MTK_SRCLKEN_RC_SUPPORT */ + + /* Check if the setting is ok */ + clk_buf_dump_clkbuf_log(); +} + +static void clk_buf_init_pmic_wrap(void) +{ +#if 0 + /* Setup PMIC_WRAP setting for XO2 & XO3 */ + if (CLK_BUF2_STATUS_PMIC != CLOCK_BUFFER_DISABLE) { +#ifdef CLKBUF_CONN_SUPPORT_CTRL_FROM_I1 + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_ADDR0, PMIC_DCXO_CW00_CLR_ADDR | (PMIC_DCXO_CW00_SET_ADDR << DCXO_CMD_ADDR0_1_SHFT)); + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_WDATA0, (PMIC_XO_EXTBUF2_EN_M_MASK << PMIC_XO_EXTBUF2_EN_M_SHIFT) + | (PMIC_XO_EXTBUF2_EN_M_MASK << PMIC_XO_EXTBUF2_EN_M_SHIFT) << DCXO_CMD_WDATA0_1_SHFT ); +#else + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_ADDR0, PMIC_RG_SRCLKEN_IN3_EN_ADDR | (PMIC_RG_SRCLKEN_IN3_EN_ADDR << DCXO_CMD_ADDR0_1_SHFT)); + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_WDATA0, (0 << PMIC_RG_SRCLKEN_IN3_EN_SHIFT) + | (1 << PMIC_RG_SRCLKEN_IN3_EN_SHIFT) << DCXO_CMD_WDATA0_1_SHFT ); +#endif + } + + if (CLK_BUF3_STATUS_PMIC != CLOCK_BUFFER_DISABLE) { + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_ADDR1, PMIC_DCXO_CW00_CLR_ADDR | (PMIC_DCXO_CW00_SET_ADDR << DCXO_CMD_ADDR0_1_SHFT)); + clkbuf_writel_ap(PMIFSPI_DCXO_CMD_WDATA1, (PMIC_XO_EXTBUF3_EN_M_MASK << PMIC_XO_EXTBUF3_EN_M_SHIFT) + | (PMIC_XO_EXTBUF3_EN_M_MASK << PMIC_XO_EXTBUF3_EN_M_SHIFT) << DCXO_CMD_WDATA0_1_SHFT ); + } + + buf_info("DCXO_CMD_ADR0/WDATA0=0x%x/%x\n", + clkbuf_readl_ap(PMIFSPI_DCXO_CMD_ADDR0), + clkbuf_readl_ap(PMIFSPI_DCXO_CMD_WDATA0)); + buf_info("DCXO_CMD_ADR1/WDATA1=0x%x/%x\n", + clkbuf_readl_ap(PMIFSPI_DCXO_CMD_ADDR1), + clkbuf_readl_ap(PMIFSPI_DCXO_CMD_WDATA1)); +#endif +} + +int clk_buf_init(void) +{ + clk_buf_init_pmic_clkbuf(); + clk_buf_init_pmic_wrap(); + + return 0; +} + diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 85eac5b..3266a3a 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -20,6 +20,8 @@ INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, + RC_BASE = IO_PHYS + 0x00006500, + RC_STATUS_BASE = IO_PHYS + 0x00006E00, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, diff --git a/src/soc/mediatek/mt8192/include/soc/clkbuf.h b/src/soc/mediatek/mt8192/include/soc/clkbuf.h new file mode 100644 index 0000000..2facd3e --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/clkbuf.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_MEDIATEK_MT8192_CLKBUF_H +#define SOC_MEDIATEK_MT8192_CLKBUF_H + +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW08 = 0x079C, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW09_CLR = 0x07A2, + PMIC_RG_DCXO_CW10 = 0x07A4, + PMIC_RG_DCXO_CW12 = 0x07A8, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW19 = 0x07B6, +}; + + +enum { + PMIC_TOP_TMA_KEY = 0x3A8, + PMIC_RG_TOP_SPI_CON1 = 0x458, +}; + +enum { + PMIC_RG_LDO_VRFCK_ELR = 0x1b40, + PMIC_RG_LDO_VRFCK_CON0 = 0x1D1C, + PMIC_RG_LDO_VRFCK_OP_EN = 0x1D22, + PMIC_RG_LDO_VRFCK_OP_EN_SET = 0x1D24, + PMIC_RG_LDO_VBBCK_CON0 = 0x1D2E, + PMIC_RG_LDO_VBBCK_OP_EN = 0x1D34, + PMIC_RG_LDO_VBBCK_OP_EN_SET = 0x1D36, +}; + +enum { + PMIC_RG_DCXO_ADLDO_BIAS_ELR_0 = 0x209C, + PMIC_RG_DCXO_ADLDO_BIAS_ELR_1 = 0x209E, +}; + +enum { + PMIC_RG_XO_BUF_CTL0 = 0x54C, + PMIC_RG_XO_CONN_BT0 = 0x556, +}; + +#define PMIC_RG_VRFCK_HV_EN_MASK 0x1 +#define PMIC_RG_VRFCK_HV_EN_SHIFT 9 +#define PMIC_RG_LDO_VRFCK_EN_MASK 0x1 +#define PMIC_RG_LDO_VRFCK_EN_SHIFT 0 +#define PMIC_RG_LDO_VRFCK_ANA_SEL_MASK 0x1 +#define PMIC_RG_LDO_VRFCK_ANA_SEL_SHIFT 0 +#define PMIC_RG_LDO_VBBCK_EN_MASK 0x1 +#define PMIC_RG_LDO_VBBCK_EN_SHIFT 0 +#define PMIC_RG_VRFCK_NDIS_EN_MASK 0x1 +#define PMIC_RG_VRFCK_NDIS_EN_SHIFT 11 +#define PMIC_RG_VRFCK_1_NDIS_EN_MASK 0x1 +#define PMIC_RG_VRFCK_1_NDIS_EN_SHIFT 0 +#define PMIC_RG_LDO_VRFCK_HW14_OP_EN_MASK 0x1 +#define PMIC_RG_LDO_VRFCK_HW14_OP_EN_SHIFT 14 +#define PMIC_RG_LDO_VBBCK_HW14_OP_EN_MASK 0x1 +#define PMIC_RG_LDO_VBBCK_HW14_OP_EN_SHIFT 14 + +int clk_buf_init(void); + +#endif + diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h index 6106a3d..71f3724 100644 --- a/src/soc/mediatek/mt8192/include/soc/pmif.h +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -154,7 +154,48 @@ E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ }; +enum pmic_interface { + PMIF_VLD_RDY = 0, + PMIF_SLP_REQ, + PMIF_MAX, +}; + +#define PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPI_OTHER_INF_DXCO0_EN_MSK 0x1 +#define PMIFSPI_OTHER_INF_DXCO0_EN_SHFT 0 +#define PMIFSPI_OTHER_INF_DXCO1_EN_MSK 0x1 +#define PMIFSPI_OTHER_INF_DXCO1_EN_SHFT 1 +#define PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPI_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPI_ARB_EN_DCXO_CONN_SHFT 15 +#define PMIFSPI_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPI_ARB_EN_DCXO_NFC_SHFT 16 +#define PMIFSPI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT 9 +#define PMIFSPI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPI_MD_CTL_PMIF_RDY_SHFT 11 +#define PMIFSPI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPI_MD_CTL_SRCLK_EN_SHFT 12 +#define PMIFSPI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPI_MD_CTL_SRVOL_EN_SHFT 13 + +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT 9 +#define PMIFSPMI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI_MD_CTL_PMIF_RDY_SHFT 11 +#define PMIFSPMI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRCLK_EN_SHFT 12 +#define PMIFSPMI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRVOL_EN_SHFT 13 + /* start external API */ extern struct pmif *get_pmif_controller(int inf, int mstid); +extern void pmwrap_interface_init(void); extern int mtk_pmif_init(void); #endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h index bad7c68..4ec7475 100755 --- a/src/soc/mediatek/mt8192/include/soc/rtc.h +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -159,6 +159,7 @@ PMIC_RG_BANK_FQMTR_RST_SHIFT = 6 }; +#if 0 /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, @@ -171,6 +172,7 @@ PMIC_RG_DCXO_CW09_CLR = 0x07A2, PMIC_RG_DCXO_CW12 = 0x07A8 }; +#endif /* PMIC Frequency Meter Definition */ enum { diff --git a/src/soc/mediatek/mt8192/include/soc/srclken_rc.h b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h new file mode 100644 index 0000000..0ed4da9 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h @@ -0,0 +1,425 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_MEDIATEK_MT8192_SRCLKEN_RC_H +#define SOC_MEDIATEK_MT8192_SRCLKEN_RC_H + +//#include <soc/addressmap.h> + +struct mtk_rc_regs { + u32 srclken_rc_cfg; + u32 rc_central_cfg1; + u32 rc_central_cfg2; + u32 rc_cmd_arb_cfg; + u32 rc_pmic_rcen_addr; + u32 rc_pmic_rcen_set_clr_addr; + u32 rc_dcxo_fpm_cfg; + u32 rc_central_cfg3; + u32 rc_mxx_srclken_cfg[13]; + u32 srclken_sw_con_cfg; + u32 rc_central_cfg4; + u32 reserved1; + u32 rc_protocol_chk_cfg; + u32 rc_debug_cfg; + u32 reserved2[19]; + u32 rc_misc_0; + u32 rc_spm_ctrl; + u32 rc_subsys_intf_cfg; +}; + +check_member(mtk_rc_regs, rc_central_cfg1, 0x4); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[0], 0x20); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[12], 0x50); +check_member(mtk_rc_regs, rc_central_cfg4, 0x58); +check_member(mtk_rc_regs, rc_protocol_chk_cfg, 0x60); +check_member(mtk_rc_regs, rc_misc_0, 0xb4); +check_member(mtk_rc_regs, rc_subsys_intf_cfg, 0xbc); + +struct mtk_rc_status_regs { + u32 rc_fsm_sta_0; + u32 rc_cmd_sta_0; + u32 rc_cmd_sta_1; + u32 rc_spi_sta_0; + u32 rc_pi_po_sta_0; + u32 rc_mxx_req_sta_0[14]; + u32 reserved2[2]; + u32 rc_debug_trace; +}; + +check_member(mtk_rc_status_regs, rc_cmd_sta_1, 0x8); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[0], 0x14); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[13], 0x48); +check_member(mtk_rc_status_regs, rc_debug_trace, 0x54); + +/* + * Definitions + */ + +#define MTK_SRCLKEN_RC_BRINGUP (0) +#define MTK_SRCLKEN_RC_SUPPORT +#ifdef MTK_SRCLKEN_RC_SUPPORT +#define MTK_SRCLKEN_RC_FULL_SET (1) +#endif +#define SRCLKEN_DBG (1) + + +//#define AP_BASE (0x1000C000) +//#define SPM_BASE (0x10006000) +//#define RC_BASE (0x10006500) +//#define RC_STATE_BASE (0x10006E00) +//#define PMIF_SPI_BASE (0x10026000) +//#define PMIF_SPMI_BASE (0x10027000) + +#if 0 +/* PMIF Register*/ +#define PMIFSPI_INF_EN (PMIF_SPI_BASE + 0x0024) +#define PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPI_OTHER_INF_EN (PMIF_SPI_BASE + 0x0028) +#define PMIFSPI_OTHER_INF_DXCO0_EN_MSK 0x1 +#define PMIFSPI_OTHER_INF_DXCO0_EN_SHFT 0 +#define PMIFSPI_OTHER_INF_DXCO1_EN_MSK 0x1 +#define PMIFSPI_OTHER_INF_DXCO1_EN_SHFT 1 + +#define PMIFSPI_DCXO_CMD_ADDR0 (PMIF_SPI_BASE + 0x005C) +#define DCXO_CMD_ADDR0_0_MSK 0xffff +#define DCXO_CMD_ADDR0_0_SHFT 0 +#define DCXO_CMD_ADDR0_1_MSK 0xffff +#define DCXO_CMD_ADDR0_1_SHFT 16 + +#define PMIFSPI_DCXO_CMD_WDATA0 (PMIF_SPI_BASE + 0x0060) +#define DCXO_CMD_WDATA0_0_MSK 0xffff +#define DCXO_CMD_WDATA0_0_SHFT 0 +#define DCXO_CMD_WDATA0_1_MSK 0xffff +#define DCXO_CMD_WDATA0_1_SHFT 16 + +#define PMIFSPI_DCXO_CMD_ADDR1 (PMIF_SPI_BASE + 0x0064) +#define DCXO_CMD_ADDR1_0_MSK 0xffff +#define DCXO_CMD_ADDR1_0_SHFT 0 +#define DCXO_CMD_ADDR1_1_MSK 0xffff +#define DCXO_CMD_ADDR1_1_SHFT 16 + +#define PMIFSPI_DCXO_CMD_WDATA1 (PMIF_SPI_BASE + 0x0068) +#define DCXO_CMD_WDATA1_0_MSK 0xffff +#define DCXO_CMD_WDATA1_0_SHFT 0 +#define DCXO_CMD_WDATA1_1_MSK 0xffff +#define DCXO_CMD_WDATA1_1_SHFT 16 + +#define PMIFSPI_ARB_EN (PMIF_SPI_BASE + 0x0150) +#define PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPI_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPI_ARB_EN_DCXO_CONN_SHFT 15 +#define PMIFSPI_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPI_ARB_EN_DCXO_NFC_SHFT 16 + +#define PMIFSPI_SLEEP_PROTECTION_CRL (PMIF_SPI_BASE + 0x03E8) +#define PMIFSPI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPI_MODE_CRL (PMIF_SPI_BASE + 0x0400) +#define PMIFSPI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPI_MD_CTL_PMIF_RDY_SHFT 11 +#define PMIFSPI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPI_MD_CTL_SRCLK_EN_SHFT 12 +#define PMIFSPI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPI_MD_CTL_SRVOL_EN_SHFT 13 + +#define PMIFSPMI_SLEEP_PROTECTION_CRL (PMIF_SPMI_BASE + 0x03E8) +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI_MODE_CRL (PMIF_SPMI_BASE + 0x0400) +#define PMIFSPMI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI_MD_CTL_PMIF_RDY_SHFT 11 +#define PMIFSPMI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRCLK_EN_SHFT 12 +#define PMIFSPMI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRVOL_EN_SHFT 13 +#endif + +/* SPM Register */ +#define ULPOSC_CON (SPM_BASE + 0x0440) +#define ULPOSC_EN_SHFT 0 +#define ULPOSC_RST_SHFT 1 +#define ULPOSC_CG_EN_SHFT 2 +#define ULPOSC_CLK_SEL_SHFT 3 + +#define SRCLKEN_RC_CFG (RC_BASE + 0x0000) +#define SW_RESET_MSK 0x1 +#define SW_RESET_SHFT 0 +#define CG_32K_EN_MSK 0x1 +#define CG_32K_EN_SHFT 1 +#define CG_FCLK_EN_MSK 0x1 +#define CG_FCLK_EN_SHFT 2 +#define CG_FCLK_FR_EN_MSK 0x1 +#define CG_FCLK_FR_EN_SHFT 3 +#define MUX_FCLK_FR_MSK 0x1 +#define MUX_FCLK_FR_SHFT 4 +#define RC_32K_DCM_MSK 0x1 +#define RC_32K_DCM_SHFT 8 + + +#define RC_CENTRAL_CFG1 (RC_BASE + 0x0004) +#define SRCLKEN_RC_EN_MSK 0x1 +#define SRCLKEN_RC_EN_SHFT 0 +#define RCEN_ISSUE_M_MSK 0x1 +#define RCEN_ISSUE_M_SHFT 1 +#define RC_SPI_ACTIVE_MSK 0x1 +#define RC_SPI_ACTIVE_SHFT 2 +#define SRCLKEN_RC_EN_SEL_MSK 0x1 +#define SRCLKEN_RC_EN_SEL_SHFT 3 +#define VCORE_SETTLE_T_MSK 0x7 +#define VCORE_SETTLE_T_SHFT 5 +#define ULPOSC_SETTLE_T_MSK 0xf +#define ULPOSC_SETTLE_T_SHFT 8 +#define NON_DCXO_SETTLE_T_MSK 0x3ff +#define NON_DCXO_SETTLE_T_SHFT 12 +#define DCXO_SETTLE_T_MSK 0x3ff +#define DCXO_SETTLE_T_SHFT 22 + +#define RC_CENTRAL_CFG2 (RC_BASE + 0x0008) +#define SRCVOLTEN_CTRL_MSK 0xf +#define SRCVOLTEN_CTRL_SHFT 0 +#define VREQ_CTRL_MSK 0xf +#define VREQ_CTRL_SHFT 4 +#define SRCVOLTEN_VREQ_SEL_MSK 0x1 +#define SRCVOLTEN_VREQ_SEL_SHFT 8 +#define SRCVOLTEN_VREQ_M_MSK 0x1 +#define SRCVOLTEN_VREQ_M_SHFT 9 +#define FORCE_SRCVOLTEN_OFF_MSK 0x1 +#define FORCE_SRCVOLTEN_OFF_SHFT 10 +#define FORCE_SRCVOLTEN_ON_MSK 0x1 +#define FORCE_SRCVOLTEN_ON_SHFT 11 +#define ULPOSC_CTRL_M_MSK 0xf +#define ULPOSC_CTRL_M_SHFT 12 +#define FORCE_VCORE_RDY_MSK 0x1 +#define FORCE_VCORE_RDY_SHFT 16 +#define FORCE_ULPOSC2ON_MSK 0x1 +#define FORCE_ULPOSC2ON_SHFT 17 +#define FORCE_ULPOSC_CLK_EN_MSK 0x1 +#define FORCE_ULPOSC_CLK_EN_SHFT 18 +#define FORCE_ULPOSC_ON_MSK 0x1 +#define FORCE_ULPOSC_ON_SHFT 19 +#define DIS_ULPOSC_RDY_CHK_MSK 0x1 +#define DIS_ULPOSC_RDY_CHK_SHFT 20 +#define PWRAP_SLP_CTRL_M_MSK 0xf +#define PWRAP_SLP_CTRL_M_SHFT 21 +#define PWRAP_SLP_MUX_SEL_MSK 0x1 +#define PWRAP_SLP_MUX_SEL_SHFT 25 +#define FORCE_PWRAP_ON_MSK 0x1 +#define FORCE_PWRAP_ON_SHFT 26 +#define FORCE_PWRAP_AWK_MSK 0x1 +#define FORCE_PWRAP_AWK_SHFT 27 +#define NON_DCXO_REQ_FORCEON_MSK 0x1 +#define NON_DCXO_REQ_FORCEON_SHFT 28 +#define NON_DCXO_REQ_FORCEOFF_MSK 0x1 +#define NON_DCXO_REQ_FORCEOFF_SHFT 29 +#define DCXO_REQ_FORCEON_MSK 0x1 +#define DCXO_REQ_FORCEON_SHFT 30 +#define DCXO_REQ_FORCEOFF_MSK 0x1 +#define DCXO_REQ_FORCEOFF_SHFT 31 + +#define RC_CMD_ARB_CFG (RC_BASE + 0x000C) +#define SW_RC_EN_MSK 0x1fff +#define SW_RC_EN_SHFT 0 +#define SW_RCEN_EN_MSK 0x1fff +#define SW_RCEN_EN_SHFT 13 +#define SW_DCXO_M_EN_MSK 0x1 +#define SW_DCXO_M_EN_SHFT 28 +#define SW_DCXO_M_MSK 0x7 +#define SW_DCXO_M_SHFT 29 + +#define RC_PMIC_RCEN_ADDR (RC_BASE + 0x0010) +#define RC_PMIC_RCEN_SET_CLR_ADDR (RC_BASE + 0x0014) +#define RC_DCXO_FPM_CFG (RC_BASE + 0x0018) +#define DCXO_FPM_CTRL_M_MSK 0xf +#define DCXO_FPM_CTRL_M_SHFT 0 +#define SRCVOLTEN_FPM_MSK_B_MSK 0x1 +#define SRCVOLTEN_FPM_MSK_B_SHFT 4 +#define SUB_SRCLKEN_FPM_MSK_B_MSK 0x1fff +#define SUB_SRCLKEN_FPM_MSK_B_SHFT 16 + +#define RC_CENTRAL_CFG3 (RC_BASE + 0x001C) +#define TO_LPM_SETTLE_EN_MSK 0x1 +#define TO_LPM_SETTLE_EN_SHFT 0 +#define BLK_SCP_DXCO_MD_TARGET_MSK 0x1 +#define BLK_SCP_DXCO_MD_TARGET_SHFT 1 +#define BLK_COANT_DXCO_MD_TARGET_MSK 0x1 +#define BLK_COANT_DXCO_MD_TARGET_SHFT 2 +#define TO_BBLPM_SETTLE_EN_MSK 0x1 +#define TO_BBLPM_SETTLE_EN_SHFT 0x3 +#define TO_BBLPM_SETTLE_ND_EN_MSK 0x1 +#define TO_BBLPM_SETTLE_ND_EN_SHFT 0x4 +#define TO_LPM_SETTLE_T_MSK 0x2ff +#define TO_LPM_SETTLE_T_SHFT 12 + +#define RC_MXX_SRCLKEN_CFG (RC_BASE + 0x0020) +#define DCXO_SETTLE_BLK_EN_MSK 0x1 +#define DCXO_SETTLE_BLK_EN_SHFT 1 +#define BYPASS_CMD_EN_MSK 0x1 +#define BYPASS_CMD_EN_SHFT 2 +#define SW_SRCLKEN_RC_MSK 0x1 +#define SW_SRCLKEN_RC_SHFT 3 +#define SW_SRCLKEN_FPM_MSK 0x1 +#define SW_SRCLKEN_FPM_SHFT 4 +#define SW_SRCLKEN_BBLPM_MSK 0x1 +#define SW_SRCLKEN_BBLPM_SHFT 5 +#define XO_SOC_LINK_EN_MSK 0x1 +#define XO_SOC_LINK_EN_SHFT 6 +#define REQ_ACK_LOW_IMD_EN_MSK 0x1 +#define REQ_ACK_LOW_IMD_EN_SHFT 7 +#define SRCLKEN_TRACK_M_EN_MSK 0x1 +#define SRCLKEN_TRACK_M_EN_SHFT 8 +#define CNT_PRD_STEP_MSK 0x3 +#define CNT_PRD_STEP_SHFT 10 +#define XO_STABLE_PRD_MSK 0x3ff +#define XO_STABLE_PRD_SHFT 12 +#define DCXO_STABLE_PRD_MSK 0x3ff +#define DCXO_STABLE_PRD_SHFT 22 + +#define RC_DEBUG_TRACE (RC_BASE + 0x0054) +#define TACE_EN_MSK 0x1 +#define TACE_EN_SHFT 0 + +#define RC_CENTRAL_CFG4 (RC_BASE + 0x0058) +#define KEEP_RC_SPI_ACTIVE_MSK 0x1ff +#define KEEP_RC_SPI_ACTIVE_SHFT 0 +#define PWRAP_VLD_FORCE_MAK 0x1 +#define PWRAP_VLD_FORCE_SHFT 16 +#define SLEEP_VLD_MODE_MAK 0x1 +#define SLEEP_VLD_MODE_SHFT 17 +#define SCP_SLEEP_REQ_MODE_MAK 0x1 +#define SCP_SLEEP_REQ_MODE_SHFT 18 +#define SLEEP_REQ_MODE_MSK 0x1 +#define SLEEP_REQ_MODE_SHFT 20 + +#define RC_DEBUG_CFG (RC_BASE + 0x0064) +#define TRACE_MODE_EN_MSK 0x1 +#define TRACE_MODE_EN_SHFT 24 +#define DBG_STOP_PROT_EN_MSK 0x1 +#define DBG_STOP_PROT_EN_SHFT 28 + +#define SUBSYS_INTF_CFG (RC_BASE + 0x00BC) +#define SRCLKEN_FPM_MASK_B_MSK 0x1fff +#define SRCLKEN_FPM_MASK_B_SHFT 0 +#define SRCLKEN_BBLPM_MASK_B_MSK 0x1fff +#define SRCLKEN_BBLPM_MASK_B_SHFT 16 + +#define RC_PI_PO_STA (RC_STATUS_BASE + 0x0010) +#define RC_MXX_REQ_STA_0 (RC_STATUS_BASE + 0x0014) +#define FPM_ACK_MSK 0x1 +#define FPM_ACK_SHFT 1 +#define BBLPM_ACK_MSK 0x1 +#define BBLPM_ACK_SHFT 3 + +#define RC_SPI_STA_0 (RC_STATUS_BASE + 0x000C) + +/*#define TEST_UFS (UFS_HCI_BASE + 0x0144)*/ + +enum { + PMIC_PMRC_CON0 = 0x1A6, +}; + +typedef struct { + u32 osc_div; + u32 cali_val; +} ulposc_con_t; + +enum { + ULPOSC_DIV_1 = 0, + ULPOSC_DIV_4 = 1 +}; + +enum chn_id { + CHN_SUSPEND = 0, + CHN_RF = 1, + CHN_DEEPIDLE = 2, + CHN_MD= 3, + CHN_GPS = 4, + CHN_BT = 5, + CHN_WIFI = 6, + CHN_MCU = 7, + CHN_COANT = 8, + CHN_NFC = 9, + CHN_UFS = 10, + CHN_SCP = 11, + CHN_RESERVE = 12, + MAX_CHN_NUM, +}; + +enum { + SRCLKENAO_MODE, + VREQ_MODE, +}; + +enum { + MERGE_OR_MODE = 0x0, + BYPASS_MODE = 0x1, + MERGE_AND_MODE = 0x1 << 1, + BYPASS_RC_MODE = 0x2 << 1, + BYPASS_OTHER_MODE = 0x3 << 1, + ASYNC_MODE = 0x1 << 3, +}; + +enum { + RC_32K = 0, + RC_ULPOSC1, +}; + +enum rc_ctrl_m { + HW_MODE = 0, + SW_MODE = 1, + INIT_MODE = 0xff, +}; + +enum rc_ctrl_r { + NO_REQ = 0, + FPM_REQ = 1 << SW_SRCLKEN_FPM_SHFT, + BBLPM_REQ = 1 << SW_SRCLKEN_BBLPM_SHFT, +}; + +enum { + SRLCKEN_RC_BRINGUP = 0, + SRCLKEN_RC_DISABLE, + SRCLKEN_RC_ENABLE, + SRCLKEN_RC_SKIP, +}; + +struct subsys_rc_con { + enum chn_id id; + unsigned int dcxo_prd; + unsigned int xo_prd; + unsigned int cnt_step; + unsigned int track_en; + unsigned int req_ack_imd_en; + unsigned int xo_soc_link_en; + unsigned int sw_bblpm; + unsigned int sw_fpm; + unsigned int sw_rc; + unsigned int bypass_cmd; + unsigned int dcxo_settle_blk_en; +}; + +#define RC_SUBSYS_SET(_dcxo_prd, _xo_prd, _cnt_step, _track_en, \ + _req_ack_imd_en, _xo_soc_link_en, _sw_bblpm, \ + _sw_fpm, _sw_rc, _bypass_settle) { \ + .dcxo_prd = _dcxo_prd, \ + .xo_prd = _xo_prd, \ + .cnt_step = _cnt_step, \ + .track_en = _track_en, \ + .req_ack_imd_en = _req_ack_imd_en, \ + .xo_soc_link_en = _xo_soc_link_en, \ + .sw_bblpm = _sw_bblpm, \ + .sw_fpm = _sw_fpm, \ + .sw_rc = _sw_rc, \ + .bypass_settle = _bypass_settle, \ + } + +//extern void rc_ctrl_mode_switch_hw(enum chn_id id); +//extern void rc_ctrl_mode_switch_sw(enum chn_id id); +extern int srclken_rc_init(void); +#endif diff --git a/src/soc/mediatek/mt8192/pmif.c b/src/soc/mediatek/mt8192/pmif.c index 295deaf..c7d325b 100644 --- a/src/soc/mediatek/mt8192/pmif.c +++ b/src/soc/mediatek/mt8192/pmif.c @@ -156,6 +156,134 @@ return NULL; } +static void pmif_select(enum pmic_interface mode) +{ + unsigned int spi_sleep_ctrl, spmi_sleep_ctrl; + unsigned int spi_mode_ctrl, spmi_mode_ctrl; + unsigned int inf_en, other_inf_en, arb_en; + + spi_sleep_ctrl = read32(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl); + spmi_sleep_ctrl = read32(&pmif_spmi_arb[0].mtk_pmif->sleep_protection_ctrl); + spi_mode_ctrl = read32(&pmif_spi_arb[0].mtk_pmif->spi_mode_ctrl); + spmi_mode_ctrl = read32(&pmif_spmi_arb[0].mtk_pmif->spi_mode_ctrl); + inf_en = read32(&pmif_spi_arb[0].mtk_pmif->inf_en); + other_inf_en = read32(&pmif_spi_arb[0].mtk_pmif->other_inf_en); + arb_en = read32(&pmif_spi_arb[0].mtk_pmif->arb_en); + + if(PMIF_VLD_RDY == mode){ + /* spm and scp sleep request disable spi and spmi */ + spi_sleep_ctrl = (spi_sleep_ctrl & ~(PMIFSPI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT)) + | (0x1 << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT); + spi_sleep_ctrl = (spi_sleep_ctrl & ~(PMIFSPI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT)) + | (0x1 << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT); + + spmi_sleep_ctrl = (spmi_sleep_ctrl & ~(PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT)) + | (0x1 << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT); + spmi_sleep_ctrl = (spmi_sleep_ctrl & ~(PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT)) + | (0x1 << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT); + /* pmic vld/rdy control spi mode enable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_PMIF_RDY_MSK << PMIFSPI_MD_CTL_PMIF_RDY_SHFT)) + | (0x1 << PMIFSPI_MD_CTL_PMIF_RDY_SHFT); + /* srclken control spi mode disable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_SRCLK_EN_MSK << PMIFSPI_MD_CTL_SRCLK_EN_SHFT)) + | (0x0 << PMIFSPI_MD_CTL_SRCLK_EN_SHFT); + /* vreq control spi mode disable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_SRVOL_EN_MSK << PMIFSPI_MD_CTL_SRVOL_EN_SHFT)) + | (0x0 << PMIFSPI_MD_CTL_SRVOL_EN_SHFT); + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_PMIF_RDY_MSK << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT)) + | (0x1 << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT); + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_SRCLK_EN_MSK << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT)) + | (0x0 << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT); + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_SRVOL_EN_MSK << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT)) + | (0x0 << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT); + + /* srclken rc interface enable*/ + inf_en = (inf_en & ~(PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT)) + | (0x1 << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT); + + /* dcxo interface disable */ + other_inf_en = (other_inf_en & ~(PMIFSPI_OTHER_INF_DXCO0_EN_MSK << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT)) + | (0x0 << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT); + other_inf_en = (other_inf_en & ~(PMIFSPI_OTHER_INF_DXCO1_EN_MSK << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT)) + | (0x0 << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT); + /*srclken enable, dcxo0,1 disable*/ + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT)) + | (0x1 << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT); + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_CONN_MSK << PMIFSPI_ARB_EN_DCXO_CONN_SHFT)) + | (0x0 << PMIFSPI_ARB_EN_DCXO_CONN_SHFT); + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_NFC_MSK << PMIFSPI_ARB_EN_DCXO_NFC_SHFT)) + | (0x0 << PMIFSPI_ARB_EN_DCXO_NFC_SHFT); + + } else if (PMIF_SLP_REQ == mode) { + + /* spm and scp sleep request enable spi and spmi */ + spi_sleep_ctrl = (spi_sleep_ctrl & ~(PMIFSPI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT)) + | (0x0 << PMIFSPI_SPM_SLEEP_REQ_SEL_SHFT); + spi_sleep_ctrl = (spi_sleep_ctrl & ~(PMIFSPI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT)) + | (0x0 << PMIFSPI_SCP_SLEEP_REQ_SEL_SHFT); + + spmi_sleep_ctrl = (spmi_sleep_ctrl & ~(PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT)) + | (0x0 << PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT); + spmi_sleep_ctrl = (spmi_sleep_ctrl & ~(PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT)) + | (0x0 << PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT); + + /* pmic vld/rdy control spi mode disable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_PMIF_RDY_MSK << PMIFSPI_MD_CTL_PMIF_RDY_SHFT)) + | (0x0 << PMIFSPI_MD_CTL_PMIF_RDY_SHFT); + /* srclken control spi mode enable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_SRCLK_EN_MSK << PMIFSPI_MD_CTL_SRCLK_EN_SHFT)) + | (0x1 << PMIFSPI_MD_CTL_SRCLK_EN_SHFT); + /* vreq control spi mode enable*/ + spi_mode_ctrl = (spi_mode_ctrl & ~(PMIFSPI_MD_CTL_SRVOL_EN_MSK << PMIFSPI_MD_CTL_SRVOL_EN_SHFT)) + | (0x1 << PMIFSPI_MD_CTL_SRVOL_EN_SHFT); + + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_PMIF_RDY_MSK << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT)) + | (0x0 << PMIFSPMI_MD_CTL_PMIF_RDY_SHFT); + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_SRCLK_EN_MSK << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT)) + | (0x1 << PMIFSPMI_MD_CTL_SRCLK_EN_SHFT); + spmi_mode_ctrl = (spmi_mode_ctrl & ~(PMIFSPMI_MD_CTL_SRVOL_EN_MSK << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT)) + | (0x1 << PMIFSPMI_MD_CTL_SRVOL_EN_SHFT); + + /* srclken rc interface disable*/ + inf_en = (inf_en & ~(PMIFSPI_INF_EN_SRCLKEN_RC_HW_MSK << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT)) + | (0x0 << PMIFSPI_INF_EN_SRCLKEN_RC_HW_SHFT); + /* dcxo interface enable */ + other_inf_en = (other_inf_en & ~(PMIFSPI_OTHER_INF_DXCO0_EN_MSK << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT)) + | (0x1 << PMIFSPI_OTHER_INF_DXCO0_EN_SHFT); + other_inf_en = (other_inf_en & ~(PMIFSPI_OTHER_INF_DXCO1_EN_MSK << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT)) + | (0x1 << PMIFSPI_OTHER_INF_DXCO1_EN_SHFT); + + /*srclken dissable, dcxo0,1 enable*/ + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_SRCLKEN_RC_HW_MSK << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT)) + | (0x0 << PMIFSPI_ARB_EN_SRCLKEN_RC_HW_SHFT); + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_CONN_MSK << PMIFSPI_ARB_EN_DCXO_CONN_SHFT)) + | (0x1 << PMIFSPI_ARB_EN_DCXO_CONN_SHFT); + arb_en = (arb_en & ~(PMIFSPI_ARB_EN_DCXO_NFC_MSK << PMIFSPI_ARB_EN_DCXO_NFC_SHFT)) + | (0x1 << PMIFSPI_ARB_EN_DCXO_NFC_SHFT); + + } else + return; + + write32(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl, spi_sleep_ctrl); + write32(&pmif_spmi_arb[0].mtk_pmif->sleep_protection_ctrl, spmi_sleep_ctrl); + write32(&pmif_spi_arb[0].mtk_pmif->spi_mode_ctrl, spi_mode_ctrl); + write32(&pmif_spmi_arb[0].mtk_pmif->spi_mode_ctrl, spmi_mode_ctrl); + write32(&pmif_spi_arb[0].mtk_pmif->inf_en, inf_en); + write32(&pmif_spi_arb[0].mtk_pmif->other_inf_en, other_inf_en); + write32(&pmif_spi_arb[0].mtk_pmif->arb_en, arb_en); +} + +void pmwrap_interface_init(void){ + /* MTK_SRCLKEN_RC_SUPPORT */ +#if 1 + printk(BIOS_ERR, "[%s] PMIF_VLD_RDY\n", __func__); + pmif_select(PMIF_VLD_RDY); +#else + printk(BIOS_ERR, "[%s] PMIF_SLP_REQ\n", __func__); + pmic_select(PMIF_SLP_REQ); +#endif +} + int mtk_pmif_init(void) { int ret = 1; diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c index f02c633..ca817fa 100755 --- a/src/soc/mediatek/mt8192/rtc.c +++ b/src/soc/mediatek/mt8192/rtc.c @@ -14,6 +14,7 @@ */ #include <delay.h> #include <halt.h> +#include <soc/clkbuf.h> #include <soc/mt6359p.h> #include <soc/pmif.h> #include <soc/rtc_common.h> @@ -428,6 +429,7 @@ halt(); } +#if 0 static void dcxo_init(void) { u16 tmp; @@ -459,13 +461,17 @@ rtc_write_field(PMIC_RG_DCXO_CW12, 0x2, 0x3, 0); } +#endif + /* the rtc boot flow entry */ void rtc_boot(void) { u16 tmp; +#if 0 /* dcxo clock init settings */ dcxo_init(); +#endif /* dcxo 32k init settings */ rtc_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp); diff --git a/src/soc/mediatek/mt8192/srclken_rc.c b/src/soc/mediatek/mt8192/srclken_rc.c new file mode 100644 index 0000000..31a0098 --- /dev/null +++ b/src/soc/mediatek/mt8192/srclken_rc.c @@ -0,0 +1,437 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pmif.h> +#include <soc/srclken_rc.h> + +#define RCTAG "[SRCLKEN_RC]" +#define rc_info(fmt, arg ...) printk(BIOS_INFO, RCTAG "%s,%d: " fmt, \ + __func__, __LINE__, ## arg) + +/* RC settle time setting */ +/*#define NO_DCXO_XO_CHN ((1 << CHN_COANT) | (1 << CHN_SCP) | (1 << CHN_RESERVE))*/ +//#define BT_ONLY_HW_MODE ((1 << CHN_BT)) /* only BT use HW side-band signal */ +#define FULL_SET_HW_MODE 0 /* dcxo mode use pmrc_en */ +#define VCORE_SETTLE_TIME 1 /* ~= 30us */ +#define ULPOSC_SETTLE_TIME 4 /* ~= ? 150us */ +#define XO_SETTLE_TIME 0x1 /* 2^(step_sz+5) * 0x33 *30.77ns~=400us */ +#define DCXO_SETTLE_TIME 0x1 /* 2^(step_sz+5) * 0x87 *30.77ns~= 1063us */ +#define CENTROL_CNT_STEP 0x3 /* Fix in 3, central align with Mxx Channel */ +#define DCXO_STABLE_TIME 0x70 +#define XO_STABLE_TIME 0x70 +#define KEEP_RC_SPI_ACTIVE 1 +#define SRCLKEN_RC_EN_SEL 0 + +#define INIT_SUBSYS_FPM_TO_LPM ( 1 << CHN_RF | 1 << CHN_DEEPIDLE \ + | 1 << CHN_MD | 1 << CHN_GPS | 1 <<CHN_BT \ + | 1 << CHN_WIFI | 1 << CHN_MCU \ + | 1 << CHN_COANT | 1 << CHN_NFC | 1 << CHN_UFS \ + | 1 << CHN_SCP | 1 << CHN_RESERVE) + +#define INIT_SUBSYS_FPM_TO_BBLPM ( 1 << CHN_DEEPIDLE) + +#define INIT_SUBSYS_TO_HW ( 1 << CHN_SUSPEND | 1 << CHN_RF | 1 << CHN_DEEPIDLE \ + | 1 << CHN_GPS | 1 <<CHN_BT \ + | 1 << CHN_WIFI | 1 << CHN_MCU \ + | 1 << CHN_COANT | 1 << CHN_NFC ) + +/* RC central setting */ +#define RC_CENTRAL_ENABLE 1 +#define RC_CENTRAL_DISABLE 0 +#if MTK_SRCLKEN_RC_FULL_SET +#define SPI_TRIG_MODE SRCLKENAO_MODE /* use srlckenao to set vcore */ +#define IS_SPI_DONE_RELEASE 0 /* release vcore when spi request done */ +#define IS_SPI2PMIC_SET_CLR 0 /* register direct write */ +#define SRCLKENO_0_CTRL_M MERGE_OR_MODE /* merge with spm */ +#define VREQ_CTRL_M BYPASS_MODE /* merge with vreq */ +#define ULPOSC_CTRL_M BYPASS_MODE /* merge with ulposc */ +#define PWRAP_CTRL_M MERGE_OR_MODE /* merge with pwrap_scp */ +#endif +#define SPI_CLK_SRC RC_32K /* pmic spec under 200us */ + +/* other setting */ +#define PMRC_CON0 0x1A6 /* default use this reg direct write */ +#define PMRC_CON0_SET 0x1A8 +#define PMRC_CON0_CLR 0x1AA + +#define DCXO_FPM_CTRL_MODE MERGE_OR_MODE | ASYNC_MODE /* merge with spm */ + +#define PWRAP_TMOUT_VAL 0xA /* 31us * 0xa ~= 310us */ + +#if MTK_SRCLKEN_RC_FULL_SET +#define FPM_MSK_B FULL_SET_HW_MODE +#define MD0_SRCLKENO_0_MASK_B 0 /* md0 control by pmrc */ + +#define SUB_BBLPM_SET ( 1 << CHN_COANT | 1 << CHN_DEEPIDLE ) +#define SUB_FPM_SET (1 << CHN_SUSPEND | 1 << CHN_RF \ + | 1 << CHN_MD | 1 << CHN_GPS | 1 <<CHN_BT \ + | 1 << CHN_WIFI | 1 << CHN_MCU \ + | 1 << CHN_NFC | 1 << CHN_UFS | 1 << CHN_SCP \ + | 1 << CHN_RESERVE) + +#define SW_BBLPM_HIGH 1 +#define SW_BBLPM_LOW 0 +#define SW_FPM_HIGH 1 +#define SW_FPM_LOW 0 +#define DXCO_SETTLE_BLK_EN 1 +#define DXCO_SETTLE_BLK_DIS 0 + +#define SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd , _sw_bblpm, _sw_fpm, \ + _sw_rc, _bypass_cmd, _dcxo_settle_blk_en) { \ + .id = _id, \ + .dcxo_prd = _dcxo_prd, \ + .xo_prd = _xo_prd, \ + .cnt_step = CENTROL_CNT_STEP, \ + .track_en = 0x0, \ + .req_ack_imd_en = 0x1, \ + .xo_soc_link_en = 0x0, \ + .sw_bblpm = _sw_bblpm, \ + .sw_fpm = _sw_fpm, \ + .sw_rc = _sw_rc, \ + .bypass_cmd = _bypass_cmd, \ + .dcxo_settle_blk_en = _dcxo_settle_blk_en, \ + } + +static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE; +static struct mtk_rc_status_regs *rc_sta_regs = + (struct mtk_rc_status_regs *)RC_STATUS_BASE; + +static struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = { + SUB_CTRL_CON(CHN_SUSPEND, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_RF, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_DEEPIDLE, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_MD, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_GPS, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_BT, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_WIFI, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_MCU, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_COANT, 0x0, 0x0, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x1 /*bypass*/,DXCO_SETTLE_BLK_DIS), + SUB_CTRL_CON(CHN_NFC, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_UFS, DCXO_STABLE_TIME, XO_STABLE_TIME, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x0 /*bypass*/,DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON(CHN_SCP, 0x0, 0x0, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x1 /*bypass*/,DXCO_SETTLE_BLK_DIS), + SUB_CTRL_CON(CHN_RESERVE, 0x0, 0x0, SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, 0x1 /*bypass*/,DXCO_SETTLE_BLK_DIS), +}; +#endif + +static struct pmif *pmif_arb = NULL; +static s32 pmic_read(u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + return pmif_arb->read_cmd(pmif_arb, 0, addr, rdata); +} + +static void rc_dump_reg_info(void){ +#if SRCLKEN_DBG + unsigned int chn_n; + + rc_info("SRCLKEN_RC_CFG:0x%x\n", read32(&rc_regs->srclken_rc_cfg)); + rc_info("RC_CENTRAL_CFG1:0x%x\n", read32(&rc_regs->rc_central_cfg1)); + rc_info("RC_CENTRAL_CFG2:0x%x\n", read32(&rc_regs->rc_central_cfg2)); + rc_info("RC_CENTRAL_CFG3:0x%x\n", read32(&rc_regs->rc_central_cfg3)); + rc_info("RC_CENTRAL_CFG4:0x%x\n", read32(&rc_regs->rc_central_cfg4)); + rc_info("RC_DCXO_FPM_CFG:0x%x\n", read32(&rc_regs->rc_dcxo_fpm_cfg)); + rc_info("SUBSYS_INTF_CFG:0x%x\n", read32(&rc_regs->rc_subsys_intf_cfg)); + rc_info("RC_SPI_STA_0:0x%x\n", read32(&rc_sta_regs->rc_spi_sta_0)); + rc_info("RC_PI_PO_STA:0x%x\n", read32(&rc_sta_regs->rc_pi_po_sta_0)); + + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++){ + rc_info("M0%d: 0x%x\n", chn_n, + read32(&rc_regs->rc_mxx_srclken_cfg[chn_n])); + } +#endif +} + +/* RC initial flow and relative setting */ +static void __rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode) +{ +#ifdef MTK_SRCLKEN_RC_SUPPORT + + unsigned int value = 0; + + if(mode == INIT_MODE){ + value = ((rc_ctrl[id].dcxo_settle_blk_en & DCXO_SETTLE_BLK_EN_MSK) << DCXO_SETTLE_BLK_EN_SHFT) | + ((rc_ctrl[id].bypass_cmd & BYPASS_CMD_EN_MSK) << BYPASS_CMD_EN_SHFT) | + ((rc_ctrl[id].sw_rc & SW_SRCLKEN_RC_MSK) << SW_SRCLKEN_RC_SHFT) | + ((rc_ctrl[id].sw_fpm & SW_SRCLKEN_FPM_MSK) << SW_SRCLKEN_FPM_SHFT) | + ((rc_ctrl[id].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << SW_SRCLKEN_BBLPM_SHFT) | + ((rc_ctrl[id].xo_soc_link_en & XO_SOC_LINK_EN_MSK) << XO_SOC_LINK_EN_SHFT) | + ((rc_ctrl[id].req_ack_imd_en & REQ_ACK_LOW_IMD_EN_MSK) << REQ_ACK_LOW_IMD_EN_SHFT) | + ((rc_ctrl[id].track_en & SRCLKEN_TRACK_M_EN_MSK) << SRCLKEN_TRACK_M_EN_SHFT) | + ((rc_ctrl[id].cnt_step & CNT_PRD_STEP_MSK) << CNT_PRD_STEP_SHFT) | + ((rc_ctrl[id].xo_prd & XO_STABLE_PRD_MSK) << XO_STABLE_PRD_SHFT) | + ((rc_ctrl[id].dcxo_prd & DCXO_STABLE_PRD_MSK) << DCXO_STABLE_PRD_SHFT) ; + }else if (mode == SW_MODE){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) | ( 0x1 << SW_SRCLKEN_RC_SHFT); + }else if (mode == HW_MODE){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) & ~(SW_SRCLKEN_RC_MSK << SW_SRCLKEN_RC_SHFT); + }else + return; + + write32(&rc_regs->rc_mxx_srclken_cfg[id], value); + + rc_info("M0%d: 0x%x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +#endif +} + + +/* RC subsys FPM control*/ +static void __rc_ctrl_fpm_switch(enum chn_id id, unsigned int mode) +{ +#ifdef MTK_SRCLKEN_RC_SUPPORT + + unsigned int value = 0; + + if (mode == SW_FPM_HIGH){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) | ( 0x1 << SW_SRCLKEN_FPM_SHFT); + }else if (mode == SW_FPM_LOW){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) & ~(SW_SRCLKEN_FPM_MSK << SW_SRCLKEN_FPM_SHFT); + }else + return; + + rc_ctrl[id].sw_fpm = mode; + write32(&rc_regs->rc_mxx_srclken_cfg[id], value); + + rc_info("M0%d FPM SWITCH: 0x%x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +#endif +} + +static void __rc_ctrl_bblpm_switch(enum chn_id id, unsigned int mode) +{ +#ifdef MTK_SRCLKEN_RC_SUPPORT + + unsigned int value = 0; + + if (mode == SW_BBLPM_HIGH){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) | ( 0x1 << SW_SRCLKEN_BBLPM_SHFT); + }else if (mode == SW_BBLPM_LOW){ + value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) & ~(SW_SRCLKEN_BBLPM_MSK << SW_SRCLKEN_BBLPM_SHFT); + }else + return; + + rc_ctrl[id].sw_bblpm = mode; + write32(&rc_regs->rc_mxx_srclken_cfg[id], value); + + rc_info("M0%d BBLPM SWITCH: 0x%x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +#endif +} + +static void rc_init_subsys_hw_mode(void){ +#ifdef MTK_SRCLKEN_RC_SUPPORT + unsigned int chn_n; + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++){ + if( INIT_SUBSYS_TO_HW & (1 << chn_n)) + __rc_ctrl_mode_switch(chn_n, HW_MODE); + } +#endif +} + +static void rc_init_subsys_lpm(void){ +#ifdef MTK_SRCLKEN_RC_SUPPORT + unsigned int chn_n; + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++){ + if( INIT_SUBSYS_FPM_TO_LPM & (1 << chn_n)) + __rc_ctrl_fpm_switch(chn_n, SW_FPM_LOW); + } + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++){ + if( INIT_SUBSYS_FPM_TO_BBLPM & (1 << chn_n)) + __rc_ctrl_bblpm_switch(chn_n, SW_BBLPM_HIGH); + } +#endif +} + +#if 0 +static void rc_ctrl_mode_switch_hw(enum chn_id id) +{ + __rc_ctrl_mode_switch(id, HW_MODE); +} + +static void rc_ctrl_mode_switch_sw(enum chn_id id) +{ + __rc_ctrl_mode_switch(id, SW_MODE); +} +#endif + +static void rc_ctrl_mode_switch_init(enum chn_id id) +{ + __rc_ctrl_mode_switch(id, INIT_MODE); +} + +static int srclken_rc_chk_init_cfg(void) +{ +#if MTK_SRCLKEN_RC_BRINGUP + rc_info("Bring-UP : skip srclken_rc init\n"); + + return SRLCKEN_RC_BRINGUP; +#else + pmwrap_interface_init(); + + /*enable debug trace*/ +#if SRCLKEN_DBG + write32(&rc_sta_regs->rc_debug_trace, 1); + write32(&rc_regs->rc_debug_cfg, + read32(&rc_regs->rc_debug_cfg) + | (TRACE_MODE_EN_MSK << TRACE_MODE_EN_SHFT)); +#endif +#ifdef MTK_SRCLKEN_RC_SUPPORT + return SRCLKEN_RC_ENABLE; +#else + return SRCLKEN_RC_DISABLE; +#endif +#endif +} + +int srclken_rc_init(void) +{ + /* new co-clock architecture srclkenrc implement here */ + unsigned int chn_n; + int ret = 0; + + /* check platform config to proceed init flow */ + if (srclken_rc_chk_init_cfg() != SRCLKEN_RC_ENABLE) + return ret; + + /* Set SW RESET 1 */ + write32(&rc_regs->srclken_rc_cfg, 1 << SW_RESET_SHFT); + + /* Wait 100us */ + udelay(100); + + /* Set SW CG 1 */ + write32(&rc_regs->srclken_rc_cfg, + (1 << SW_RESET_SHFT) | (1 << CG_32K_EN_SHFT) + | (1 << CG_FCLK_EN_SHFT) | (1 << CG_FCLK_FR_EN_SHFT)); + + /* Wait 100us */ + udelay(100); + + /* Set Clock Mux*/ + write32(&rc_regs->srclken_rc_cfg, + (1 << SW_RESET_SHFT) |(1 << CG_32K_EN_SHFT) + | (1 << CG_FCLK_EN_SHFT) | (1 << CG_FCLK_FR_EN_SHFT) + | (1 << MUX_FCLK_FR_SHFT)); + + /* Set req_filter m00~m12 as default SW_FPM */ + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) + rc_ctrl_mode_switch_init(chn_n); + + /* Set PMIC addr for SPI CMD */ + write32(&rc_regs->rc_pmic_rcen_addr, PMRC_CON0); + + write32(&rc_regs->rc_pmic_rcen_set_clr_addr, + (PMRC_CON0_CLR << 16 | PMRC_CON0_SET)); + + write32(&rc_regs->rc_cmd_arb_cfg, 0); + + /* CFG1 setting for spi cmd config */ + write32(&rc_regs->rc_central_cfg1, + DCXO_SETTLE_TIME << DCXO_SETTLE_T_SHFT | + XO_SETTLE_TIME << NON_DCXO_SETTLE_T_SHFT | + ULPOSC_SETTLE_TIME << ULPOSC_SETTLE_T_SHFT | + VCORE_SETTLE_TIME << VCORE_SETTLE_T_SHFT | + SRCLKEN_RC_EN_SEL << SRCLKEN_RC_EN_SEL_SHFT | + KEEP_RC_SPI_ACTIVE << RC_SPI_ACTIVE_SHFT | + IS_SPI2PMIC_SET_CLR << RCEN_ISSUE_M_SHFT | + RC_CENTRAL_DISABLE << SRCLKEN_RC_EN_SHFT); + + /* CFG2 setting for signal mode of each control mux */ + write32(&rc_regs->rc_central_cfg2, + SPI_CLK_SRC << PWRAP_SLP_MUX_SEL_SHFT | + PWRAP_CTRL_M << PWRAP_SLP_CTRL_M_SHFT | + ULPOSC_CTRL_M << ULPOSC_CTRL_M_SHFT | + IS_SPI_DONE_RELEASE << SRCVOLTEN_VREQ_M_SHFT | + SPI_TRIG_MODE << SRCVOLTEN_VREQ_SEL_SHFT | + VREQ_CTRL_M << VREQ_CTRL_SHFT | + SRCLKENO_0_CTRL_M << SRCVOLTEN_CTRL_SHFT); + + write32(&rc_regs->rc_central_cfg3, + 0x4 << TO_LPM_SETTLE_T_SHFT | + 1 << TO_BBLPM_SETTLE_EN_SHFT | + 1 << BLK_COANT_DXCO_MD_TARGET_SHFT | + 1 << BLK_SCP_DXCO_MD_TARGET_SHFT | + 1 << TO_LPM_SETTLE_EN_SHFT); + + /* Set srclkeno_0/conn_bt as factor to allow dcxo change to FPM */ + write32(&rc_regs->rc_dcxo_fpm_cfg, + FPM_MSK_B << SUB_SRCLKEN_FPM_MSK_B_SHFT | + MD0_SRCLKENO_0_MASK_B << SRCVOLTEN_FPM_MSK_B_SHFT | + DCXO_FPM_CTRL_MODE << DCXO_FPM_CTRL_M_SHFT); + + /* Set bblpm/fpm channel */ + write32(&rc_regs->rc_subsys_intf_cfg, + SUB_BBLPM_SET << SRCLKEN_BBLPM_MASK_B_SHFT| + SUB_FPM_SET << SRCLKEN_FPM_MASK_B_SHFT); + + /* Trigger srclken_rc enable */ + write32(&rc_regs->rc_central_cfg1, read32(&rc_regs->rc_central_cfg1) + | (RC_CENTRAL_ENABLE << SRCLKEN_RC_EN_SHFT)); + + write32(&rc_regs->rc_central_cfg4, + 0x1 << SLEEP_VLD_MODE_SHFT | + 0x1 << PWRAP_VLD_FORCE_SHFT | + 0x800 << KEEP_RC_SPI_ACTIVE_SHFT); + + + /* Wait 100us */ + udelay(100); + + /* Set SW RESET 0 */ + write32(&rc_regs->srclken_rc_cfg, + (1 << CG_32K_EN_SHFT) | (1 << CG_FCLK_EN_SHFT) + | (1 << CG_FCLK_FR_EN_SHFT) | (1 << MUX_FCLK_FR_SHFT)); + + /* Wait 100us */ + udelay(100); + + /* Set SW CG 0 */ + write32(&rc_regs->srclken_rc_cfg, 1 << MUX_FCLK_FR_SHFT); + + /* Wait 500us */ + udelay(500); + + /* Set req_filter m00~m12 FPM to LPM*/ + rc_init_subsys_lpm(); + + /* Polling ACK of Initial Subsys Input */ + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + unsigned int chk_sta, shift_chn_n = 0; + int i = 0; + u32 temp; + + if(chn_n > 0) + shift_chn_n = 1; + + chk_sta = (rc_ctrl[chn_n].sw_fpm & SW_SRCLKEN_FPM_MSK) << 1 + | (rc_ctrl[chn_n].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << 3; + ; /* Fix RC_MXX_REQ_STA_0 register shift */ + while((read32(&rc_sta_regs->rc_mxx_req_sta_0[chn_n + shift_chn_n]) & 0xa) != chk_sta) { + udelay(10); + i++; + if(i > 200) { + pmic_read(PMIC_PMRC_CON0, &temp); + rc_info("%s: polling M%d status fail.(R:0x%x)(C:0x%x)(PMRC:0x%x)\n", + __func__, chn_n, + read32(&rc_sta_regs->rc_mxx_req_sta_0[chn_n + shift_chn_n]), + read32(&rc_regs->rc_mxx_srclken_cfg[chn_n]), temp); + ret = -1; + break; + } + } + } + + /* Set req_filter m00~m12 */ + rc_init_subsys_hw_mode(); + + /* release force pmic req signal*/ + write32(&rc_regs->rc_central_cfg4, + 0x1 << SLEEP_VLD_MODE_SHFT | + 0x800 << KEEP_RC_SPI_ACTIVE_SHFT); + + rc_dump_reg_info(); + + return ret; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I947bf14df7a307bf359c590c2a20265882b3f1be Gerrit-Change-Number: 46878 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ran Bi <ran.bi(a)mediatek.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-MessageType: newchange

10 80

Change in coreboot[master]: soc/mediatek/mt8192: Save dramc shuffle result after calibration
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44714 to review the following change. Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ...................................................................... soc/mediatek/mt8192: Save dramc shuffle result after calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index ce24829..67e2340 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -111,3 +111,85 @@ *(cali->pll_mode) = pll_mode; } +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("wait dramc to shuffle sram done, tmp:%d.\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); +} + +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE)<< 1); + dramc_dbg("wait shuffle sram to dramc done.\n"); + } while (tmp != 0x3); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 5ca7bce..3273f28 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -290,6 +290,11 @@ get_dram_info_after_cal(&cali); dramc_ac_timing_optimize(&cali); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); + + /* for frequency switch in dramc_mode_reg_init phase */ + if (first_freq_k) + dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); first_freq_k= false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 Gerrit-Change-Number: 44714 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: soc/mediatek/mt8192: Add dramc ac timing setting
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44713 to review the following change. Change subject: soc/mediatek/mt8192: Add dramc ac timing setting ...................................................................... soc/mediatek/mt8192: Add dramc ac timing setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h 3 files changed, 1,320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44713/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 31e8d0e..1a5f242 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3,6 +3,7 @@ #include <soc/gpio.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_ac_timing.h> #include <string.h> #include <timer.h> @@ -4030,6 +4031,206 @@ dramc_set_broadcast(bc_bak); } +static void ddr_update_ac_timing(const struct ddr_cali *cali) +{ + u8 table_idx; + struct ac_timing ac_tim; + dram_freq_grp freq_group = cali->freq_group; + + u8 rank_inctl = 0, tx_dly = 0, datlat_dsel = 0; + u8 rodt_tracking_mck = 0, root = 0, tx_rank_inctl = 0; + u8 tref_bw = 0, tfaw_05t=0, trrd_05t=0; + u16 xrtwtw = 0, xtrtrt = 0, xrtw2r = 0, xrtr2w = 0, tfaw = 0; + u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; + u16 phs_inctl = 0; + u32 rank_inctl_root; + + for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++) + if ((ac_timing_tbl[table_idx].freq_group == freq_group) && + (ac_timing_tbl[table_idx].div_mode == get_div_mode(cali)) && + (ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali))) { + dramc_dbg("match AC timing table %d\n", table_idx); + break; + } + + if (table_idx == AC_TIMING_NUMBER) { + dramc_dbg("Error, no match AC timing table\n"); + return; + } + memcpy(&ac_tim, &ac_timing_tbl[table_idx], sizeof(struct ac_timing)); + + trtw = ac_tim.trtw_odt_on; + trtw_05t = ac_tim.trtw_odt_on_05T; + xrtw2r = ac_tim.xrtw2r_odt_on; + xrtr2w = ac_tim.xrtr2w_odt_on; + tfaw = ac_tim.tfaw_4266; + tfaw_05t = ac_tim.tfaw_4266_05T; + trrd = ac_tim.trrd_4266; + trrd_05t = ac_tim.trrd_4266_05T; + xtrtrt = ac_tim.xrtr2r_new_mode; + xrtwtw = ac_tim.xrtw2w_new_mode; + tmrr2w = ac_tim.tmrr2w_odt_on; + rodt_tracking_mck = 0; + trtw = trtw - rodt_tracking_mck; + xrtr2w = xrtr2w - rodt_tracking_mck; + + if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = ac_tim.datlat; + else + datlat_dsel = ac_tim.datlat - 1; + + if (ac_tim.dqsinctl >= 2) { + rank_inctl_root = ac_tim.dqsinctl - 2; + } else { + dramc_info("rank_inctl_root <2, need check\n"); + rank_inctl_root = 0; + } + phs_inctl = (ac_tim.dqsinctl == 0) ? 0 : (ac_tim.dqsinctl - 1); + + if (freq_group <= DDRFREQ_800) { + if (get_div_mode(cali) == DIV4_MODE) { + tx_rank_inctl = 1; + tx_dly = 2; + } else { + tx_rank_inctl = 0; + tx_dly = 1; + } + } else { + tx_rank_inctl = 1; + tx_dly = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim1, + SHU_ACTIM1_TRAS, ac_tim.tras, + SHU_ACTIM1_TRP, ac_tim.trp, + SHU_ACTIM1_TRPAB, ac_tim.trpab, + SHU_ACTIM1_TMRWCKEL, ac_tim.tmrwckel, + SHU_ACTIM1_TRC, ac_tim.trc); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, ac_tim.trfc, + SHU_ACTIM3_TR2MRR, ac_tim.tr2mrr, + SHU_ACTIM3_TRFCPB, ac_tim.trfcpb); + SET32_BITFIELDS(&ch[chn].ao.shu_actim2, + SHU_ACTIM2_TXP, ac_tim.txp, + SHU_ACTIM2_TMRRI, ac_tim.tmrri, + SHU_ACTIM2_TFAW, tfaw, + SHU_ACTIM2_TR2W, trtw, + SHU_ACTIM2_TRTP, ac_tim.trtp); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, + SHU_ACTIM0_TRCD, ac_tim.trcd, + SHU_ACTIM0_TWR, ac_tim.twr, + SHU_ACTIM0_TRRD, trrd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, + SHU_ACTIM5_TPBR2PBR, ac_tim.tpbr2pbr, + SHU_ACTIM5_TWTPD, ac_tim.twtpd, + SHU_ACTIM5_TPBR2ACT, ac_tim.tpbr2act); + SET32_BITFIELDS(&ch[chn].ao.shu_actim6, + SHU_ACTIM6_TR2MRW, ac_tim.tr2mrw, + SHU_ACTIM6_TW2MRW, ac_tim.tw2mrw, + SHU_ACTIM6_TMRD, ac_tim.tmrd, + SHU_ACTIM6_TZQLAT2, ac_tim.zqlat2, + SHU_ACTIM6_TMRW, ac_tim.tmrw); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TMRR2MRW, ac_tim.tmrr2mrw, + SHU_ACTIM4_TMRR2W, tmrr2w, + SHU_ACTIM4_TZQCS, ac_tim.tzqcs, + SHU_ACTIM4_TXREFCNT, ac_tim.txrefcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim.ckeprd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTW2W, xrtwtw, + SHU_ACTIM_XRT_XRTW2R, xrtw2r, + SHU_ACTIM_XRT_XRTR2W, xrtr2w, + SHU_ACTIM_XRT_XRTR2R, xtrtrt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim.vrcgdis_prdcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim.hwset_mr2_op); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim.hwset_mr13_op); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TWTR_M05T, ac_tim.twtr_05T, + SHU_AC_TIME_05T_TR2W_05T, trtw_05t, + SHU_AC_TIME_05T_TWTPD_M05T, ac_tim.twtpd_05T, + SHU_AC_TIME_05T_TFAW_05T, tfaw_05t, + SHU_AC_TIME_05T_TRRD_05T, trrd_05t, + SHU_AC_TIME_05T_TWR_M05T, ac_tim.twr_05T, + SHU_AC_TIME_05T_TRAS_05T, ac_tim.tras_05T, + SHU_AC_TIME_05T_TRPAB_05T, ac_tim.trpab_05T, + SHU_AC_TIME_05T_TRP_05T, ac_tim.trp_05T, + SHU_AC_TIME_05T_TRCD_05T, ac_tim.trcd_05T, + SHU_AC_TIME_05T_TRTP_05T, ac_tim.trtp_05T, + SHU_AC_TIME_05T_TXP_05T, ac_tim.txp_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, ac_tim.trfc_05T, + SHU_AC_TIME_05T_TRFCPB_05T, ac_tim.trfcpb_05T, + SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim.tpbr2pbr_05T, + SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim.tpbr2act_05T, + SHU_AC_TIME_05T_TR2MRW_05T, ac_tim.tr2mrw_05T, + SHU_AC_TIME_05T_TW2MRW_05T, ac_tim.tw2mrw_05T, + SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim.tmrr2mrw_05T, + SHU_AC_TIME_05T_TMRW_05T, ac_tim.tmrw_05T, + SHU_AC_TIME_05T_TMRD_05T, ac_tim.tmrd_05T, + SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim.tmrwckel_05T, + SHU_AC_TIME_05T_TMRRI_05T, ac_tim.tmrri_05T, + SHU_AC_TIME_05T_TRC_05T, ac_tim.trc_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim.twtr); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, + SHU_CKECTRL_TPDE, ac_tim.tpde, + SHU_CKECTRL_TPDX, ac_tim.tpdx, + SHU_CKECTRL_TPDE_05T, ac_tim.tpde_05T, + SHU_CKECTRL_TPDX_05T, ac_tim.tpdx_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim.trtpd); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2PD_05T, ac_tim.trtpd_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_TRCD_DERATE, ac_tim.trcd_derate, + SHU_AC_DERATING0_TRRD_DERATE, ac_tim.trrd_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRC_DERATE, ac_tim.trc_derate, + SHU_AC_DERATING1_TRAS_DERATE, ac_tim.tras_derate, + SHU_AC_DERATING1_TRP_DERATE, ac_tim.trp_derate, + SHU_AC_DERATING1_TRPAB_DERATE, ac_tim.trpab_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim.trrd_derate_05T, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim.tras_derate_05T, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim.trpab_derate_05T, + SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim.trp_derate_05T, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim.trcd_derate_05T, + SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim.trc_derate_05T); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODT_LAT, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim.dqsinctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, ac_tim.datlat, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf, + SHU_ACTIMING_CONF_REFBW_FR, tref_bw); + rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly); + } +} + static void set_cke2rank_independent(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -4121,6 +4322,8 @@ dramc_8_phase_cal(cali); dramc_duty_calibration(cali->params); dramc_mode_reg_init(cali); + + ddr_update_ac_timing(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index cf199dc..5ca7bce 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,151 @@ #include <soc/pll_common.h> #include <soc/mt6359p.h> +static void dramc_ac_timing_optimize(const struct ddr_cali* cali) +{ + u8 rf_group = 0, cab_id = 0; + u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + + enum { + tRFCAB_130, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM + }; + enum { + GRP_DDR800_DIV4_ACTIM, + GRP_DDR1200_ACTIM, + GRP_DDR1600_ACTIM, + GRP_DDR1866_ACTIM, + GRP_DDR2400_ACTIM, + GRP_DDR3200_ACTIM, + GRP_DDR4266_ACTIM, + GRP_ACTIM_NUM + }; + struct optimize_ac_time { + u8 trfc; + u8 trfc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; + u16 tx_ref_cnt; + }; + + u8 density = cali->density; + dram_freq_grp freq_group = get_freq_group(cali); + + struct optimize_ac_time *ptRFCab_Opt; + struct optimize_ac_time tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = { + [GRP_DDR800_DIV4_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1200_ACTIM] = { + {.trfc = 8, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 21}, + {.trfc = 15, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 29}, + {.trfc = 30, .trfc_05t = 1, .trfc_pb = 9, .trfrc_pb05t = 1, .tx_ref_cnt = 44}, + {.trfc = 45, .trfc_05t = 1, .trfc_pb = 17, .trfrc_pb05t = 0, .tx_ref_cnt = 59} + }, + [GRP_DDR1600_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1866_ACTIM] = { + {.trfc = 18, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 33}, + {.trfc = 30, .trfc_05t = 0, .trfc_pb = 9, .trfrc_pb05t = 0, .tx_ref_cnt = 44}, + {.trfc = 53, .trfc_05t = 1, .trfc_pb = 21, .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + {.trfc = 77, .trfc_05t = 0, .trfc_pb = 32, .trfrc_pb05t = 1, .tx_ref_cnt = 91} + }, + [GRP_DDR2400_ACTIM] = { + {.trfc = 27, .trfc_05t = 1, .trfc_pb = 6, .trfrc_pb05t = 1, .tx_ref_cnt = 42}, + {.trfc = 42, .trfc_05t = 1, .trfc_pb = 15, .trfrc_pb05t = 1, .tx_ref_cnt = 57}, + {.trfc = 72, .trfc_05t = 1, .trfc_pb = 30, .trfrc_pb05t = 1, .tx_ref_cnt = 87}, + {.trfc = 102, .trfc_05t = 1, .trfc_pb = 45, .trfrc_pb05t = 1, .tx_ref_cnt = 117} + }, + [GRP_DDR3200_ACTIM] = { + {.trfc = 40, .trfc_05t = 0, .trfc_pb = 12, .trfrc_pb05t = 0, .tx_ref_cnt = 55}, + {.trfc = 60, .trfc_05t = 0, .trfc_pb = 24, .trfrc_pb05t = 0, .tx_ref_cnt = 75}, + {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, .trfrc_pb05t = 0, .tx_ref_cnt = 115}, + {.trfc = 140, .trfc_05t = 0, .trfc_pb = 64, .trfrc_pb05t = 0, .tx_ref_cnt = 155} + }, + [GRP_DDR4266_ACTIM] = { + {.trfc = 57, .trfc_05t = 1, .trfc_pb = 20, .trfrc_pb05t = 0, .tx_ref_cnt = 74}, + {.trfc = 84, .trfc_05t = 0, .trfc_pb = 36, .trfrc_pb05t = 0, .tx_ref_cnt = 100}, + {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, .trfrc_pb05t = 0, .tx_ref_cnt = 154}, + {.trfc = 191, .trfc_05t = 0, .trfc_pb = 89, .trfrc_pb05t = 1, .tx_ref_cnt = 207} + } + }; + + switch (density) { + case 0x0: + rf_group = tRFCAB_130; + break; + case 0x1: + case 0x2: + rf_group = tRFCAB_180; + break; + case 0x3: + case 0x4: + rf_group = tRFCAB_280; + break; + case 0x5: + case 0x6: + rf_group = tRFCAB_380; + break; + default: + die("Invalid DDR density %u\n", density); + return; + } + + switch (freq_group) { + case DDRFREQ_400: + cab_id = GRP_DDR800_DIV4_ACTIM; + break; + case DDRFREQ_600: + cab_id = GRP_DDR1200_ACTIM; + break; + case DDRFREQ_800: + cab_id = GRP_DDR1600_ACTIM; + break; + case DDRFREQ_933: + cab_id = GRP_DDR1866_ACTIM; + break; + case DDRFREQ_1200: + cab_id = GRP_DDR2400_ACTIM; + break; + case DDRFREQ_1600: + cab_id = GRP_DDR3200_ACTIM; + break; + case DDRFREQ_2133: + cab_id = GRP_DDR4266_ACTIM; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + ptRFCab_Opt = &tRFCab_Opt[cab_id][0]; + trfc = ptRFCab_Opt[rf_group].trfc; + trfc_05t = ptRFCab_Opt[rf_group].trfc_05t; + trfc_pb = ptRFCab_Opt[rf_group].trfc_pb; + trfrc_pb05t = ptRFCab_Opt[rf_group].trfrc_pb05t; + tx_ref_cnt = ptRFCab_Opt[rf_group].tx_ref_cnt; + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFC, trfc); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, SHU_ACTIM4_TXREFCNT, tx_ref_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFCPB, trfc_pb); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); + dramc_dbg("Density (MR8 OP[5:2]) %d, TRFC %d, TRFC_05T %d, TXREFCNT %d, TRFCpb %d, TRFCpb_05T %d\n", + density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + } +} + static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) { u32 vcore = get_vcore_value(cali); @@ -144,6 +289,8 @@ if (first_freq_k) get_dram_info_after_cal(&cali); + dramc_ac_timing_optimize(&cali); + first_freq_k= false; } } diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h new file mode 100644 index 0000000..717d247 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h @@ -0,0 +1,970 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_common_mt8192.h> + +/* Normal Mode and Byte Mode */ +#define AC_TIMING_NUMBER (DDRFREQ_MAX * 2) + +struct ac_timing { + u8 cbt_mode, read_dbi; + u8 div_mode; + u16 freq_group; + u16 read_lat, write_lat; + u16 dqsinctl, datlat; + u16 tras; + u16 trp; + u16 trpab; + u16 trc; + u16 trfc; + u16 trfcpb; + u16 txp; + u16 trtp; + u16 trcd; + u16 twr; + u16 twtr; + u16 tpbr2pbr; + u16 tpbr2act; + u16 tr2mrw; + u16 tw2mrw; + u16 tmrr2mrw; + u16 tmrw; + u16 tmrd; + u16 tmrwckel; + u16 tpde; + u16 tpdx; + u16 tmrri; + u16 trrd; + u16 trrd_4266; + u16 tfaw; + u16 tfaw_4266; + u16 trtw_odt_off; + u16 trtw_odt_on; + u16 txrefcnt; + u16 tzqcs; + u16 xrtw2w_new_mode; + u16 xrtw2w_old_mode; + u16 xrtw2r_odt_on; + u16 xrtw2r_odt_off; + u16 xrtr2w_odt_on; + u16 xrtr2w_odt_off; + u16 xrtr2r_new_mode; + u16 xrtr2r_old_mode; + u16 tr2mrr; + u16 vrcgdis_prdcnt; + u16 hwset_mr2_op; + u16 hwset_mr13_op; + u16 hwset_vrcg_op; + u16 trcd_derate; + u16 trc_derate; + u16 tras_derate; + u16 trpab_derate; + u16 trp_derate; + u16 trrd_derate; + u16 trtpd; + u16 twtpd; + u16 tmrr2w_odt_off; + u16 tmrr2w_odt_on; + u16 ckeprd; + u16 ckelckcnt; + u16 zqlat2; + u16 tras_05T; + u16 trp_05T; + u16 trpab_05T; + u16 trc_05T; + u16 trfc_05T; + u16 trfcpb_05T; + u16 txp_05T; + u16 trtp_05T; + u16 trcd_05T; + u16 twr_05T; + u16 twtr_05T; + u16 tpbr2pbr_05T; + u16 tpbr2act_05T; + u16 tr2mrw_05T; + u16 tw2mrw_05T; + u16 tmrr2mrw_05T; + u16 tmrw_05T; + u16 tmrd_05T; + u16 tmrwckel_05T; + u16 tpde_05T; + u16 tpdx_05T; + u16 tmrri_05T; + u16 trrd_05T; + u16 trrd_4266_05T; + u16 tfaw_05T; + u16 tfaw_4266_05T; + u16 trtw_odt_off_05T; + u16 trtw_odt_on_05T; + u16 trcd_derate_05T; + u16 trc_derate_05T; + u16 tras_derate_05T; + u16 trpab_derate_05T; + u16 trp_derate_05T; + u16 trrd_derate_05T; + u16 trtpd_05T; + u16 twtpd_05T; +}; + +/* Normal Mode and Byte Mode for each frequency */ +static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = { + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 36, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 14, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 40, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 28, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 8, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 32, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 24, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 9, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 26, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 20, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 1, + .twtr = 5, .twtr_05T = 1, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 0, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 9, .trtpd_05T = 1, + .twtpd = 10, .twtpd_05T = 1, + .tmrr2w_odt_off = 5, + .tmrr2w_odt_on = 7, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 22, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 0, + .twtr = 5, .twtr_05T = 0, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 1, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 4, + .xrtr2w_odt_off = 4, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 11, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 4, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, +}; +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a Gerrit-Change-Number: 44713 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 56

Change in coreboot[master]: soc/mediatek/mt8192: Get DDR base information after calibration
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44712 to review the following change. Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ...................................................................... soc/mediatek/mt8192: Get DDR base information after calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index adabb80..31e8d0e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3835,6 +3835,36 @@ write32(regs_bak[i].addr, regs_bak[i].value); } +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d =%#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value = 0; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + return value; +} + void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, u8 chn, u8 rank, u8 mr_idx, u8 value) { diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 355cc9d..cf199dc 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -14,6 +14,55 @@ mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); } +static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } @@ -91,6 +140,10 @@ dramc_calibration_all_channels(&cali); + /* only need do once for get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + first_freq_k= false; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Gerrit-Change-Number: 44712 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: tests: Add lib/imd_cbmem-test test case
by Name of user not set (Code Review) 18 Jan '21

18 Jan '21

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46458 ) Change subject: tests: Add lib/imd_cbmem-test test case ...................................................................... tests: Add lib/imd_cbmem-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie893b5e8fc91c230ff96a14146085de16d78b1c1 --- M tests/lib/Makefile.inc A tests/lib/imd_cbmem-test.c 2 files changed, 309 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46458/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..2f381fe 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += imd_cbmem-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,11 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +imd_cbmem-test-srcs += tests/lib/imd_cbmem-test.c +# imd_cbmem-test-srcs += src/lib/imd_cbmem.c +imd_cbmem-test-srcs += tests/stubs/console.c +imd_cbmem-test-srcs += src/lib/imd.c +imd_cbmem-test-srcs += src/lib/bootmem.c +imd_cbmem-test-srcs += src/lib/memrange.c diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c new file mode 100644 index 0000000..2ad0941 --- /dev/null +++ b/tests/lib/imd_cbmem-test.c @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Include UUT source code directly instead of linking it. This will allow + * access to internal structures and data without having to extract them to + * another header file + */ +#include "../lib/imd_cbmem.c" + +#include <imd.h> +#include <cbmem.h> +#include <stdlib.h> +#include <tests/test.h> +#include <stdio.h> +#include <commonlib/bsd/helpers.h> +#include <imd_private.h> + +#define LIMIT_SZ (LIMIT_ALIGN + 1) + +#define CBMEM_ENTRY_ID 0xA001 +#define CBMEM_SM_ENTRY_ID 0xB001 + +#define CBMEM_SIZE (4 * MiB) + +void reset_imd(void) +{ + imd.lg.limit = (uintptr_t) NULL; + imd.lg.r = NULL; + imd.sm.limit = (uintptr_t) NULL; + imd.sm.r = NULL; +} + +void cbmem_run_init_hooks(int is_recovery) +{ + (void) is_recovery; +} + +static void test_cbmem_top(void **state) +{ + cbmem_top_init_once(); + + if (ENV_ROMSTAGE) + assert_ptr_equal(cbmem_top_chipset(), cbmem_top()); + + if (ENV_POSTCAR || ENV_RAMSTAGE) + assert_ptr_equal((void *)_cbmem_top_ptr, cbmem_top()); +} + +static void test_cbmem_initialize_empty(void **state) +{ + const struct cbmem_entry *found; + + cbmem_initialize_empty(); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_empty_id_size(void **state) +{ + const struct cbmem_entry *found_1, *found_2; + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_initialize(void **state) +{ + int res; + const struct cbmem_entry *found; + + res = cbmem_initialize(); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize(); + assert_int_equal(0, res); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_id_size(void **state) +{ + int res; + const struct cbmem_entry *found_1, *found_2; + + res = cbmem_initialize_id_size(0, 0); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_recovery(void **state) +{ + int is_wakeup = 1; + assert_int_equal(0, cbmem_recovery(is_wakeup)); + + is_wakeup = 0; + assert_int_equal(0, cbmem_recovery(is_wakeup)); +} + +static void test_cbmem_entry_add(void **state) +{ + int id1 = 0x1; + int id2 = 0x2; + + assert_null(cbmem_entry_find(id1)); + assert_null(cbmem_entry_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_entry_find(id1)); + assert_non_null(cbmem_entry_find(id2)); +} + +static void test_cbmem_add(void **state) +{ + int id1 = 0x3; + int id2 = 0x4; + + assert_null(cbmem_find(id1)); + assert_null(cbmem_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_find(id1)); + assert_non_null(cbmem_find(id2)); +} + +static void test_cbmem_entry_find(void **state) +{ + int id1 = 0x6; + int id2 = 0x7; + const struct cbmem_entry *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_entry_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_entry_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_find(void **state) +{ + int id1 = 0x8; + int id2 = 0x9; + void *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_entry_remove(void **state) +{ + int id1 = 0x10; + int id2 = 0x11; + const struct cbmem_entry *cbm_e1, *cbm_e2; + + assert_int_equal(-1, cbmem_entry_remove(NULL)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_int_equal(-1, cbmem_entry_remove(cbm_e1)); + assert_int_equal(0, cbmem_entry_remove(cbm_e2)); + assert_int_equal(0, cbmem_entry_remove(cbm_e1)); +} + +static void test_cbmem_entry_size(void **state) +{ + struct imd_entry i_e = { .size = CBMEM_ROOT_SIZE }; + const struct cbmem_entry *cbm_e = imd_to_cbmem(&i_e); + + assert_int_equal(CBMEM_ROOT_SIZE, cbmem_entry_size(cbm_e)); + + i_e.size = 0; + assert_int_equal(0, cbmem_entry_size(cbm_e)); +} + +static void test_cbmem_entry_start(void **state) +{ + const struct cbmem_entry *cbm_e = NULL; + + assert_null(cbmem_entry_start(cbm_e)); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + cbm_e = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(cbmem_entry_start(cbm_e)); +} + +static void test_cbmem_add_bootmem(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_add_bootmem(); + + assert_non_null(&baseptr); + assert_int_not_equal(0, &size); +} + +static void test_cbmem_get_region(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_get_region(&baseptr, &size); + assert_non_null(&baseptr); + assert_int_not_equal(0, size); +} + +static int teardown_test_imd_cbmem(void **state) +{ + reset_imd(); + return 0; +} + +static int setup_group_imd_cbmem(void **status) +{ + _cbmem_top_ptr = (uintptr_t)malloc(CBMEM_SIZE) + CBMEM_SIZE; + return 0; +} + +static int teardown_group_imd_cbmem(void **status) +{ + free((void *)_cbmem_top_ptr - CBMEM_SIZE); + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_cbmem_top), + cmocka_unit_test_teardown(test_cbmem_initialize_empty, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_empty_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_recovery, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_remove, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_start, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add_bootmem, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_get_region, teardown_test_imd_cbmem), + }; + + return cmocka_run_group_tests(tests, setup_group_imd_cbmem, teardown_group_imd_cbmem); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie893b5e8fc91c230ff96a14146085de16d78b1c1 Gerrit-Change-Number: 46458 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

6 34

Change in coreboot[master]: nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 16 Jan '21

16 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46282 ) Change subject: nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I633d944b6171902e1c28de634341cd6001ba6f16 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 3 files changed, 326 insertions(+), 336 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46282/1 diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..13893f2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -67,10 +67,10 @@ if (config->use_crt) { /* Enable VGA */ - MCHBAR32_OR(DACGIOCTRL1, 1 << 15); + mchbar32_or(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); + mchbar32_unset(DACGIOCTRL1, (1 << 15)); } if (config->use_lvds) { @@ -79,17 +79,17 @@ reg32 &= ~0xf1000000; reg32 |= 0x90000000; MCHBAR32(LVDSICR2) = reg32; - MCHBAR32_OR(IOCKTRR1, 1 << 9); + mchbar32_or(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32_OR(DACGIOCTRL1, 3 << 25); + mchbar32_or(DACGIOCTRL1, 3 << 25); } MCHBAR32(CICTRL) = 0xc6db8b5f; MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); - MCHBAR32_OR(DACGIOCTRL1, 1 << 5); + mchbar32_unset(DACGIOCTRL1, 0x000000ff); + mchbar32_or(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ pci_write_config8(GMCH_IGD, 0xf4, 0x4c); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index ec4152f..025070a 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -33,16 +33,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 2248d03..67f0a29 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -501,7 +501,7 @@ if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32_OR(PMSTS, 1); + mchbar32_or(PMSTS, 1); reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -566,7 +566,7 @@ MCHBAR32(HMCCPEXT) = 0; MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; - MCHBAR32_OR(HMCCMC, 1 << 7); + mchbar32_or(HMCCMC, 1 << 7); if ((fsb_freq == 0) && (ddr_freq == 1)) { MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; @@ -616,8 +616,8 @@ u8 ddr_freq; u16 mpll_ctl; - MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); - MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); + mchbar16_unset(CSHRMISCCTL1, (1 << 8)); + mchbar8_unset(CSHRMISCCTL1, 0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { ddr_freq = 0; @@ -627,10 +627,10 @@ mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); + mchbar16_unset_and_set(MPLLCTL, 0x033f, mpll_ctl); MCHBAR32(C0GNT2LNCH1) = 0x58001117; - MCHBAR32_OR(C0STATRDCTRL, 1 << 23); + mchbar32_or(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ @@ -682,7 +682,7 @@ flag = 1; } - MCHBAR8_OR(C0PVCFG, 0x03); + mchbar8_or(C0PVCFG, 0x03); MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; @@ -699,7 +699,7 @@ /* FIXME: Only applies to DDR2 */ reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; - MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); + mchbar16_unset_and_set(SHCYCTRKCKEL, 0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; MCHBAR16(C0CYCTRKWR) = reg16; @@ -714,10 +714,10 @@ MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); - MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + mchbar16_unset_and_set(C0CKECTRL, 0x03fe, 100 << 1); + mchbar8_unset_and_set(C0CYCTRKPCHG2, 0x3f, s->selected_timings.tRAS); MCHBAR16(C0ARBCTRL) = 0x2310; - MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); + mchbar8_unset_and_set(C0ADDCSCTRL, 0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -730,7 +730,7 @@ reg2 = 5000; } reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); + mchbar16_unset_and_set(C0STATRDCTRL, 0x1f00, reg16); flag = 0; if (wl > 2) { @@ -739,13 +739,13 @@ reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); + mchbar16_unset_and_set(C0WRDATACTRL, 0x01ff, reg16); MCHBAR16(C0RDQCTRL) = 0x1585; - MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + mchbar8_unset(C0PWLRCTRL, 0x1f); /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ - MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); + mchbar16_unset_and_set(C0PWLRCTRL, 0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg16 = 0x0514; @@ -754,115 +754,115 @@ reg16 = 0x0618; reg32 = 0x0c30; } - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); + mchbar32_unset_and_set(C0REFRCTRL2, 0x0fffff00, (0x3f << 22) | (reg32 << 8)); /* FIXME: Is this weird access necessary? Reference code does it */ MCHBAR8(C0REFRCTRL + 3) = 0; - MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + mchbar16_unset_and_set(C0REFCTRL, 0x3fff, reg16); /* NPUT Static Mode */ - MCHBAR8_OR(C0DYNRDCTRL, 1); + mchbar8_or(C0DYNRDCTRL, 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); + mchbar32_unset_and_set(C0STATRDCTRL, 0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32_OR(C0STATRDCTRL, 1 << 24); + mchbar32_or(C0STATRDCTRL, 1 << 24); } - MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); - MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); + mchbar8_unset(C0RDFIFOCTRL, 0x3); + mchbar16_unset_and_set(C0WRDATACTRL, 0x7c00, (wl + 10) << 10); + mchbar32_unset_and_set(C0CKECTRL, 0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); + mchbar16_unset_and_set(C0REFRCTRL + 4, 0x7fff, reg16); reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); - MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); - MCHBAR8_AND(C0JEDEC, ~(1 << 7)); - MCHBAR8_AND(C0DYNRDCTRL, ~0x6); + mchbar32_unset_and_set(C0REFRCTRL2, 0x30000000, reg32 << 8); + mchbar8_unset_and_set(C0REFRCTRL + 3, 0xfa, reg32 >> 24); + mchbar8_unset(C0JEDEC, (1 << 7)); + mchbar8_unset(C0DYNRDCTRL, 0x6); /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; MCHBAR32(C0WRWMFLSH) = reg32; - MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); - MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + mchbar16_unset_and_set(C0WRWMFLSH + 4, 0x1ff, (8 << 3) | (6 >> 2)); + mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5)); /* FIXME: Why not do a single word write? */ - MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); - MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); - MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + mchbar8_unset_and_set(SHPAGECTRL, 0xff, 0x40); + mchbar8_unset_and_set(SHPAGECTRL + 1, 0x07, 0x05); + mchbar8_or(SHCMPLWRCMD, 0x1f); reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); - MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); - MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + mchbar8_unset_and_set(SHBONUSREG, 0xdf, reg8); + mchbar8_unset(CSHRWRIOMLNS, 0x02); + mchbar8_unset_and_set(C0MISCTM, 0x07, 0x02); + mchbar16_unset_and_set(C0BYPCTRL, 0x3fc, 4 << 2); /* [31..29] = 0b010 for kN = 2 (2N) */ reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + mchbar32_unset_and_set(WRWMCONFIG, 0xffb00000, reg32); reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); - MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + mchbar8_unset_and_set(BYPACTSF, 0xf0, reg8 << 4); reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); - MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + mchbar8_unset_and_set(BYPACTSF, 0x0f, reg8); /* FIXME: Why not clear everything at once? */ - MCHBAR8_AND(BYPKNRULE, ~0xfc); - MCHBAR8_AND(BYPKNRULE, ~0x03); - MCHBAR8_AND(SHBONUSREG, ~0x03); - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); + mchbar8_unset(BYPKNRULE, 0xfc); + mchbar8_unset(BYPKNRULE, 0x03); + mchbar8_unset(SHBONUSREG, 0x03); + mchbar8_or(C0BYPCTRL, 1); + mchbar16_or(CSHRMISCCTL1, 1 << 9); for (i = 0; i < 8; i++) { /* FIXME: Hardcoded for DDR2 SO-DIMMs */ - MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); + mchbar32_unset_and_set(C0DLLRCVCTLy(i), 0x3f3f3f3f, 0x0c0c0c0c); } /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, (s->selected_timings.CAS + 1) << 16); /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); - MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); + mchbar8_unset(C0RXRCVyDLL(i), 0x3f); + mchbar16_unset(C0RCVMISCCTL2, (u16) (3 << (i * 2))); + mchbar16_unset(C0RCVMISCCTL1, (u16) (3 << (i * 2))); + mchbar16_unset(C0COARSEDLY0, (u16) (3 << (i * 2))); } - MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ - MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ - MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ - MCHBAR32_OR(C0COREBONUS, 0x000c0400); - MCHBAR32_OR(C0CMDTX1, 1 << 31); + mchbar8_unset(C0DLLPIEN, 1); /* Power up receiver */ + mchbar8_or(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + mchbar8_or(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + mchbar32_or(C0COREBONUS, 0x000c0400); + mchbar32_or(C0CMDTX1, 1 << 31); } /* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16_AND_OR(C0CKTX, ~0xc440, + mchbar32_unset_and_set(0x400*ch + 0x59c, 0x3300000, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | (pll->dbsel[f][i] << 6)); - MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); + mchbar8_unset_and_set(C0TXCK0DLL, 0x3f, pll->pi[f][i]); } /* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { /* FIXME: This is actually a dword write! */ - MCHBAR16_AND_OR(C0CKTX, ~0x00030880, + mchbar32_unset_and_set(0x400*ch + 0x5a0, 0x30880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | (pll->dbsel[f][i] << 7)); - MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); + mchbar8_unset_and_set(C0TXCK1DLL, 0x3f, pll->pi[f][i]); } /* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -872,14 +872,14 @@ /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); + mchbar8_unset_and_set(C0CMDTX1, 0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); + mchbar8_unset_and_set(C0CMDTX2, 0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCMD0DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCMD1DLL, 0x3f, reg8); } /* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -895,11 +895,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); + mchbar32_unset_and_set(C0CTLTX2, 0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL0DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL1DLL, 0x3f, reg8); /* CTRL2 and CTRL3 */ reg32 = ((u32) pll->dbsel[f][i]) << 12; @@ -908,11 +908,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); + mchbar32_unset_and_set(C0CMDTX2, 0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL2DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL3DLL, 0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -934,11 +934,11 @@ & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + mchbar16_unset_and_set(0x400*i + 0x590, 0xffff, reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXDQS0R0DLL + j, 0x3f, reg8); } static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) @@ -960,10 +960,10 @@ & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); + mchbar32_unset_and_set(C0DQSDQRyTX3(rank), (1 << (dq * 2+1)) | (1 << (dq * 2)), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXDQ0R0DLL + j, 0x3f, reg8); } /* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ @@ -1054,8 +1054,8 @@ } /* Disable Dynamic DQS Slave Setting Per Rank */ - MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); - MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); + mchbar8_unset(CSHRDQSCMN, (1 << 7)); + mchbar16_unset_and_set(CSHRPDCTL4, 0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); @@ -1078,13 +1078,13 @@ s->async = 0; reg8 = 0; - MCHBAR16_OR(CSHRPDCTL, 1 << 15); - MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); - MCHBAR8_OR(CSHRPDCTL, 1 << 3); - MCHBAR8_OR(CSHRPDCTL, 1 << 2); + mchbar16_or(CSHRPDCTL, 1 << 15); + mchbar8_unset(CSHRPDCTL, (1 << 7)); + mchbar8_or(CSHRPDCTL, 1 << 3); + mchbar8_or(CSHRPDCTL, 1 << 2); /* Start hardware HMC calibration */ - MCHBAR8_OR(CSHRPDCTL, 1 << 7); + mchbar8_or(CSHRPDCTL, 1 << 7); /* Busy-wait until calibration is done */ while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) @@ -1109,80 +1109,80 @@ } else { reg32 = 0x00014221; } - MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); - MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); + mchbar32_unset_and_set(CSHRMSTRCTL1, 0x0fffffff, reg32); + mchbar32_or(CSHRMSTRCTL1, 1 << 23); + mchbar32_or(CSHRMSTRCTL1, 1 << 15); + mchbar32_unset(CSHRMSTRCTL1, (1 << 15)); if (s->nodll) { /* Disable the Master DLLs by setting these bits, IN ORDER! */ - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); + mchbar16_or(CSHRMSTRCTL0, 1 << 0); + mchbar16_or(CSHRMSTRCTL0, 1 << 2); + mchbar16_or(CSHRMSTRCTL0, 1 << 4); + mchbar16_or(CSHRMSTRCTL0, 1 << 8); + mchbar16_or(CSHRMSTRCTL0, 1 << 10); + mchbar16_or(CSHRMSTRCTL0, 1 << 12); + mchbar16_or(CSHRMSTRCTL0, 1 << 14); } else { /* Enable the Master DLLs by clearing these bits, IN ORDER! */ - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 0)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 2)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 4)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 8)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 10)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 12)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 14)); } /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); + mchbar8_unset_and_set(CREFPI, 0x3f, 0x07); } else { - MCHBAR8_AND(CREFPI, ~0x3f); + mchbar8_unset(CREFPI, 0x3f); } sdram_calibratepll(s, 0); // XXX check /* Enable all modular Slave DLL */ - MCHBAR16_OR(C0DLLPIEN, 1 << 11); - MCHBAR16_OR(C0DLLPIEN, 1 << 12); + mchbar16_or(C0DLLPIEN, 1 << 11); + mchbar16_or(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); + mchbar16_or(C0DLLPIEN, (1 << 10) >> i); } /* Enable DQ/DQS output */ - MCHBAR8_OR(C0SLVDLLOUTEN, 1); + mchbar8_or(C0SLVDLLOUTEN, 1); MCHBAR16(CSPDSLVWT) = 0x5005; - MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); - MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); + mchbar16_unset_and_set(CSHRPDCTL2, 0x1f1f, 0x051a); + mchbar16_unset_and_set(CSHRPDCTL5, 0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); + mchbar8_unset_and_set(CSHRPDCTL3, 0x7f, 0x6b); } else { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); + mchbar8_unset_and_set(CSHRPDCTL3, 0x7f, 0x55); sdram_calibratehwpll(s); } /* Disable Dynamic Diff Amp */ - MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); + mchbar32_unset(C0STATRDCTRL, (1 << 22)); /* Now, start initializing the transmit FIFO */ - MCHBAR8_AND(C0MISCCTL, ~0x02); + mchbar8_unset(C0MISCCTL, 0x02); /* Disable (gate) mdclk and mdclkb */ - MCHBAR8_OR(CSHWRIOBONUS, 0xc0); + mchbar8_or(CSHWRIOBONUS, 0xc0); /* Select mdmclk */ - MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + mchbar8_unset(CSHWRIOBONUS, (1 << 5)); /* Ungate mdclk */ - MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); - MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + mchbar8_unset_and_set(CSHWRIOBONUS, 0xc0, 1 << 6); + mchbar8_unset_and_set(CSHRFIFOCTL, 0x3f, 0x1a); /* Enable the write pointer count */ - MCHBAR8_OR(CSHRFIFOCTL, 1); + mchbar8_or(CSHRFIFOCTL, 1); /* Set the DDR3 Reset Enable bit */ - MCHBAR8_OR(CSHRDDR3CTL, 1); + mchbar8_or(CSHRDDR3CTL, 1); /* Configure DQS-DQ Transmit */ MCHBAR32(CSHRDQSTXPGM) = 0x00551803; @@ -1190,10 +1190,10 @@ reg8 = 0; /* Switch all clocks on anyway */ /* Enable clock groups depending on rank population */ - MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + mchbar32_unset_and_set(C0CKTX, 0x3f000000, reg8 << 24); /* Enable DDR command output buffers from core */ - MCHBAR8_AND(0x594, ~1); + mchbar8_unset(0x594, 1); reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { @@ -1208,7 +1208,7 @@ if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16_OR(C0CTLTX2, reg16); + mchbar16_or(C0CTLTX2, reg16); } /* Define a shorter name for these to make the lines fit in 96 characters */ @@ -1343,54 +1343,54 @@ FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); - MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + mchbar8_unset_and_set(C0RCOMPCTRLx(i), 1, reg8); + mchbar8_unset(C0RCOMPCTRLx(i), 2); reg16 = rcompslew; - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_unset_and_set(C0RCOMPCTRLx(i), 0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); + mchbar8_unset_and_set(C0DCOMPx(i), 0x03, rcompdelay[i]); if (i == 2) { /* FIXME: Why are we rewriting this? */ - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_unset_and_set(C0RCOMPCTRLx(i), 0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); + mchbar8_unset_and_set(C0DCOMPx(i), 0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + mchbar16_unset(C0SLEWBASEx(i), 0x7f7f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + mchbar16_unset(C0SLEWPULUTx(i), 0x3f3f); + mchbar16_unset(C0SLEWPULUTx(i) + 2, 0x3f3f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); + mchbar16_unset(C0SLEWPDLUTx(i), 0x3f3f); + mchbar16_unset(C0SLEWPDLUTx(i) + 2, 0x3f3f); } /* FIXME: Hardcoded */ - MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); - MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); + mchbar8_unset_and_set(C0ODTRECORDX, 0x3f, 0x36); + mchbar8_unset_and_set(C0DQSODTRECORDX, 0x3f, 0x36); FOR_EACH_RCOMP_GROUP(i) { - MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); - MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); - MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); - MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); - MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); - MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); + mchbar8_unset(C0RCOMPCTRLx(i), 0x60); + mchbar16_unset(C0RCOMPCTRLx(i) + 2, 0x0706); + mchbar16_unset(C0RCOMPOSVx(i), 0x7f7f); + mchbar16_unset(C0SCOMPOFFx(i), 0x3f3f); + mchbar16_unset(C0DCOMPOFFx(i), 0x1f1f); + mchbar8_unset(C0DCOMPOFFx(i) + 2, 0x1f); } - MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); + mchbar16_unset(C0ODTRECORDX, 0xffc0); + mchbar16_unset(C0ODTRECORDX + 2, 0x000f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + mchbar16_unset(C0DQSODTRECORDX, 0xffc0); + mchbar16_unset(C0DQSODTRECORDX + 2, 0x000f); FOR_EACH_RCOMP_GROUP(i) { MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; @@ -1400,24 +1400,24 @@ MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); + mchbar32_unset_and_set(DCMEASBUFOVR, 0x001f1f1f, 0x000c1219); /* FIXME: Why not do a single word write? */ - MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); - MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + mchbar16_unset_and_set(XCOMPSDR0BNS, 0x1f00, 0x1200); + mchbar8_unset_and_set(XCOMPSDR0BNS, 0x1f, 0x12); MCHBAR32(COMPCTRL3) = 0x007C9007; MCHBAR32(OFREQDELSEL) = rcomp1; MCHBAR16(XCOMPCMNBNS) = 0x1f7f; MCHBAR32(COMPCTRL2) = rcomp2; - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + mchbar16_unset_and_set(XCOMPDFCTRL, 0x0f, 1); MCHBAR16(ZQCALCTRL) = 0x0134; MCHBAR32(COMPCTRL1) = 0x4C293600; /* FIXME: wtf did these MRC guys smoke */ - MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); - MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); - MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + mchbar8_unset_and_set(COMPCTRL1 + 3, 0x44, (1 << 6) | (1 << 2)); + mchbar16_unset(XCOMPSDR0BNS, (1 << 13)); + mchbar8_unset(XCOMPSDR0BNS, (1 << 5)); FOR_EACH_RCOMP_GROUP(i) { /* FIXME: This should be an _AND_OR */ @@ -1426,7 +1426,7 @@ if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { /* Start COMP */ - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); /* Wait until COMP is done */ while ((MCHBAR8(COMPCTRL1) & 1) != 0) @@ -1442,55 +1442,55 @@ /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + mchbar16_unset_and_set(C0SLEWBASEx(i), 0x7f00, reg16); reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); + mchbar8_unset_and_set(C0SLEWBASEx(i), 0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); + mchbar8_unset_and_set(C0SLEWPULUTx(0) + i, 0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); + mchbar8_unset_and_set(C0SLEWPULUTx(2) + i, 0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); - MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); + mchbar8_unset_and_set(C0SLEWPULUTx(3) + i, 0x3f, rcomplut[j][6]); + mchbar8_unset_and_set(C0SLEWPULUTx(4) + i, 0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); - MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); + mchbar8_unset_and_set(C0SLEWPULUTx(5) + i, 0x3f, rcomplut[j][8]); + mchbar8_unset_and_set(C0SLEWPULUTx(6) + i, 0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); + mchbar8_unset_and_set(C0SLEWPDLUTx(0) + i, 0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); + mchbar8_unset_and_set(C0SLEWPDLUTx(2) + i, 0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); + mchbar8_unset_and_set(C0SLEWPDLUTx(3) + i, 0x3f, rcomplut[j][7]); + mchbar8_unset_and_set(C0SLEWPDLUTx(4) + i, 0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); + mchbar8_unset_and_set(C0SLEWPDLUTx(5) + i, 0x3f, rcomplut[j][9]); + mchbar8_unset_and_set(C0SLEWPDLUTx(6) + i, 0x3f, rcomplut[j][9]); } } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); } /* FIXME: The ODT tables are for DDR2 only! */ @@ -1565,24 +1565,24 @@ if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x100001); MCHBAR32(C0DRA01) = 0x00000001; MCHBAR32(C0DRB0) = 0x00020002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + mchbar32_unset_and_set(C0CKECTRL, 1, w260[s->dimm_config[0]]); MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; @@ -1651,10 +1651,10 @@ u32 reg32a, reg32b; ok = 0; - MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); - MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); + mchbar8_unset(XCOMPDFCTRL, (1 << 3)); + mchbar8_unset(COMPCTRL1, (1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1667,7 +1667,7 @@ reg32a |= (1 << 31) | (1 << 15); MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1680,7 +1680,7 @@ reg32 = jval << 3; reg32 |= rank * (1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); + mchbar8_unset_and_set(C0JEDEC, 0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1689,10 +1689,10 @@ static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); - MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); + mchbar32_or(C0CKECTRL, 1 << 27); + mchbar8_unset_and_set(C0JEDEC, 0x0e, NORMAL_OP_CMD); + mchbar8_unset(C0JEDEC, 0x30); + mchbar32_unset_and_set(C0REFRCTRL2, (3 << 30), 3 << 30); } } @@ -1758,12 +1758,12 @@ reg32 = 0; reg32 |= (4 << 13); reg32 |= (6 << 8); - MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); - MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar32_unset_and_set(C0DYNRDCTRL, 0x3ff00, reg32); + mchbar8_unset(C0DYNRDCTRL, (1 << 7)); + mchbar8_or(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); + mchbar8_unset_and_set(C0JEDEC, 0x0e, NORMAL_OP_CMD); + mchbar8_unset(C0JEDEC, 0x30); } else { sdram_zqcl(s); } @@ -1860,10 +1860,10 @@ reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + mchbar8_unset_and_set(C0CKECTRL + 2, 0xf0, reg8); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_OR(C0CKECTRL, 1); + mchbar8_or(C0CKECTRL, 1); } addr = C0DRB0; @@ -1884,9 +1884,9 @@ { u8 dqsmatches = 1; while (count--) { - MCHBAR8_AND(C0RSTCTL, ~2); + mchbar8_unset(C0RSTCTL, 2); hpet_udelay(1); - MCHBAR8_OR(C0RSTCTL, 2); + mchbar8_or(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1905,12 +1905,12 @@ { if (*medium < 3) { (*medium)++; - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, *coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, *medium << (lane * 2)); } } @@ -1929,8 +1929,8 @@ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8_AND(C0RSTCTL, ~0x0c); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); + mchbar8_unset(C0RSTCTL, 0x0c); + mchbar8_unset(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 0\n"); for (lane = 0; lane < maxlane; lane++) { @@ -1942,10 +1942,10 @@ pi = 0; medium = 0; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, medium << (lane * 2)); - MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + mchbar8_unset(C0RXRCVyDLL(lane), 0x3f); savecoarse = coarse; savemedium = medium; @@ -1954,7 +1954,7 @@ PRINTK_DEBUG("rcven 0.1\n"); // XXX comment out - // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); + // mchbar16_unset_and_set(C0RCVMISCCTL1, 3 << lane * 2, 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); @@ -1985,8 +1985,8 @@ PRINTK_DEBUG("rcven 0.3\n"); coarse = savecoarse; medium = savemedium; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; @@ -1997,12 +1997,12 @@ break; // } } - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_unset_and_set(C0RXRCVyDLL(lane), 0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_unset_and_set(C0RXRCVyDLL(lane), 0x3f, pi << s->pioffset); rcvenclock(&coarse, &medium, lane); if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { @@ -2012,7 +2012,7 @@ PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { coarse--; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; @@ -2039,10 +2039,10 @@ do { lane--; offset = lanecoarse[lane] - minlanecoarse; - MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + mchbar16_unset_and_set(C0COARSEDLY0, 3 << lane * 2, offset << (lane * 2)); } while (lane != 0); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, minlanecoarse << 16); s->coarsectrl = minlanecoarse; s->coarsedelay = MCHBAR16(C0COARSEDLY0); @@ -2050,14 +2050,14 @@ s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8_AND(C0RSTCTL, ~0x0e); - MCHBAR8_OR(C0RSTCTL, 0x02); - MCHBAR8_OR(C0RSTCTL, 0x04); - MCHBAR8_OR(C0RSTCTL, 0x08); + mchbar8_unset(C0RSTCTL, 0x0e); + mchbar8_or(C0RSTCTL, 0x02); + mchbar8_or(C0RSTCTL, 0x04); + mchbar8_or(C0RSTCTL, 0x08); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); - MCHBAR8_OR(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar8_unset(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } @@ -2137,20 +2137,20 @@ { u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8_OR(C0ADDCSCTRL, 1); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar8_or(C0ADDCSCTRL, 1); + mchbar8_or(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + mchbar32_unset_and_set(WRWMCONFIG, mask32, reg32); MCHBAR8(C0DITCTRL + 1) = 2; MCHBAR16(C0DITCTRL + 2) = 0x0804; MCHBAR16(C0DITCTRL + 4) = 0x2010; MCHBAR8(C0DITCTRL + 6) = 0x40; MCHBAR16(C0DITCTRL + 8) = 0x091c; MCHBAR8(C0DITCTRL + 10) = 0xf2; - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR8_OR(C0CWBCTRL, 1); - MCHBAR16_OR(C0ARBSPL, 0x0100); + mchbar8_or(C0BYPCTRL, 1); + mchbar8_or(C0CWBCTRL, 1); + mchbar16_or(C0ARBSPL, 0x0100); pci_or_config8(HOST_BRIDGE, 0xf0, 1); MCHBAR32(SBCTL) = 0x00000002; @@ -2208,14 +2208,14 @@ die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); - MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); + mchbar8_unset_and_set(CHDECMISC, 0xfc, reg8 & 0xfc); + mchbar32_unset(NOACFGBUSCTL, 0x80000000); MCHBAR32(HTBONUS0) = 0x0000000f; - MCHBAR8_OR(C0COREBONUS + 4, 1); + mchbar8_or(C0COREBONUS + 4, 1); - MCHBAR32_AND(HIT3, ~0x0e000000); - MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); + mchbar32_unset(HIT3, 0x0e000000); + mchbar32_unset_and_set(HIT4, 0x000c0000, 0x00040000); u32 clkcx[2][2][3] = { { @@ -2235,20 +2235,20 @@ MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; - MCHBAR8_AND(HIT4, ~0x02); + mchbar8_unset(HIT4, 0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8_AND(COMPCTRL1, ~0x02); + mchbar8_unset(COMPCTRL1, 0x02); while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16_AND(CSHRMISCCTL, ~0x3000); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); + mchbar16_unset(CSHRMISCCTL, 0x3000); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar16_unset_and_set(XCOMPDFCTRL, 0x0f, 0x09); - MCHBAR8_OR(COMPCTRL1, 0x82); + mchbar8_or(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2336,7 +2336,7 @@ } } - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); + mchbar16_unset_and_set(C0STATRDCTRL, 0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2346,26 +2346,26 @@ /* Thermal sensor */ MCHBAR8(TSC1) = 0x9b; - MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + mchbar32_unset_and_set(TSTTP, 0x00ffffff, 0x1d00); MCHBAR8(THERM1) = 0x08; MCHBAR8(TSC3) = 0x00; - MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); - MCHBAR8_AND_OR(THERM1, ~1, 1); - MCHBAR8_AND_OR(TCO, ~0x80, 0x80); + mchbar8_unset_and_set(TSC2, 0x0f, 0x04); + mchbar8_unset_and_set(THERM1, 1, 1); + mchbar8_unset_and_set(TCO, 0x80, 0x80); /* Clock gating */ - MCHBAR32_AND(PMMISC, ~0x00040001); - MCHBAR8_AND(SBCTL3 + 3, ~0x80); - MCHBAR8_AND(CISDCTRL + 3, ~0x80); - MCHBAR16_AND(CICGDIS, ~0x1fff); - MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); - MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); - MCHBAR8_AND(TSMISC, ~1); + mchbar32_unset(PMMISC, 0x00040001); + mchbar8_unset(SBCTL3 + 3, 0x80); + mchbar8_unset(CISDCTRL + 3, 0x80); + mchbar16_unset(CICGDIS, 0x1fff); + mchbar32_unset(SBCLKGATECTRL, 0x0001ffff); + mchbar16_unset(HICLKGTCTL, 0x03ff mchbar16_unset(HICLKGTCTL, 0x03ff mchbar16_unset(HICLKGTCTL, 0x03ff & 0x06); 0x06); 0x06); + mchbar32_unset_and_set(HTCLKGTCTL, 0xffffffff, 0x20); + mchbar8_unset(TSMISC, 1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + mchbar16_unset_and_set(CLOCKGATINGI, 0x07fc, 0x0040); + mchbar16_unset_and_set(CLOCKGATINGII, 0x0fff, 0x0d00); + mchbar16_unset(CLOCKGATINGIII, 0x0d80); MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ @@ -2378,15 +2378,15 @@ MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + mchbar16_unset_and_set(PMMSPMRES, 0x03ff, 0x00c8); else - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + mchbar16_unset_and_set(PMMSPMRES, 0x03ff, 0x0100); j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); - MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); - MCHBAR8_AND(PMBAK, ~0x02); + mchbar32_unset_and_set(PMCLKRC, 0x01fff37f, 0x10810700); + mchbar8_unset_and_set(PMPXPRC, 0x07, 1); + mchbar8_unset(PMBAK, 0x02); static const u16 ddr2lut[2][4][2] = { { @@ -2406,8 +2406,8 @@ MCHBAR16(C0C2REG) = 0x7a89; MCHBAR8(SHC2REGII) = 0xaa; MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + mchbar16_unset_and_set(SHC2REGI, 0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + mchbar16_unset_and_set(CLOCKGATINGIII, 0xf000, 0xf000); MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); reg32 = s->nodll ? 0x30000000 : 0; @@ -2415,72 +2415,72 @@ /* FIXME: Compacting this results in changes to the binary */ MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); - MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); - MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + mchbar32_unset_and_set(CLOCKGATINGI, 0x00f00000, 0x00f00000); + mchbar32_unset_and_set(CLOCKGATINGII - 1, 0x001ff000, 0xbf << 20); + mchbar16_unset_and_set(SHC3C4REG2, 0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); MCHBAR16(SHC3C4REG3) = 0x3264; - MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + mchbar16_unset_and_set(SHC3C4REG4, 0x3f3f, (0x14 << 8) | 0x0a); - MCHBAR32_OR(C1COREBONUS, 0x80002000); + mchbar32_or(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + mchbar16_unset_and_set(CLOCKGATINGII, 0x03ff, 0x0100); + mchbar16_unset_and_set(CLOCKGATINGIII, 0x003f, 0x0010); + mchbar16_unset_and_set(CLOCKGATINGI, 0x7000, 0x2000); - MCHBAR8_AND(CSHRPDCTL, ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); - MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + mchbar8_unset(CSHRPDCTL, 0x0e); + mchbar8_unset(CSHRWRIOMLNS, 0x0c); + mchbar8_unset(C0MISCCTLy(0), 0x0e); + mchbar8_unset(C0MISCCTLy(1), 0x0e); + mchbar8_unset(C0MISCCTLy(2), 0x0e); + mchbar8_unset(C0MISCCTLy(3), 0x0e); + mchbar8_unset(C0MISCCTLy(4), 0x0e); + mchbar8_unset(C0MISCCTLy(5), 0x0e); + mchbar8_unset(C0MISCCTLy(6), 0x0e); + mchbar8_unset(C0MISCCTLy(7), 0x0e); + mchbar8_unset(CSHRWRIOMLNS, 0x02); - MCHBAR16_AND(CSHRMISCCTL, ~0x0400); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); - MCHBAR8_AND(C0WRDPYN, ~0x80); - MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); - MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); - MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + mchbar16_unset(CSHRMISCCTL, 0x0400); + mchbar16_unset(CLOCKGATINGIII, 0x0dc0); + mchbar8_unset(C0WRDPYN, 0x80); + mchbar32_unset(C0COREBONUS, (1 << 22)); + mchbar16_unset(CLOCKGATINGI, 0x80fc); + mchbar16_unset(CLOCKGATINGII, 0x0c00); - MCHBAR8_AND(CSHRPDCTL, ~0x0d); - MCHBAR8_AND(C0MISCCTLy(0), ~1); - MCHBAR8_AND(C0MISCCTLy(1), ~1); - MCHBAR8_AND(C0MISCCTLy(2), ~1); - MCHBAR8_AND(C0MISCCTLy(3), ~1); - MCHBAR8_AND(C0MISCCTLy(4), ~1); - MCHBAR8_AND(C0MISCCTLy(5), ~1); - MCHBAR8_AND(C0MISCCTLy(6), ~1); - MCHBAR8_AND(C0MISCCTLy(7), ~1); + mchbar8_unset(CSHRPDCTL, 0x0d); + mchbar8_unset(C0MISCCTLy(0), 1); + mchbar8_unset(C0MISCCTLy(1), 1); + mchbar8_unset(C0MISCCTLy(2), 1); + mchbar8_unset(C0MISCCTLy(3), 1); + mchbar8_unset(C0MISCCTLy(4), 1); + mchbar8_unset(C0MISCCTLy(5), 1); + mchbar8_unset(C0MISCCTLy(6), 1); + mchbar8_unset(C0MISCCTLy(7), 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); - MCHBAR32_AND(C0COREBONUS, ~0x00100000); - MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); - MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); - MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); - MCHBAR16_OR(C0STATRDCTRL, 0x6000); - MCHBAR32_OR(C0CKECTRL, 0x00010000); - MCHBAR8_OR(C0COREBONUS, 0x10); - MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); - MCHBAR8_OR(CSHWRIOBONUS, 0x07); - MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); - MCHBAR8_OR(SHC2REGIII, 7); - MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); - MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); - MCHBAR16_OR(C0COREBONUS, 0x01e0); - MCHBAR8_OR(CSHWRIOBONUS, 0x18); - MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); - MCHBAR16_OR(SHC3C4REG1, 0x0a3f); - MCHBAR8_OR(C0STATRDCTRL, 3); - MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); - MCHBAR8_AND(C0COREBONUS + 4, ~0x60); - MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); + mchbar32_unset_and_set(C0STATRDCTRL, 0x00700000, 3 << 20); + mchbar32_unset(C0COREBONUS, 0x00100000); + mchbar8_or(C0DYNSLVDLLEN, 0x1e); + mchbar8_or(C0DYNSLVDLLEN2, 0x03); + mchbar32_unset_and_set(SHCYCTRKCKEL, 0x0c000000, 0x04000000); + mchbar16_or(C0STATRDCTRL, 0x6000); + mchbar32_or(C0CKECTRL, 0x00010000); + mchbar8_or(C0COREBONUS, 0x10); + mchbar32_or(CLOCKGATINGI - 1, 0xf << 24); + mchbar8_or(CSHWRIOBONUS, 0x07); + mchbar8_or(C0DYNSLVDLLEN, 0xc0); + mchbar8_or(SHC2REGIII, 7); + mchbar16_unset_and_set(SHC2MINTM, 0xffff, 0x0080); + mchbar8_unset_and_set(SHC2IDLETM, 0xff, 0x10); + mchbar16_or(C0COREBONUS, 0x01e0); + mchbar8_or(CSHWRIOBONUS, 0x18); + mchbar8_or(CSHRMSTDYNDLLENB, 0x0d); + mchbar16_or(SHC3C4REG1, 0x0a3f); + mchbar8_or(C0STATRDCTRL, 3); + mchbar8_unset_and_set(C0REFRCTRL2, 0xff, 0x4a); + mchbar8_unset(C0COREBONUS + 4, 0x60); + mchbar16_or(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2540,13 +2540,13 @@ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); + mchbar32_unset(C0COREBONUS, (1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32_OR(C0COREBONUS, 1 << 23); + mchbar32_or(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } @@ -2555,10 +2555,10 @@ MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8_OR(CLOCKGATINGI, 3); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); - MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); - MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); + mchbar8_or(CLOCKGATINGI, 3); + mchbar16_unset_and_set(CLOCKGATINGIII, 0xf000, pimdclk << 12); + mchbar8_unset_and_set(CSHWRIOBONUSX, 0x77, (push << 4) | push); + mchbar32_unset_and_set(C0COREBONUS, 0x0f000000, 0x03000000); } /** @@ -2591,7 +2591,7 @@ /* Enable HPET */ enable_hpet(); - MCHBAR16_OR(CPCTL, 1 << 15); + mchbar16_or(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2626,16 +2626,16 @@ PRINTK_DEBUG("Done mmap\n"); /* Enable DDR IO buffer */ - MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); - MCHBAR8_OR(C0RSTCTL, 1); + mchbar8_unset_and_set(C0IOBUFACTCTL, 0x3f, 0x08); + mchbar8_or(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8_OR(HIT4, 2); + mchbar8_or(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); + mchbar32_or(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2648,7 +2648,7 @@ PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0REFRCTRL2, 3 << 30); + mchbar32_or(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2679,7 +2679,7 @@ PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32_OR(C0REFRCTRL2, 1 << 30); + mchbar32_or(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633d944b6171902e1c28de634341cd6001ba6f16 Gerrit-Change-Number: 46282 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/intel/cannonlake: Add i915_gpu_controller_info
by Jeremy Soller (Code Review) 16 Jan '21

16 Jan '21

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43616 ) Change subject: soc/intel/cannonlake: Add i915_gpu_controller_info ...................................................................... soc/intel/cannonlake: Add i915_gpu_controller_info This adds the i915_gpu_controller_info struct to chip.h and implements intel_igd_get_controller_info. Due to conflicts with the GMA driver ACPI, gfx.asl had to be commented out. I believe gfx.asl should be removed, but would like to hear alternatives. Tested on system76/lemp9 - ACPI backlight control was verified. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/graphics.c 4 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43616/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..e6d330a 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += fsp_params.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 12269d3..9cdd3b5 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include "gfx.asl" +//TODO: fix inclusion when using gma ACPI #include "gfx.asl" /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2923efc..3457f4d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include <intelblocks/cfg.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -478,6 +479,9 @@ * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 0000000..fda4998 --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *device) +{ + struct soc_intel_cannonlake_config *chip = device->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e Gerrit-Change-Number: 43616 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: soc/intel/xeon_sp/acpi: Remove southcluster.asl
by Marc Jones (Code Review) 15 Jan '21

15 Jan '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45835 ) Change subject: soc/intel/xeon_sp/acpi: Remove southcluster.asl ...................................................................... soc/intel/xeon_sp/acpi: Remove southcluster.asl Remove the non-built southcluster.asl file. The asl is duplicated in iiostack.asl and uncore_irq.asl. Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- D src/soc/intel/xeon_sp/acpi/southcluster.asl 1 file changed, 0 insertions(+), 235 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45835/1 diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl deleted file mode 100644 index effed43..0000000 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ /dev/null @@ -1,235 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/iomap.h> - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfeafffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, - 0x6EB00000,,, PMEM) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, - 0x00100000,,, APIC) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, - 0x00100000,,, PCHR) - - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000380000000000, // Range Minimum - 0x0000383FFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000004000000000, // Length - ,,, AddressRangeMemory, TypeStatic) -}) - -Method (_CRS, 0, Serialized) { - Return (MCRS) -} - -Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - - -Name (AR00, Package() { - // [DMI0]: Legacy PCI Express Port 0 on PCI0 - Package() { 0x0000FFFF, 0, 0, 47 }, - // [BR1A]: PCI Express Port 1A on PCI0 - // [BR1B]: PCI Express Port 1B on PCI0 - Package() { 0x0001FFFF, 0, 0, 47 }, - // [BR2A]: PCI Express Port 2A on PCI0 - // [BR2B]: PCI Express Port 2B on PCI0 - // [BR2C]: PCI Express Port 2C on PCI0 - // [BR2D]: PCI Express Port 2D on PCI0 - Package() { 0x0002FFFF, 0, 0, 47 }, - // [BR3A]: PCI Express Port 3A on PCI0 - // [BR3B]: PCI Express Port 3B on PCI0 - // [BR3C]: PCI Express Port 3C on PCI0 - // [BR3D]: PCI Express Port 3D on PCI0 - Package() { 0x0003FFFF, 0, 0, 47 }, - // [CB0A]: CB3DMA on PCI0 - // [CB0E]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 0, 0, 31 }, - // [CB0B]: CB3DMA on PCI0 - // [CB0F]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 1, 0, 39 }, - // [CB0C]: CB3DMA on PCI0 - // [CB0G]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 2, 0, 31 }, - // [CB0D]: CB3DMA on PCI0 - // [CB0H]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 3, 0, 39 }, - // [IIM0]: IIOMISC on PCI0 - Package() { 0x0005FFFF, 0, 0, 16 }, - Package() { 0x0005FFFF, 1, 0, 17 }, - Package() { 0x0005FFFF, 2, 0, 18 }, - Package() { 0x0005FFFF, 3, 0, 19 }, - // [IID0]: IIODFX0 on PCI0 - Package() { 0x0006FFFF, 0, 0, 16 }, - Package() { 0x0006FFFF, 1, 0, 17 }, - Package() { 0x0006FFFF, 2, 0, 18 }, - Package() { 0x0006FFFF, 3, 0, 19 }, - // [XHCI]: xHCI controller 1 on PCH - Package() { 0x0014FFFF, 3, 0, 19 }, - // [HECI]: ME HECI on PCH - // [IDER]: ME IDE redirect on PCH - Package() { 0x0016FFFF, 0, 0, 16 }, - // [HEC2]: ME HECI2 on PCH - // [MEKT]: MEKT on PCH - Package() { 0x0016FFFF, 1, 0, 17 }, - // [GBEM]: GbE Controller VPRO - Package() { 0x0019FFFF, 0, 0, 20 }, - // [EHC2]: EHCI controller #2 on PCH - Package() { 0x001AFFFF, 2, 0, 18 }, - // [ALZA]: High definition Audio Controller - Package() { 0x001BFFFF, 0, 0, 22 }, - // [RP01]: Pci Express Port 1 on PCH - // [RP05]: Pci Express Port 5 on PCH - Package() { 0x001CFFFF, 0, 0, 16 }, - // [RP02]: Pci Express Port 2 on PCH - // [RP06]: Pci Express Port 6 on PCH - Package() { 0x001CFFFF, 1, 0, 17 }, - // [RP03]: Pci Express Port 3 on PCH - // [RP07]: Pci Express Port 7 on PCH - Package() { 0x001CFFFF, 2, 0, 18 }, - // [RP04]: Pci Express Port 4 on PCH - // [RP08]: Pci Express Port 8 on ICH - Package() { 0x001CFFFF, 3, 0, 19 }, - // [EHC1]: EHCI controller #1 on PCH - Package() { 0x001DFFFF, 2, 0, 18 }, - // [SAT1]: SATA controller 1 on PCH - // [SAT2]: SATA Host controller 2 on PCH - Package() { 0x001FFFFF, 0, 0, 16 }, - // [SMBS]: SMBus controller on PCH - // [TERM]: Thermal Subsystem on ICH - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 0, 0, 20 }, - Package() { 0x0011FFFF, 0, 0, 21 }, -}) - -// Socket 0 Root bridge -Method (_PRT, 0) { - Return (AR00) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Gerrit-Change-Number: 45835 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020