coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/stout: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 26 Jan '21

26 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46180 ) Change subject: mb/google/stout: Convert to ASL 2.0 syntax ...................................................................... mb/google/stout: Convert to ASL 2.0 syntax Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/stout/acpi/mainboard.asl M src/mainboard/google/stout/acpi/platform.asl M src/mainboard/google/stout/acpi/thermal.asl 3 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46180/1 diff --git a/src/mainboard/google/stout/acpi/mainboard.asl b/src/mainboard/google/stout/acpi/mainboard.asl index 6cbe92e..f8cbe21 100644 --- a/src/mainboard/google/stout/acpi/mainboard.asl +++ b/src/mainboard/google/stout/acpi/mainboard.asl @@ -9,14 +9,14 @@ Method (_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.HPLD, \LIDS) + \LIDS = \_SB.PCI0.LPCB.EC0.HPLD Return (\LIDS) } Method (_PSW, 1) { // Enable/Disable LID as a wake source - Store (Arg0, \_SB.PCI0.LPCB.EC0.HWLO) + \_SB.PCI0.LPCB.EC0.HWLO = Arg0 } } } diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl index 8220599..b3421d5 100644 --- a/src/mainboard/google/stout/acpi/platform.asl +++ b/src/mainboard/google/stout/acpi/platform.asl @@ -7,7 +7,7 @@ Method(_PTS,1) { // Notify EC to enter S3 - Store(0x01, \_SB.PCI0.LPCB.EC0.S3FG) + \_SB.PCI0.LPCB.EC0.S3FG = 0x01 } /* The _WAK method is called on system wakeup */ @@ -15,16 +15,16 @@ Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACPW, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACPW + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (NOT(\_SB.PCI0.LPCB.EC0.HPLD), Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = ~\_SB.PCI0.LPCB.EC0.HPLD + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.LID0, 0x80) } diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl index 2484332..72324d7 100644 --- a/src/mainboard/google/stout/acpi/thermal.asl +++ b/src/mainboard/google/stout/acpi/thermal.asl @@ -22,10 +22,10 @@ Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -51,21 +51,21 @@ Method (_TMP, 0, Serialized) { // Returns Higher of the two readings for CPU & VGA Temperature - If (LGreater (\_SB.PCI0.LPCB.EC0.TMP2, \_SB.PCI0.LPCB.EC0.TMP1)) + If (\_SB.PCI0.LPCB.EC0.TMP2 > \_SB.PCI0.LPCB.EC0.TMP1) { // CPU high temperature - Store (\_SB.PCI0.LPCB.EC0.TMP2, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TMP2 } Else { // VGA high temperature - Store (\_SB.PCI0.LPCB.EC0.TMP1, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TMP1 } // If temp less 35 or great then 115, set default 35 - If (Or (LLess (Local0, 35), LGreater (Local0, 115))) + If ((Local0 < 35) || (Local0 > 115)) { - Store (35, Local0) + Local0 = 35 } Return (CTOK (Local0)) -- To view, visit https://review.coreboot.org/c/coreboot/+/46180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978 Gerrit-Change-Number: 46180 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 26 Jan '21

26 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46166 ) Change subject: mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax ...................................................................... mb/gigabyte/ga-h61m-series: Convert to ASL 2.0 syntax Change-Id: Ibc7c1249e6d497a948d2c4b41e4d163d031d37f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46166/1 diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl index 2544617..ae4ef30 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl @@ -21,10 +21,10 @@ Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc7c1249e6d497a948d2c4b41e4d163d031d37f2 Gerrit-Change-Number: 46166 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/51nb/x210: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 26 Jan '21

26 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46074 ) Change subject: mb/51nb/x210: Convert to ASL 2.0 syntax ...................................................................... mb/51nb/x210: Convert to ASL 2.0 syntax Change-Id: I02bfc5207ef584bc259407b5bdb14fae4c470bcd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/acpi/ec.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46074/1 diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index 78e156c..581e1e7 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -45,10 +45,10 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACIN, \PWRS) + \PWRS = ACIN /* Initialize LID switch state */ - Store (LIDC, \LIDS) + \LIDS = LIDC } /* KEY_BRIGHTNESSUP */ @@ -72,14 +72,14 @@ /* AC event */ Method (_Q0D) { - Store (ACIN, \PWRS) + \PWRS = ACIN Notify (AC, 0x80) } /* Lid event */ Method (_Q0E) { - Store (LIDC, \LIDS) + \LIDS = LIDC Notify (LID0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02bfc5207ef584bc259407b5bdb14fae4c470bcd Gerrit-Change-Number: 46074 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44904 ) Change subject: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads Update microcode using a core specific semaphore. The SDM and most of the BWGs suggest doing this. Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44904/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..4c4de09 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -25,6 +25,7 @@ #include <symbols.h> #include <timer.h> #include <thread.h> +#include <lib.h> #include <security/intel/stm/SmmStm.h> @@ -97,6 +98,9 @@ uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; + uint32_t microcode_lock_ht; /* 1 special microcode locking for Intel HT CPUs */ + uint32_t apic_core_id_mask; + uint32_t hyperthreading_lock[CONFIG_MAX_CPUS/2]; } __packed; /* This also needs to match the assembly code for saved MSR encoding. */ @@ -216,6 +220,31 @@ sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); + sp->microcode_lock_ht = !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + if (sp->microcode_lock_ht) { + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + + sp->apic_core_id_mask = 1UL << log2_ceil(core_ids); + sp->apic_core_id_mask <<= log2_ceil(threads); + } else { + sp->apic_core_id_mask = 0; + } + memset(sp->hyperthreading_lock, 0, sizeof(sp->hyperthreading_lock)); } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..abf0549 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -3,6 +3,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> /* The SIPI vector is responsible for initializing the APs in the system. It @@ -33,6 +34,12 @@ .long 0 ap_count: .long 0 +apic_core_id_mask: +.long 0 +hyperthreading_lock: +.space CONFIG_MAX_CPUS/2 +microcode_lock_ht: +.long 0 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) #define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) @@ -115,6 +122,35 @@ test %edx, %edx jnz microcode_done + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + je load_microcode + + /* Get this CPU's LAPIC ID */ + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl (%esi), %ecx + shr $24, %ecx + + movl apic_core_id_mask, %eax + andl %eax, %ecx +1: + bt $0, %eax + jc 1f + shr $1, %eax + shr $1, %ecx + jmp 1b +1: + /* ecx now contains the core ID */ + movl $(hyperthreading_lock), %ebx + shl $2, %ecx + addl %ecx, %ebx + +lock_ht_semaphore: + /* Lock the core specific semaphore */ + lock bts $0, (%ebx) + jc lock_ht_semaphore + jmp load_microcode + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode @@ -136,6 +172,15 @@ wrmsr popa + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + jne 1f + + xor %eax, %eax + mov %eax, (%ebx) + je microcode_done + +1: /* Unconditionally unlock microcode loading. */ cmpl $0xffffffff, microcode_lock je microcode_done -- To view, visit https://review.coreboot.org/c/coreboot/+/44904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Gerrit-Change-Number: 44904 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mpinit/sipi_vector: Move code to C
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46821 ) Change subject: cpu/x86/mpinit/sipi_vector: Move code to C ...................................................................... cpu/x86/mpinit/sipi_vector: Move code to C Use a C helper function to do early x86 CPU init. The code is compiled without SSE and without optimizations. Use existing code to update microcode. Tested on Supermicro X11SSH: * The microcode is still updated on all core * All cores call into MPinit code Change-Id: Ib6c2ffa2ce8c42eee9f3fe8ec8cff933942207ca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S A src/cpu/x86/sipi_vector_c_handler.c M src/include/cpu/x86/mp.h 5 files changed, 150 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46821/1 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 66b1a68..54e2397 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -26,8 +26,11 @@ $(eval $(call create_class_compiler,sipi_vec,$(ARCH-$(TARGET_STAGE)-y))) sipi_vec-generic-ccopts = $(rmodule_$(ARCH-$(TARGET_STAGE)-y)-generic-ccopts) +sipi_vec-generic-ccopts += -mno-sse -O0 sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector.S +sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector_c_handler.c +sipi_vec-$(CONFIG_PARALLEL_MP) += $(top)/src/cpu/intel/microcode/microcode.c $(SIPI_DOTO): $$(sipi_vec-objs) $(COMPILER_RT_sipi_vec) $(LD_sipi_vec) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_sipi_vec) --whole-archive --start-group $(sipi_vec-objs) --no-whole-archive $(COMPILER_RT_sipi_vec) --end-group diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4870529..83d71190 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -83,29 +83,6 @@ int num_records; }; -/* This needs to match the layout in the .module_parametrs section. */ -struct sipi_params { - uint16_t gdtlimit; - uint32_t gdt; - uint16_t unused; - uint32_t idt_ptr; - uint32_t stack_top; - uint32_t stack_size; - uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ - uint32_t microcode_ptr; - uint32_t msr_table_ptr; - uint32_t msr_count; - uint32_t c_handler; - atomic_t ap_count; -} __packed; - -/* This also needs to match the assembly code for saved MSR encoding. */ -struct saved_msr { - uint32_t index; - uint32_t lo; - uint32_t hi; -} __packed; - /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ extern char _binary_sipi_vector_start[]; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..52ca6ba 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,10 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/cr.h> -#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> #include <arch/ram_segs.h> +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) +#define CR0_CLEAR_FLAGS \ + (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | CR0_MP) +#define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -34,11 +38,6 @@ ap_count: .long 0 -#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) -#define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) -#define CR0_CLEAR_FLAGS \ - (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | CR0_MP) - .text .code16 .global _start @@ -101,102 +100,13 @@ /* Save CPU number. */ mov %ecx, %esi - /* Determine if one should check microcode versions. */ - mov microcode_ptr, %edi - test %edi, %edi - jz microcode_done /* Bypass if no microde exists. */ + /* sipi_secondary_early_entry(ap_start_params), preserve proper stack alignment */ + sub $8, %esp + push %esi + leal ap_start_params, %eax + push %eax + call sipi_secondary_early_entry - /* Get the Microcode version. */ - mov $1, %eax - cpuid - mov $IA32_BIOS_SIGN_ID, %ecx - rdmsr - /* If something already loaded skip loading again. */ - test %edx, %edx - jnz microcode_done - - /* Determine if parallel microcode loading is allowed. */ - cmpl $0xffffffff, microcode_lock - je load_microcode - - /* Protect microcode loading. */ -lock_microcode: - lock bts $0, microcode_lock - jc lock_microcode - -load_microcode: - /* Load new microcode. */ - mov $IA32_BIOS_UPDT_TRIG, %ecx - xor %edx, %edx - mov %edi, %eax - /* The microcode pointer is passed in pointing to the header. Adjust - * pointer to reflect the payload (header size is 48 bytes). */ - add $48, %eax - pusha - wrmsr - popa - - /* Unconditionally unlock microcode loading. */ - cmpl $0xffffffff, microcode_lock - je microcode_done - - xor %eax, %eax - mov %eax, microcode_lock - -microcode_done: - /* - * Load MSRs. Each entry in the table consists of: - * 0: index, - * 4: value[31:0] - * 8: value[63:32] - */ - mov msr_table_ptr, %edi - mov msr_count, %ebx - test %ebx, %ebx - jz 1f - -#if CONFIG(X86_AMD_FIXED_MTRRS) - /* Allow modification of RdDram and WrDram bits */ - mov $SYSCFG_MSR, %ecx - rdmsr - or $SYSCFG_MSR_MtrrFixDramModEn, %eax - wrmsr -#endif - -load_msr: - mov (%edi), %ecx - mov 4(%edi), %eax - mov 8(%edi), %edx - wrmsr - add $12, %edi - dec %ebx - jnz load_msr - -#if CONFIG(X86_AMD_FIXED_MTRRS) - mov $SYSCFG_MSR, %ecx - rdmsr - and $~SYSCFG_MSR_MtrrFixDramModEn, %eax - wrmsr -#endif - -1: - /* Enable caching. */ - mov %cr0, %eax - and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax - mov %eax, %cr0 - -#if CONFIG(SSE) - /* Enable sse instructions. */ - mov %cr4, %eax - orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax - mov %eax, %cr4 -#endif - - /* c_handler(cpu_num), preserve proper stack alignment */ - sub $12, %esp - push %esi /* cpu_num */ - mov c_handler, %eax - call *%eax halt_jump: hlt jmp halt_jump diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c new file mode 100644 index 0000000..dab6c65 --- /dev/null +++ b/src/cpu/x86/sipi_vector_c_handler.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> +#include <arch/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/amd/mtrr.h> + +asmlinkage void sipi_secondary_early_entry(struct sipi_params *params, int cpu_num); + +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) + +static void sipi_update_microcode(struct sipi_params *params) +{ + /* Determine if one should check microcode versions. */ + if (!params->microcode_ptr) + return; + + /* Get the Microcode version. */ + const uint32_t rev = get_current_microcode_rev(); + + /* If something already loaded skip loading again. */ + if (rev) + return; + + /* Determine if parallel microcode loading is allowed. */ + if (params->microcode_lock != 0xffffffff) { + + /* Protect microcode loading. */ + asm volatile( + "\tlock_microcode:\n" + "\tlock bts $0, %0\n" + "\tjc lock_microcode\n" + : "=m"(params->microcode_lock) + : "m"(params->microcode_lock)); + } + + /* Load new microcode. */ + intel_microcode_load_unlocked((void *)((uintptr_t)params->microcode_ptr)); + + /* Unconditionally unlock microcode loading. */ + if (params->microcode_lock != 0xffffffff) + params->microcode_lock = 0; +} + +static void sipi_set_mtrrs(struct sipi_params *params) +{ + struct saved_msr *smsr; + if (!params->msr_count) + return; + + if (CONFIG(X86_AMD_FIXED_MTRRS)) { + msr_t msr; + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + } + + /* Load MSRs */ + smsr = (struct saved_msr *)params->msr_table_ptr; + for (size_t i = 0; i < params->msr_count; i++) { + msr_t msr = {.lo = smsr->lo, .hi = smsr->hi}; + wrmsr(smsr->index, msr); + } + + if (CONFIG(X86_AMD_FIXED_MTRRS)) { + msr_t msr; + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + } +} + +static void sipi_enable_caches(struct sipi_params *params) +{ + /* Enable caches */ + CRx_TYPE cr0 = read_cr0(); + cr0 &= ~(CR0_CLEAR_FLAGS_CACHE_ENABLE); + write_cr0(cr0); +} + +static void sipi_enable_sse(struct sipi_params *params) +{ + /* Enable sse instructions. */ + if (CONFIG(SSE)) { + CRx_TYPE cr4 = read_cr4(); + cr4 &= (CR4_OSFXSR | CR4_OSXMMEXCPT); + write_cr4(cr4); + } +} + +/* + * Early CPU bringup hook. + * - No Microcode has been loaded + * - Caches are disabled + * - SSE is disabled + * - MTRR haven't been set up + * + * You have been warned, expect the unexpected! + */ +asmlinkage void sipi_secondary_early_entry(struct sipi_params *params, int cpu_num) +{ + sipi_update_microcode(params); + sipi_set_mtrrs(params); + sipi_enable_caches(params); + sipi_enable_sse(params); + + void (*doit)(int) = (void (*)(int))params->c_handler; + doit(cpu_num); +} \ No newline at end of file diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b2704eb..75cbe26 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -143,4 +143,27 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* This needs to match the layout in the .module_parametrs section. */ +struct sipi_params { + uint16_t gdtlimit; + uint32_t gdt; + uint16_t unused; + uint32_t idt_ptr; + uint32_t stack_top; + uint32_t stack_size; + uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ + uint32_t microcode_ptr; + uint32_t msr_table_ptr; + uint32_t msr_count; + uint32_t c_handler; + atomic_t ap_count; +} __packed; + +/* This also needs to match the assembly code for saved MSR encoding. */ +struct saved_msr { + uint32_t index; + uint32_t lo; + uint32_t hi; +} __packed; + #endif /* _X86_MP_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c2ffa2ce8c42eee9f3fe8ec8cff933942207ca Gerrit-Change-Number: 46821 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: cpu/x86: Use class for sipi module
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46820 ) Change subject: cpu/x86: Use class for sipi module ...................................................................... cpu/x86: Use class for sipi module This removes the hardcoded single assembly file and allows to add more source files to the SIPI rmodule. This can be used to link C code for reusing existing code. Change-Id: I701eb340688e43591dfca77f55106c5b2f1a7735 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Makefile.inc M src/cpu/x86/Makefile.inc 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46820/1 diff --git a/Makefile.inc b/Makefile.inc index bf33f8b..6b015f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -93,7 +93,7 @@ ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_microcode verstage +classes-y := ramstage romstage bootblock decompressor postcar sipi_vec smm smmstub cpu_microcode verstage # Add a special 'all' class to add sources to all stages $(call add-special-class,all) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..66b1a68 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -23,10 +23,14 @@ ifeq ($(CONFIG_PARALLEL_MP),y) $(TARGET_STAGE)-srcs += $(SIPI_BIN).manual endif -rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S -$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ +$(eval $(call create_class_compiler,sipi_vec,$(ARCH-$(TARGET_STAGE)-y))) +sipi_vec-generic-ccopts = $(rmodule_$(ARCH-$(TARGET_STAGE)-y)-generic-ccopts) + +sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $$(sipi_vec-objs) $(COMPILER_RT_sipi_vec) + $(LD_sipi_vec) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_sipi_vec) --whole-archive --start-group $(sipi_vec-objs) --no-whole-archive $(COMPILER_RT_sipi_vec) --end-group $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) -- To view, visit https://review.coreboot.org/c/coreboot/+/46820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I701eb340688e43591dfca77f55106c5b2f1a7735 Gerrit-Change-Number: 46820 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/google/auron: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 25 Jan '21

25 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46169 ) Change subject: mb/google/auron: Convert to ASL 2.0 syntax ...................................................................... mb/google/auron: Convert to ASL 2.0 syntax Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/auron/acpi/mainboard.asl M src/mainboard/google/auron/acpi/thermal.asl M src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl 8 files changed, 60 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46169/1 diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 746efa2..1be0a47 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -19,8 +19,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_WLAN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_WLAN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index 4be4fe5..fd05e73 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -24,10 +24,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,56 +53,56 @@ Method (TCHK, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } Method (_TMP, 0, Serialized) { // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for EC to re-poll Sleep (1000) // Re-read temperature from EC - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) @@ -110,7 +110,7 @@ /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (CTL_TDP_THRESHOLD_OFF)) } Else { Return (CTOK (CTL_TDP_THRESHOLD_ON)) @@ -119,7 +119,7 @@ /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) } Else { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) @@ -132,14 +132,14 @@ PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 /* Enable Power Limit */ \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT) @@ -147,7 +147,7 @@ Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 /* Disable Power Limit */ \_SB.PCI0.MCHC.CTLD () @@ -159,18 +159,18 @@ PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index b3dc42c..4b0ac45 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -24,7 +24,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -59,7 +59,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -70,8 +70,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -96,7 +96,7 @@ { Store (BUDDY_NIC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl index febaffe..cc26de6 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl index 76e1f2e..35f0d3c 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl @@ -31,17 +31,17 @@ Method(_DSM, 0x4, NotSerialized) { - If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */ + If (Arg0 == ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")) /* I2C-HID UUID */ { - If (LEqual(Arg2, Zero)) /* DSM Function */ + If (Arg2 == 0) /* DSM Function */ { /* Function 0: Query function, return based on revision */ - If (LEqual(Arg1, One)) /* Arg1 DSM Revision */ + If (Arg1 == 1) /* Arg1 DSM Revision */ { /* Revision 1: Function 0 supported */ Return(Buffer(One) { 0x03 }) } - } ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */ + } ElseIf (Arg2 == 1) /* Function 1 : HID Function */ { Return(0x0020) /* HID Descriptor Address */ } @@ -52,7 +52,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -63,8 +63,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -100,7 +100,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -111,8 +111,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 4329d5f..9ca592f 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -30,8 +30,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -39,7 +39,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -141,8 +141,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -150,7 +150,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -188,8 +188,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -198,7 +198,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Gerrit-Change-Number: 46169 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Documentation: Add documentation on jenkins builders
by Martin Roth (Code Review) 25 Jan '21

25 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43984 ) Change subject: Documentation: Add documentation on jenkins builders ...................................................................... Documentation: Add documentation on jenkins builders Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 --- A Documentation/community/builders.md 1 file changed, 391 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43984/1 diff --git a/Documentation/community/builders.md b/Documentation/community/builders.md new file mode 100644 index 0000000..bc35bcc --- /dev/null +++ b/Documentation/community/builders.md @@ -0,0 +1,391 @@ +# Jenkins builder setup and configuration + +## How to set up a new jenkins builder + +### Contact a jenkins admin + +Let a jenkins admin know that you’re interested in setting up a jenkins +build system. + +For a permanent build system, this should generally be a dedicated +machine that is not generally being used for other purposes. The +coreboot builds are very intensive. + +It's also best to be aware that although we don't know of any security +issues, the jenkins-node image is run with the privileged flag which +gives the container root access to the build machine. See +[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-ru… +about why this is discouraged. + +It's recommended that you give an admin root access on your machine so +that they can reset it in case of a failure. This is not a requirement, +as the system can just be disabled until someone is available to fix any +issues. + +Currently active Jenkins admins: +* Patrick Georgi: + * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de) + * IRC: pgeorgi + + +### Build Machine requirements + +For a builder, we need a fast system with lots of threads and plenty of +RAM. The builder builds and stores the git repos and output in tmpfs +along with the ccache save area, so if there isn't enough memory, the +builds will slow down because of smaller ccache areas and can run into +"out of storage space" errors. + +#### Current Build Machines + +To give an idea of what a suitable build machine might be, currently the +coreboot project has 3 active jenkins build machines. + +* Congenialbuilder - 128 threads, 256GiB RAM + * Fastest Passing coreboot gerrit build: 4 min, 30 sec + * Slowest Passing coreboot gerrit build: 9 min, 56 sec + + +* Gleeful builder - 64 thread, 64GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 6 sec + * Slowest Passing coreboot gerrit build, 34 min + + +* Ultron (9elements) - 48 threads, 128GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 32 sec + * Slowest Passing coreboot gerrit build: 44 min + + +### Jenkins Builds + +There are a number of builds handled by the coreboot jenkins builders, +for a number of different projects - coreboot, flashrom, memtest86+, +em100, etc. Many of these have builders for their current master branch +as well as gerrit and coverity builds. + +You can see all the builds here: +[https://qa.coreboot.org/](https://qa.coreboot.org/) + +Most of the time on the builders is taken up by the coreboot master and +gerrit builds. + +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) + + +* [coreboot master build](https://qa.coreboot.org/job/coreboot/) + ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) + + +### Stress test the machine + +Test the machine to make sure that building won't stress the hardware +too much. Install stress-ng, then run the stress test for at least an +hour. + +On a system with 32 cores, it was tested with this command: + +``` +$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +``` + +You can watch the temperature with the sensors package or with ‘acpi -t’ +if your machine supports that. + +You can check for thermal throttling by running this command and seeing +if the values go down on any of the cores after it's been running for a +while. + +``` +$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +``` + +If the machine throttles or resets, you probably need to upgrade the +cooling system. + + +## jenkins-server docker installation + + +### Manual Installation + +If you’ve met all the above requirements, and an admin has agreed to set +up the builder in jenkins, you’re ready to go on to the next steps. + + +### Set up your network so jenkins can talk to the container + +Expose a local port through any firewalls you might have on your router. +This would generally be in the port forwarding section, and you'd just +forward a port (typically 49151) from the internet directly to the +builder’s IP address. + +You might also want to set up a port to forward to port 22 on your +machine and set up openssh so you can manage the machine remotely. + + +### Install and set up docker + +Install docker by following the directions on the docker site. These +instructions keep changing, so just check the latest information. + +[https://docs.docker.com/engine/install/](https://docs.docker.com/engine/install/) + + +#### Set up environment variables + +To make configuration and the later commands easier, these should go in +your shell's .rc file. Note that you only need to set them if you're +using something other than the default. + +``` +# Set the port used on your machine to connect to jenkins. +export COREBOOT_JENKINS_PORT=49151 + +# Set the revision of the container from docker hub +export DOCKER_COMMIT=65718760fa + +# Set the location of where the jenkins cache directory will be. +export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache" + +# Set the name of the container +export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins" +``` + +Make sure any variables needed are set in your environment before +continuing to the next step. + + +### Using the Makefile for docker installation + +From the coreboot directory, run + +``` +make -C util/docker help +``` + +This will show you the available targets and variables needed: + +``` +Commands for working with docker images: + coreboot-sdk - Build coreboot-sdk container + upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com + coreboot-jenkins-node - Build coreboot-jenkins-node container + upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com + doc.coreboot.org - Build doc.coreboot.org container + clean-coreboot-containers - Remove all docker coreboot containers + clean-coreboot-images - Remove all docker coreboot images + docker-clean - Remove docker coreboot containers & images + +Commands for using docker images + docker-build-coreboot - Build coreboot under coreboot-sdk + <BUILD_CMD=target> + docker-abuild - Run abuild under coreboot-sdk + <ABUILD_ARGS='-a -B'> + docker-what-jenkins-does - Run 'what-jenkins-does' target + docker-shell - Bash prompt in coreboot-jenkins-node + <USER=root or USER=coreboot> + docker-jenkins-server - Run coreboot-jenkins-node image (for server) + docker-jenkins-attach - Open shell in running jenkins server + docker-build-docs - Build the documentation + docker-livehtml-docs - Run sphinx-autobuild + +Variables: + COREBOOT_JENKINS_PORT=49151 + COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache + COREBOOT_JENKINS_CONTAINER=coreboot_jenkins + COREBOOT_IMAGE_TAG=f2741aa632f + DOCKER_COMMIT=65718760fa +``` + +### Set up the system for the jenkins builder + +As a regular user - *Not root*, run: + +``` +sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} +sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR} +wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar +mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR} +``` + +### Install the coreboot jenkins builder + +``` +make -C util/docker docker-jenkins-server +``` + +Your installation is complete on your side. + +### Tell the Admins that the machine is set up +Let the admins know that the builder is set up so they can set up the +machine profile on qa.coreboot.org. + +They need to know: +* Your external IP address or domain name. If you don’t have a static +IP, make sure you have a dynamic dns hostname configured. +* The port on your machine and firewall that’s exposed for jenkins: +`$COREBOOT_JENKINS_PORT` +* The core count of the machine. +* How much memory is available on the machine. This helps determine +the amount of memory used for ccache. + + +### First build +On the first build after a machine is reset, it will frequently take +20-25 minutes to do the entire what-jenkins-does build while the ccache +is getting filled up and the entire coreboot repo gets downloaded. As +the ccache gets populated, the build time will drop. + + +## Additional Information + + +### How to log in to the docker instance for debugging +``` + $ make -C util/docker docker-jenkins-attach + $ su coreboot + $ cd ~/slave-root/workspace + $ bash +``` + + +WARNING: This should not be used to make changes to the build system, +but just to debug issues. Changes to the build system are highly +discouraged as it leads to situations where patches can pass the build +testing on one builder and fail on another builder. Any changes that are +made in the image will be lost on the next update, so if you +accidentally change something, you can remove the containers and images +and update to get a fresh installation. + + +### How to download containers/images for a fresh installation and remove old containers + +To delete the old containers & images: + +``` +$ docker stop $COREBOOT_JENKINS_CONTAINER +$ docker rm $COREBOOT_JENKINS_CONTAINER +$ docker images # lists all existing images +$ docker rmi XXXX # Use the image ID found in the above command. +``` + +To get and run the new coreboot-jenkins image, change the value in the +`DOCKER_COMMIT` variable to the new image value. + +``` +$ make -C util/docker docker-jenkins-server +``` + +#### Getting ready to push the docker images + +Set up an account on hub.docker.com + +Get an admin to add the account to the coreboot team on hub.docker.com + +[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners) + +Make sure your credentials are configured on your host machine by +running + +``` +$ docker login +``` + +This will prompt you for your docker username, password, and your email +address, and write out to ~/.docker/config.json. Without this file, you +won’t be able to push the images. + +#### Updating the Dockerfiles: + +The coreboot-sdk Dockerfile will need to be updated when any additional +dependencies are added. Both the coreboot-sdk and the +coreboot-jenkins-node Dockerfiles will need to be updated to the new +version number and git commit id anytime the toolchain is updated. Both +files are stored in the coreboot repo under coreboot/util/docker. + +Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) +page before updating the files. + +#### Rebuilding the coreboot-sdk docker image to update the toolchain: + +``` +$ make -C util/docker coreboot-sdk +``` + +This takes a relatively long time. + +#### Test the coreboot-sdk docker image: + +There are two methods of running the docker image - interactively as a +shell, or doing the build directly. Running interactively as a shell is +useful for early testing, because it allows you to update the image +(without any changes getting saved) and re-test builds. This saves the +time of having to rebuild the image for every issue you find. + +#### Running the docker image interactively: + +Run: + +``` +$ make -C util/docker docker-jenkins-server +$ make -C util/docker docker-jenkins-attach +``` + +#### Running the build directly: + +From the coreboot directory: + +``` +$ make -C util/docker docker-build-coreboot +``` + +You’ll also want to test building the other projects and payloads: +ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, +nvramcui, tint... + +#### Pushing the coreboot-sdk image to hub.docker.com for use: + +When you’re satisfied with the testing, push the coreboot-sdk image to +the hub.docker.com + +``` +$ make -C util/docker upload-coreboot-sdk +``` + +#### Building and pushing the coreboot-jenkins-node docker image: + +This docker image is pretty simple, so there’s not really any testing +that needs to be done. + +``` +$ make -C util/docker coreboot-jenkins-node +$ make -C util/docker upload-coreboot-jenkins-node +``` + +### Coverity Setup + +To run coverity jobs, the builder needs to have the tools available, and +to be marked as a coverity builder. + + +#### Set up the Coverity tools + +Download the Linux-64 coverity build tool and decompress it into your +cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable + +[https://scan.coverity.com/download](https://scan.coverity.com/download) + +Rename the directory from its original name +(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a +symlink: + +``` +ln -s cov-analysis-linux64-7.7.0.4 coverity +``` + + +Let the admins know that the ‘coverity’ label can be added to the +builder. -- To view, visit https://review.coreboot.org/c/coreboot/+/43984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 Gerrit-Change-Number: 43984 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Drop enable check from LPD0/LPD3
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46966 ) Change subject: soc/intel/broadwell: Drop enable check from LPD0/LPD3 ...................................................................... soc/intel/broadwell: Drop enable check from LPD0/LPD3 When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL. Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 14 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46966/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 91fa758..b03bcdd 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -7,14 +7,8 @@ // Put SerialIO device in D0 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD0, 2, Serialized) +Method (LPD0, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -30,14 +24,8 @@ // Put SerialIO device in D3 state // Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD3, 2, Serialized) +Method (LPD3, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { @@ -240,12 +228,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1, \S1EN) + ^^LPD0 (\S1B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1, \S1EN) + ^^LPD3 (\S1B1) } } @@ -311,12 +299,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1, \S2EN) + ^^LPD0 (\S2B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1, \S2EN) + ^^LPD3 (\S2B1) } } @@ -367,12 +355,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1, \S3EN) + ^^LPD0 (\S3B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1, \S3EN) + ^^LPD3 (\S3B1) } } @@ -435,12 +423,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1, \S4EN) + ^^LPD0 (\S4B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1, \S4EN) + ^^LPD3 (\S4B1) } } @@ -503,12 +491,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1, \S5EN) + ^^LPD0 (\S5B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1, \S5EN) + ^^LPD3 (\S5B1) } } @@ -559,12 +547,12 @@ Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1, \S6EN) + ^^LPD0 (\S6B1) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1, \S6EN) + ^^LPD3 (\S6B1) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Gerrit-Change-Number: 46966 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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