coreboot-gerrit January 2020

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Change in coreboot[master]: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit
by Petr K (Code Review) 07 Aug '23

07 Aug '23

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37153 ) Change subject: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit ...................................................................... mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on ideas from 32500 Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/early_init.c 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37153/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e0436..2770937 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,28 @@ end end + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 74c8b60..d30a621 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -77,3 +78,12 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 Gerrit-Change-Number: 37153 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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Change in coreboot[master]: {northbridge,soc,southbridge}: Don't use both of _ADR and _HID
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37532 ) Change subject: {northbridge,soc,southbridge}: Don't use both of _ADR and _HID ...................................................................... {northbridge,soc,southbridge}: Don't use both of _ADR and _HID ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I48fb3e9e48893336416eb90f80957e5bd21d1711 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37532/1 diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985..4a48aaf 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48fb3e9e48893336416eb90f80957e5bd21d1711 Gerrit-Change-Number: 37532 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: New PCI ID for FCH SATA Controller (AHCI Mode)
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37546 ) Change subject: New PCI ID for FCH SATA Controller (AHCI Mode) ...................................................................... New PCI ID for FCH SATA Controller (AHCI Mode) The 1022:7904 FCH SATA Controller is found in the AMD Bettong board. Support is added to configure properly the SATA device in initialization. Change-Id: Id8e5d67cded0588e84ad81f7d5e6fa4b6907ebc9 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/sata/sata.c M src/southbridge/amd/pi/hudson/sata.c 3 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37546/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c05640f..6444bc1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -444,14 +444,15 @@ #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 #define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 -#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A -#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E -#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 -#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 -#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 -#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 -#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 -#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A +#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD 0x7904 +#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 +#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 +#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 +#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e #define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 5aa2088..1cd342e 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -30,6 +30,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 08e967d..77365ef 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -70,6 +70,7 @@ PCI_DEVICE_ID_AMD_SB900_SATA_AHCI, PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e5d67cded0588e84ad81f7d5e6fa4b6907ebc9 Gerrit-Change-Number: 37546 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37548 ) Change subject: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit ...................................................................... New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit The 1022:1577 IOMMU device is found in the AMD Bettong board. Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/iommu/iommu.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37548/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6444bc1..1276994 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -303,6 +303,7 @@ #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 18c8e66..c8b1ff7 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -47,6 +47,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Gerrit-Change-Number: 37548 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37589 to review the following change. Change subject: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf ...................................................................... mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf No need to configure the mem_strap in the early gpio block and again later. Fixes commit 5a0edcbde1537. BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37589/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375..4ebd258 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -119,14 +119,6 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : PCH_MEM_STRAP2 */ - PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/37589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Gerrit-Change-Number: 37589 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/hatch: Move GPP_A11 config into variants from baseboard
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37590 to review the following change. Change subject: mainboard/hatch: Move GPP_A11 config into variants from baseboard ...................................................................... mainboard/hatch: Move GPP_A11 config into variants from baseboard Not all Hatch variants have a FP reader and so the baseboard should not assume one is connected. Instead the baseboard defines A11 as NC unless the variant defines it otherwise by override. Also, kindred has no FP so fix that while we are here. BUG=b:144809606 BRANCH=hatch TEST=none Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37590/1 diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 4be3c34..0be39b7 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ @@ -98,8 +96,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 029aba16..2bc843e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -35,8 +35,8 @@ /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : SUSWARN_L */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d7..0b5d0de 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..def6ff0 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,6 +19,8 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 85eb3fc..89c6b41 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -23,6 +23,8 @@ PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa..bf94edb 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), /* F1 : NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 4ebd258..49798c3 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -25,6 +25,8 @@ PAD_NC(GPP_A6, NONE), /* A10 : GPP_A10 ==> NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d27554..814f2a6 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A22 : NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Gerrit-Change-Number: 37590 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37591 to review the following change. Change subject: mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs ...................................................................... mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs Hatch always used the default MEM_STRAPs in baseboard. Adding explicit configuration for the Hatch variant in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6f6cb0af2d159ba9532f413939b546526b64a935 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/hatch/gpio.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37591/1 diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..9aac509 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -20,7 +20,16 @@ static const struct pad_config gpio_table[] = { /* C13 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), +}; const struct pad_config *override_gpio_table(size_t *num) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6cb0af2d159ba9532f413939b546526b64a935 Gerrit-Change-Number: 37591 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37675 ) Change subject: drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig ...................................................................... drivers/intel/fsp2_0: honour FSP2_0_DISPLAY_LOGO Kconfig The FSP logo support should only compile if board selects FSP2_0_DISPLAY_LOGO Change-Id: Id92cc733562468a42ceee720861f5a1a4bcae9c3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37675/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ebdbdbf..8cd63f2 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -57,13 +57,11 @@ /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); -#if (CONFIG(HAVE_FSP_GOP)) - if (CONFIG(FSP2_0_DISPLAY_LOGO)) { +#if (CONFIG(FSP2_0_DISPLAY_LOGO)) upd->FspsConfig.LogoSize = 1 * MiB; logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize); upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry); load_logo(upd); - } #endif /* Call SiliconInit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id92cc733562468a42ceee720861f5a1a4bcae9c3 Gerrit-Change-Number: 37675 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/intel/common: Add config for intel common mainboard support
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37705 ) Change subject: mainboard/intel/common: Add config for intel common mainboard support ...................................................................... mainboard/intel/common: Add config for intel common mainboard support Add config to support intel mainboard common code. The intend is to create common placeholder for APIs common across the mainboard. Change-Id: Idc6f9bd298520f5e929534c64f1b038a4c9684a9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/intel/common/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37705/1 diff --git a/src/mainboard/intel/common/Kconfig b/src/mainboard/intel/common/Kconfig new file mode 100644 index 0000000..e96d943 --- /dev/null +++ b/src/mainboard/intel/common/Kconfig @@ -0,0 +1,5 @@ +config MAINBOARD_INTEL_COMMON + bool + help + common code for Intel Mainboards + -- To view, visit https://review.coreboot.org/c/coreboot/+/37705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc6f9bd298520f5e929534c64f1b038a4c9684a9 Gerrit-Change-Number: 37705 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/intel/common: Add some common board and memory APIs
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37707 ) Change subject: mainboard/intel/common: Add some common board and memory APIs ...................................................................... mainboard/intel/common: Add some common board and memory APIs Add support for below APIs in mainboard intel/common: 1. get_board_id: Returns board ID from EC. 2. get_spd_index: Returns SPD index from board ID. Change-Id: I40c9454b583d6bc0e3034f3400beb822124ba8f4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/intel/common/Makefile.inc A src/mainboard/intel/common/board/Makefile.inc A src/mainboard/intel/common/board/board_id.c A src/mainboard/intel/common/include/intel_mb/board_id.h A src/mainboard/intel/common/include/intel_mb/spd.h A src/mainboard/intel/common/memory/Makefile.inc A src/mainboard/intel/common/memory/spd.c 7 files changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37707/1 diff --git a/src/mainboard/intel/common/Makefile.inc b/src/mainboard/intel/common/Makefile.inc new file mode 100644 index 0000000..54bba3f --- /dev/null +++ b/src/mainboard/intel/common/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_MAINBOARD_INTEL_COMMON),y) + +subdirs-y += board/ +subdirs-y += memory/ + +CPPFLAGS_common += -I$(src)/mainboard/intel/common/include/ + +endif diff --git a/src/mainboard/intel/common/board/Makefile.inc b/src/mainboard/intel/common/board/Makefile.inc new file mode 100644 index 0000000..4781dfb --- /dev/null +++ b/src/mainboard/intel/common/board/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += board_id.c +ramstage-y += board_id.c + diff --git a/src/mainboard/intel/common/board/board_id.c b/src/mainboard/intel/common/board/board_id.c new file mode 100644 index 0000000..19897c2 --- /dev/null +++ b/src/mainboard/intel/common/board/board_id.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intel_mb/board_id.h> +#include <stdint.h> + +static int get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = get_board_id_via_ext_ec(); + else{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return id; +} diff --git a/src/mainboard/intel/common/include/intel_mb/board_id.h b/src/mainboard/intel/common/include/intel_mb/board_id.h new file mode 100644 index 0000000..9aac527 --- /dev/null +++ b/src/mainboard/intel/common/include/intel_mb/board_id.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +#include <stdint.h> + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/common/include/intel_mb/spd.h b/src/mainboard/intel/common/include/intel_mb/spd.h new file mode 100644 index 0000000..3f834b8 --- /dev/null +++ b/src/mainboard/intel/common/include/intel_mb/spd.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_SPD_H_ +#define _MAINBOARD_COMMON_SPD_H_ + +#include <stdint.h> + +/* Returns SPD index from board ID */ +uint8_t get_spd_index(void); + +#endif /* _MAINBOARD_COMMON_SPD_H_ */ diff --git a/src/mainboard/intel/common/memory/Makefile.inc b/src/mainboard/intel/common/memory/Makefile.inc new file mode 100644 index 0000000..c0e5f53 --- /dev/null +++ b/src/mainboard/intel/common/memory/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += spd.c + diff --git a/src/mainboard/intel/common/memory/spd.c b/src/mainboard/intel/common/memory/spd.c new file mode 100644 index 0000000..5da5bf4 --- /dev/null +++ b/src/mainboard/intel/common/memory/spd.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intel_mb/board_id.h> +#include <intel_mb/spd.h> +#include <stdint.h> + +uint8_t get_spd_index(void) +{ + return get_board_id() & 0x7; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c9454b583d6bc0e3034f3400beb822124ba8f4 Gerrit-Change-Number: 37707 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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