coreboot-gerrit September 2019

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Change in coreboot[master]: mb/ocp/monolake: Implement bank/locator scheme
by Martin Roth (Code Review) 21 Sep '19

21 Sep '19

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35319 ) Change subject: mb/ocp/monolake: Implement bank/locator scheme ...................................................................... mb/ocp/monolake: Implement bank/locator scheme Implement Locator and Bank fields (as reported by dmidecode) to match vendor BIOS. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/ocp/monolake/mainboard.c 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index 9755b06..010e064 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -17,6 +17,8 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <cf9_reset.h> +#include <smbios.h> +#include <string.h> #include "ipmi.h" /* @@ -39,3 +41,17 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + + char locator[64] = {0}; + + snprintf(locator, sizeof(locator), "DIMM_%c%u", 'A' + dimm->channel_num, + dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "_Node0_Channel%d_Dimm%d", dimm->channel_num, + dimm->dimm_num); + t->bank_locator = smbios_add_string(t->eos, locator); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27 Gerrit-Change-Number: 35319 Gerrit-PatchSet: 5 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/fsp_broadwell_de: Use DIMM numbers relative to channel
by Martin Roth (Code Review) 21 Sep '19

21 Sep '19

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35318 ) Change subject: soc/fsp_broadwell_de: Use DIMM numbers relative to channel ...................................................................... soc/fsp_broadwell_de: Use DIMM numbers relative to channel Currently "DIMM numbers" increase monotonically for all the channels. However, commonly DIMMS are numerated on per-channel basis. This change makes numeration match the convention. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/fsp_broadwell_de/romstage/memory.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c index 7574c5f..afbf97b 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c @@ -54,7 +54,7 @@ dimm_attr dimm = {0}; u8 *spd_data = blk.spd_array[index]; if (spd_decode_ddr4(&dimm, spd_data) == SPD_STATUS_OK) - spd_add_smbios17_ddr4(channel, index, dclk_mhz, &dimm); + spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm); index++; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c Gerrit-Change-Number: 35318 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Use new common SPI code
by Richard Spiegel (Code Review) 21 Sep '19

21 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35020 ) Change subject: soc/amd/picasso: Use new common SPI code ...................................................................... soc/amd/picasso: Use new common SPI code Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=None, code already tested with grunt. Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/include/soc/southbridge.h D src/soc/amd/picasso/spi.c 4 files changed, 2 insertions(+), 207 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35020/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 26b2ec4..ed3dc1d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,7 +35,7 @@ select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select SPI_FLASH if HAVE_ACPI_RESUME + select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 67d8904..b9dd2fc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -48,7 +48,6 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c @@ -58,7 +57,6 @@ verstage-y += reset.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c -verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_PICASSO_UART) += uart.c @@ -86,7 +84,6 @@ ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c smm-y += monotonic_timer.c @@ -94,7 +91,6 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/picasso diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 803c638..ab2330e 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -261,22 +261,10 @@ #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_CNTRL1 0x0c -#define SPI_CMD_CODE 0x45 -#define SPI_CMD_TRIGGER 0x47 -#define SPI_CMD_TRIGGER_EXECUTE BIT(7) -#define SPI_TX_BYTE_COUNT 0x48 -#define SPI_RX_BYTE_COUNT 0x4b -#define SPI_STATUS 0x4c -#define SPI_DONE_BYTE_COUNT_SHIFT 0 -#define SPI_DONE_BYTE_COUNT_MASK 0xff -#define SPI_FIFO_WR_PTR_SHIFT 8 -#define SPI_FIFO_WR_PTR_MASK 0x7f -#define SPI_FIFO_RD_PTR_SHIFT 16 -#define SPI_FIFO_RD_PTR_MASK 0x7f #define SPI_FIFO 0x80 #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) diff --git a/src/soc/amd/picasso/spi.c b/src/soc/amd/picasso/spi.c deleted file mode 100644 index 8abfa16..0000000 --- a/src/soc/amd/picasso/spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/mmio.h> -#include <lib.h> -#include <timer.h> -#include <console/console.h> -#include <commonlib/helpers.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <soc/southbridge.h> -#include <amdblocks/lpc.h> -#include <soc/pci_devs.h> - -#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) - -static uintptr_t spibar; - -static void set_spibar(uintptr_t base) -{ - spibar = base; -} - -static inline uint8_t spi_read8(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline uint32_t spi_read32(uint8_t reg) -{ - return read32((void *)(spibar + reg)); -} - -static inline void spi_write8(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static inline void spi_write32(uint8_t reg, uint32_t val) -{ - write32((void *)(spibar + reg), val); -} - -static void dump_state(const char *str) -{ - if (!SPI_DEBUG_DRIVER) - return; - - printk(BIOS_DEBUG, "SPI: %s\n", str); - printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT)); - printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT)); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH); -} - -static int wait_for_ready(void) -{ - const uint32_t timeout_ms = 500; - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) - return 0; - } while (!stopwatch_expired(&sw)); - - return -1; -} - -static int execute_command(void) -{ - dump_state("Before Execute"); - - spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - - if (wait_for_ready()) - printk(BIOS_DEBUG, - "FCH SPI Error: Timeout executing command\n"); - - dump_state("Transaction finished"); - - return 0; -} - -void spi_init(void) -{ - set_spibar(lpc_get_spibase()); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - size_t count; - uint8_t cmd; - uint8_t *bufin = din; - const uint8_t *bufout = dout; - - if (SPI_DEBUG_DRIVER) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); - - /* First byte is cmd which cannot be sent through FIFO */ - cmd = bufout[0]; - bufout++; - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI" - " chip driver use spi_crop_chunk()?\n"); - return -1; - } - - if (wait_for_ready()) - return -1; - - spi_write8(SPI_CMD_CODE, cmd); - spi_write8(SPI_TX_BYTE_COUNT, bytesout); - spi_write8(SPI_RX_BYTE_COUNT, bytesin); - - for (count = 0; count < bytesout; count++) - spi_write8(SPI_FIFO + count, bufout[count]); - - if (execute_command()) - return -1; - - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read8(SPI_FIFO + count + bytesout); - - return 0; -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = SPI_FIFO_DEPTH, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/35020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Gerrit-Change-Number: 35020 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Use new common SPI code
by Richard Spiegel (Code Review) 21 Sep '19

21 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35019 ) Change subject: soc/amd/stoneyridge: Use new common SPI code ...................................................................... soc/amd/stoneyridge: Use new common SPI code Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=Build and boot grunt using new SPI code, with debug enabled. Check output. Change-Id: I639973d993316a10daa7564462e689b2c183f536 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/include/amdblocks/fch_spi.h M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/include/soc/southbridge.h D src/soc/amd/stoneyridge/spi.c 5 files changed, 12 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35019/1 diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h index c3ed793..5b275c4 100644 --- a/src/soc/amd/common/block/include/amdblocks/fch_spi.h +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -36,13 +36,21 @@ #define SPI_WRITE_ENABLE 0x06 /* SPI MMIO registers */ -#define SPI_CNTRL0 0x00 -#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_RESTRICTED_CMD1 0x04 #define SPI_RESTRICTED_CMD2 0x08 #define SPI_CNTRL1 0x0c #define SPI_CMD_CODE 0x45 #define SPI_CMD_TRIGGER 0x47 +#define SPI_CMD_TRIGGER_EXECUTE BIT(7) +#define SPI_TX_BYTE_COUNT 0x48 +#define SPI_RX_BYTE_COUNT 0x4b +#define SPI_STATUS 0x4c +#define SPI_DONE_BYTE_COUNT_SHIFT 0 +#define SPI_DONE_BYTE_COUNT_MASK 0xff +#define SPI_FIFO_WR_PTR_SHIFT 8 +#define SPI_FIFO_WR_PTR_MASK 0x7f +#define SPI_FIFO_RD_PTR_SHIFT 16 +#define SPI_FIFO_RD_PTR_MASK 0x7f /* Special SST write commands */ #define CMD_SST_BP 0x02 /* Byte Program */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f1d08c0..72719d7 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -52,7 +52,7 @@ select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select SPI_FLASH if HAVE_ACPI_RESUME + select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0fed074..53aabf5 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -49,7 +49,6 @@ bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-y += nb_util.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c @@ -67,7 +66,6 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-y += nb_util.c -romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c @@ -78,7 +76,6 @@ verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c verstage-y += nb_util.c -verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -109,7 +106,6 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c ramstage-y += nb_util.c @@ -118,7 +114,6 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += nb_util.c smm-y += gpio.c diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 07c92a1..dd514ab 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -265,22 +265,10 @@ #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_CNTRL1 0x0c -#define SPI_CMD_CODE 0x45 -#define SPI_CMD_TRIGGER 0x47 -#define SPI_CMD_TRIGGER_EXECUTE BIT(7) -#define SPI_TX_BYTE_COUNT 0x48 -#define SPI_RX_BYTE_COUNT 0x4b -#define SPI_STATUS 0x4c -#define SPI_DONE_BYTE_COUNT_SHIFT 0 -#define SPI_DONE_BYTE_COUNT_MASK 0xff -#define SPI_FIFO_WR_PTR_SHIFT 8 -#define SPI_FIFO_WR_PTR_MASK 0x7f -#define SPI_FIFO_RD_PTR_SHIFT 16 -#define SPI_FIFO_RD_PTR_MASK 0x7f #define SPI_FIFO 0x80 #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c deleted file mode 100644 index 8abfa16..0000000 --- a/src/soc/amd/stoneyridge/spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/mmio.h> -#include <lib.h> -#include <timer.h> -#include <console/console.h> -#include <commonlib/helpers.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <soc/southbridge.h> -#include <amdblocks/lpc.h> -#include <soc/pci_devs.h> - -#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) - -static uintptr_t spibar; - -static void set_spibar(uintptr_t base) -{ - spibar = base; -} - -static inline uint8_t spi_read8(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline uint32_t spi_read32(uint8_t reg) -{ - return read32((void *)(spibar + reg)); -} - -static inline void spi_write8(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static inline void spi_write32(uint8_t reg, uint32_t val) -{ - write32((void *)(spibar + reg), val); -} - -static void dump_state(const char *str) -{ - if (!SPI_DEBUG_DRIVER) - return; - - printk(BIOS_DEBUG, "SPI: %s\n", str); - printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); - printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT)); - printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT)); - printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH); -} - -static int wait_for_ready(void) -{ - const uint32_t timeout_ms = 500; - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) - return 0; - } while (!stopwatch_expired(&sw)); - - return -1; -} - -static int execute_command(void) -{ - dump_state("Before Execute"); - - spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - - if (wait_for_ready()) - printk(BIOS_DEBUG, - "FCH SPI Error: Timeout executing command\n"); - - dump_state("Transaction finished"); - - return 0; -} - -void spi_init(void) -{ - set_spibar(lpc_get_spibase()); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - size_t count; - uint8_t cmd; - uint8_t *bufin = din; - const uint8_t *bufout = dout; - - if (SPI_DEBUG_DRIVER) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); - - /* First byte is cmd which cannot be sent through FIFO */ - cmd = bufout[0]; - bufout++; - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI" - " chip driver use spi_crop_chunk()?\n"); - return -1; - } - - if (wait_for_ready()) - return -1; - - spi_write8(SPI_CMD_CODE, cmd); - spi_write8(SPI_TX_BYTE_COUNT, bytesout); - spi_write8(SPI_RX_BYTE_COUNT, bytesin); - - for (count = 0; count < bytesout; count++) - spi_write8(SPI_FIFO + count, bufout[count]); - - if (execute_command()) - return -1; - - for (count = 0; count < bytesin; count++) - bufin[count] = spi_read8(SPI_FIFO + count + bytesout); - - return 0; -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = SPI_FIFO_DEPTH, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/35019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I639973d993316a10daa7564462e689b2c183f536 Gerrit-Change-Number: 35019 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/amd/common/block: Create new SPI code
by Richard Spiegel (Code Review) 21 Sep '19

21 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35018 ) Change subject: soc/amd/common/block: Create new SPI code ...................................................................... soc/amd/common/block: Create new SPI code Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/soc/amd/common/block/include/amdblocks/fch_spi.h A src/soc/amd/common/block/spi/Kconfig A src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi_ctrl.c A src/soc/amd/common/block/spi/fch_spi_flash.c A src/soc/amd/common/block/spi/fch_spi_special.c 6 files changed, 1,008 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35018/1 diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h new file mode 100644 index 0000000..c3ed793 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FCH_SPI_H_ +#define _FCH_SPI_H_ + +#include <stdint.h> +#include <stddef.h> + +#define ROM_PROTECT_RANGE0 0x50 +#define ROM_PROTECT_RANGE1 0x54 +#define ROM_PROTECT_RANGE2 0x58 +#define ROM_PROTECT_RANGE3 0x5c +#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ +#define ROM_RANGE_WP BIT(10) +#define ROM_RANGE_RP BIT(9) +#define RANGE_UNIT BIT(8) +#define ROM_PROTECT_SKIP (ROM_PROTECT_RANGE1 - ROM_PROTECT_RANGE0) +#define ROM_PROTECT_LIMIT (ROM_PROTECT_RANGE3 + ROM_PROTECT_SKIP) +#define UPPER_16 0xffff0000 /* bits 31-16 */ +#define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */ + +#define SPI_PAGE_WRITE 0x02 +#define SPI_WRITE_ENABLE 0x06 + +/* SPI MMIO registers */ +#define SPI_CNTRL0 0x00 +#define SPI_ACCESS_MAC_ROM_EN BIT(22) +#define SPI_RESTRICTED_CMD1 0x04 +#define SPI_RESTRICTED_CMD2 0x08 +#define SPI_CNTRL1 0x0c +#define SPI_CMD_CODE 0x45 +#define SPI_CMD_TRIGGER 0x47 + +/* Special SST write commands */ +#define CMD_SST_BP 0x02 /* Byte Program */ +#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ + +#define SST_256 0x4b /* Only SST that programs 256 bytes at once */ + +#define VENDOR_ID_ADESTO 0x1f +#define VENDOR_ID_AMIC 0x37 +#define VENDOR_ID_ATMEL 0x1f +#define VENDOR_ID_EON 0x1c +#define VENDOR_ID_GIGADEVICE 0xc8 +#define VENDOR_ID_MACRONIX 0xc2 +#define VENDOR_ID_SPANSION 0x01 +#define VENDOR_ID_SST 0xbf +#define VENDOR_ID_STMICRO 0x20 +#define VENDOR_ID_STMICRO_FF 0xff +#define VENDOR_ID_WINBOND 0xef + +enum special_spi { + ESPECIAL_SPI_NONE = 0, + ESPECIAL_SPI_SST, +}; + +struct spi_data { + const char *name; + u32 size; + u32 sector_size; + u32 page_size; + u8 status_cmd; + u8 erase_cmd; + u8 write_cmd; + u8 write_enable_cmd; + u8 read_cmd; + u8 read_cmd_len; + enum special_spi special; +}; + +struct spi_detail { + u8 vendor_id; + u8 write_cmd; + u8 write_enable_cmd; +}; + +void fch_spi_init(void); +int do_fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in); +int fch_spi_flash_cmd(u8 cmd, void *response, size_t len); +int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len); +int crop_chunk(unsigned int cmd_len, unsigned int buf_len); +int special_spi_write(uint32_t offset, size_t len, const void *buf); +int fch_spi_wait_cmd_ready(unsigned long timeout); + +static inline int fch_spi_enable_write(void) +{ + return fch_spi_flash_cmd(SPI_WRITE_ENABLE, NULL, 0); +} + +#endif /* _FCH_SPI_H_ */ diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig new file mode 100644 index 0000000..40dcb29 --- /dev/null +++ b/src/soc/amd/common/block/spi/Kconfig @@ -0,0 +1,9 @@ +config SOC_AMD_COMMON_BLOCK_SPI + bool + default n + help + Select this option to add SPI controller functions to the build. + +config SOC_AMD_COMMON_BLOCK_SPI_DEBUG + bool + default n diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc new file mode 100644 index 0000000..df765d8 --- /dev/null +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -0,0 +1,24 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) + +bootblock-y += fch_spi_ctrl.c +bootblock-y += fch_spi_flash.c +bootblock-y += fch_spi_special.c +romstage-y += fch_spi_ctrl.c +romstage-y += fch_spi_flash.c +romstage-y += fch_spi_special.c +verstage-y += fch_spi_ctrl.c +verstage-y += fch_spi_flash.c +verstage-y += fch_spi_special.c +postcar-y += fch_spi_ctrl.c +postcar-y += fch_spi_flash.c +postcar-y += fch_spi_special.c +ramstage-y += fch_spi_ctrl.c +ramstage-y += fch_spi_flash.c +ramstage-y += fch_spi_special.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi_ctrl.c +smm-y += fch_spi_flash.c +smm-y += fch_spi_special.c +endif + +endif diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c new file mode 100644 index 0000000..ac73e6d --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -0,0 +1,510 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <spi_flash.h> +#include <soc/southbridge.h> +#include <soc/pci_devs.h> +#include <amdblocks/fch_spi.h> +#include <amdblocks/lpc.h> +#include <drivers/spi/spi_flash_internal.h> +#include <device/pci_ops.h> +#include <timer.h> +#include <lib.h> + +extern const struct spi_flash_ops fch_spi_flash_ops; + +struct spi_data ctrl_spi_data; +static uintptr_t spibar; + +/* + * Most SPI vendors use JEDEC defined page write command of 0x02. If a particular SPI vendor + * uses a write command different from 0x02, add it here. Each entry is {vendor_id, write_cmd, + * write_cmd_enable}. This table is terminated by a triple 0x00. + */ +const struct spi_detail vendor_write[] = { + {VENDOR_ID_SST, CMD_SST_AAI_WP, SPI_WRITE_ENABLE}, + {0, 0, 0}, +}; + +static inline uint8_t spi_read8(uint8_t reg) +{ + return read8((void *)(spibar + reg)); +} + +static inline uint32_t spi_read32(uint8_t reg) +{ + return read32((void *)(spibar + reg)); +} + +static inline void spi_write8(uint8_t reg, uint8_t val) +{ + write8((void *)(spibar + reg), val); +} + +static inline void spi_write32(uint8_t reg, uint32_t val) +{ + write32((void *)(spibar + reg), val); +} + +static void dump_state(const char *str, u8 phase) +{ + u8 dump_size; + u32 addr; + if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) + return; + + printk(BIOS_DEBUG, "SPI: %s\n", str); + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); + printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); + + addr = spibar + SPI_FIFO; + if (phase == 0) { + dump_size = spi_read8(SPI_TX_BYTE_COUNT); + printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); + printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); + } else { + dump_size = spi_read8(SPI_RX_BYTE_COUNT); + printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); + addr += spi_read8(SPI_TX_BYTE_COUNT); + } + + if (dump_size > 0) + hexdump((void *)addr, dump_size); +} + +static int wait_for_ready(void) +{ + const uint32_t timeout_ms = 500; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) + return 0; + } while (!stopwatch_expired(&sw)); + + return -1; +} + +static int execute_command(void) +{ + dump_state("Before Execute", 0); + + spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); + + if (wait_for_ready()) + printk(BIOS_DEBUG, + "FCH_SC Error: Timeout executing command\n"); + + dump_state("Transaction finished", 1); + + return 0; +} + +void spi_init(void) +{ + spibar = lpc_get_spibase(); + printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, (u32)spibar); +} + +static int spi_ctrlr_xfer(const void *dout, size_t bytesout, void *din, size_t bytesin) +{ + size_t count; + uint8_t cmd; + uint8_t *bufin = din; + const uint8_t *bufout = dout; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, + bytesin); + + /* First byte is cmd which cannot be sent through FIFO */ + cmd = bufout[0]; + bufout++; + bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout + bytesin > SPI_FIFO_DEPTH) { + printk(BIOS_DEBUG, "FCH_SC: Too much to transfer, code error!\n"); + return -1; + } + + if (wait_for_ready()) + return -1; + + spi_write8(SPI_CMD_CODE, cmd); + spi_write8(SPI_TX_BYTE_COUNT, bytesout); + spi_write8(SPI_RX_BYTE_COUNT, bytesin); + + for (count = 0; count < bytesout; count++) + spi_write8(SPI_FIFO + count, bufout[count]); + + if (execute_command()) + return -1; + + for (count = 0; count < bytesin; count++) + bufin[count] = spi_read8(SPI_FIFO + count + bytesout); + + return 0; +} + +static int amd_xfer_vectors( struct spi_op vectors[], size_t count) +{ + int ret; + void *din; + size_t bytes_in; + + if (count < 1 || count > 2) + return -1; + + /* SPI flash commands always have a command first... */ + if (!vectors[0].dout || !vectors[0].bytesout) + return -1; + /* And not read any data during the command. */ + if (vectors[0].din || vectors[0].bytesin) + return -1; + + if (count == 2) { + /* If response bytes requested ensure the buffer is valid. */ + if (vectors[1].bytesin && !vectors[1].din) + return -1; + /* No sends can accompany a receive. */ + if (vectors[1].dout || vectors[1].bytesout) + return -1; + din = vectors[1].din; + bytes_in = vectors[1].bytesin; + } else { + din = NULL; + bytes_in = 0; + } + + ret = spi_ctrlr_xfer(vectors[0].dout, vectors[0].bytesout, din, bytes_in); + + if (ret) { + vectors[0].status = SPI_OP_FAILURE; + if (count == 2) + vectors[1].status = SPI_OP_FAILURE; + } else { + vectors[0].status = SPI_OP_SUCCESS; + if (count == 2) + vectors[1].status = SPI_OP_SUCCESS; + } + + return ret; +} + +int do_fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in) +{ + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. If some specialized SPI flash controllers + * (e.g. x86) can perform both command and response together, it should + * be handled at SPI flash controller driver level. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; + size_t count = ARRAY_SIZE(vectors); + if (!bytes_in) + count = 1; + + return amd_xfer_vectors(vectors, count); +} + +int fch_spi_flash_cmd(u8 cmd, void *response, size_t len) +{ + int ret = do_fch_spi_flash_cmd(&cmd, sizeof(cmd), response, len); + if (ret) + printk(BIOS_WARNING, "FCH_SC: Failed to send command %02x: %d\n", cmd, ret); + + return ret; +} + +/* + * The following table holds all device probe functions + * + * shift: number of continuation bytes before the ID + * idcode: the expected IDCODE or 0xff for non JEDEC devices + * probe: the function to call + * + * Non JEDEC devices should be ordered in the table such that + * the probe functions with best detection algorithms come first. + * + * Several matching entries are permitted, they will be tried + * in sequence until a probe function returns non NULL. + * + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + * + * Probe functions will be given the idcode buffer starting at their + * manu id byte (the "idcode" in the table below). In other words, + * all of the continuation bytes will be skipped (the "shift" below). + */ +#define IDCODE_CONT_LEN 0 +#define IDCODE_PART_LEN 5 +static struct { + const u8 shift; + const u8 idcode; + int (*probe) (const struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash); +} flashes[] = { + /* Keep it sorted by define name */ +#if CONFIG(SPI_FLASH_ADESTO) + { 0, VENDOR_ID_ADESTO, spi_flash_probe_adesto, }, +#endif +#if CONFIG(SPI_FLASH_AMIC) + { 0, VENDOR_ID_AMIC, spi_flash_probe_amic, }, +#endif +#if CONFIG(SPI_FLASH_ATMEL) + { 0, VENDOR_ID_ATMEL, spi_flash_probe_atmel, }, +#endif +#if CONFIG(SPI_FLASH_EON) + { 0, VENDOR_ID_EON, spi_flash_probe_eon, }, +#endif +#if CONFIG(SPI_FLASH_GIGADEVICE) + { 0, VENDOR_ID_GIGADEVICE, spi_flash_probe_gigadevice, }, +#endif +#if CONFIG(SPI_FLASH_MACRONIX) + { 0, VENDOR_ID_MACRONIX, spi_flash_probe_macronix, }, +#endif +#if CONFIG(SPI_FLASH_SPANSION) + { 0, VENDOR_ID_SPANSION, spi_flash_probe_spansion, }, +#endif +#if CONFIG(SPI_FLASH_SST) + { 0, VENDOR_ID_SST, spi_flash_probe_sst, }, +#endif +#if CONFIG(SPI_FLASH_STMICRO) + { 0, VENDOR_ID_STMICRO, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO_FF, spi_flash_probe_stmicro, }, +#endif +#if CONFIG(SPI_FLASH_WINBOND) + { 0, VENDOR_ID_WINBOND, spi_flash_probe_winbond, }, +#endif + /* Keep it sorted by best detection */ +}; +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +static void save_flash_data(struct spi_flash *flash) +{ + int i; + u8 vendor, write_enable = SPI_WRITE_ENABLE, cmd = SPI_PAGE_WRITE; + + ctrl_spi_data.name = flash->name; + ctrl_spi_data.size = flash->size; + ctrl_spi_data.sector_size = flash->sector_size; + ctrl_spi_data.page_size = flash->page_size; + ctrl_spi_data.status_cmd = flash->status_cmd; + ctrl_spi_data.erase_cmd = flash->erase_cmd; + for (i = 0; i < (int)ARRAY_SIZE(vendor_write); i++) { + vendor = vendor_write[i].vendor_id; + if (vendor == flash->vendor) { + cmd = vendor_write[i].write_cmd; + write_enable = vendor_write[i].write_enable_cmd; + break; + } + if (!vendor & !cmd) { + cmd = SPI_PAGE_WRITE; + write_enable = SPI_WRITE_ENABLE; + break; + } + } + ctrl_spi_data.write_cmd = cmd; + ctrl_spi_data.write_enable_cmd = write_enable; + if (CONFIG(SPI_FLASH_NO_FAST_READ)) { + ctrl_spi_data.read_cmd_len = 4; + ctrl_spi_data.read_cmd = CMD_READ_ARRAY_SLOW; + } else { + ctrl_spi_data.read_cmd_len = 5; + ctrl_spi_data.read_cmd = CMD_READ_ARRAY_FAST; + } +} + +static int fch_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash) +{ + int ret, i, shift; + u8 idcode[IDCODE_LEN], *idp; + + /* Read the ID codes */ + ret = fch_spi_flash_cmd(CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) + return -1; + + if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) { + printk(BIOS_SPEW, "SF: Got idcode: "); + for (i = 0; i < sizeof(idcode); i++) + printk(BIOS_SPEW, "%02x ", idcode[i]); + printk(BIOS_SPEW, "\n"); + } + + /* count the number of continuation bytes */ + for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp == 0x7f; + ++shift, ++idp) + continue; + + printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); + + /* search the table for matches in shift and id */ + for (i = 0; i < (int)ARRAY_SIZE(flashes); ++i) + if (flashes[i].shift == shift && flashes[i].idcode == *idp) { + /* we have a match, call probe */ + if (flashes[i].probe(spi, idp, flash) == 0) { + flash->vendor = idp[0]; + flash->model = (idp[1] << 8) | idp[2]; + save_flash_data(flash); + flash->ops = &fch_spi_flash_ops; + if (idp[0] == VENDOR_ID_SST) { + ctrl_spi_data.special = ESPECIAL_SPI_SST; + if (idp[2] == SST_256) { + ctrl_spi_data.page_size = 256; + ctrl_spi_data.write_cmd = SPI_PAGE_WRITE; + } else + ctrl_spi_data.page_size = 2; + } else + ctrl_spi_data.special = ESPECIAL_SPI_NONE; + return 0; + } + } + + /* No match, return error. */ + return -1; +} + +static int protect_a_range(u32 value) +{ + u32 reg32; + u8 reg; + /* find a free protection register */ + for (reg = ROM_PROTECT_RANGE0; reg < ROM_PROTECT_LIMIT; reg += ROM_PROTECT_SKIP) { + reg32 = pci_read_config32(SOC_LPC_DEV, reg); + if ((reg32 & ROM_BASE_MASK) == 0) + break; + } + if (reg == ROM_PROTECT_LIMIT) + return -1; /* no free range */ + + pci_write_config32(SOC_LPC_DEV, reg, value); + return 0; +} + +/* + * Protect range of SPI flash defined by region using the SPI flash controller. + * + * Note: Up to 4 ranges can be protected, though if a particular region requires more than one + * range, total number of regions decreases accordingly. Each range can be programmed to 4KiB or + * 64KiB granularity. + * + * Know issue: If more than 1 region needs protection, and they need mixed protections (read/ + * write) than start with the region that requires the most protection. After the restricted + * commands have been written, they can't be changed (write once). So if first region is write + * protection and second region is read protection, it's best to define first region as read and + * write protection. + */ +static int fch_spi_flash_protect(const struct spi_flash *flash, const struct region *region, + const enum ctrlr_prot_type type) +{ + int ret; + u32 reg32, rom_base, range_base; + size_t addr, len, gran_value, total_ranges, range; + u8 granularity = 1; /* assume 64k granularity */ + + addr = region->offset; + len = region->size; + + reg32 = pci_read_config32(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START); + rom_base = (reg32 << 16) & UPPER_16; + range_base = addr % rom_base; + + /* Define granularity to be used */ + if (GRANULARITY_TEST_4k & range_base) + granularity = 0; /* use 4K granularity */ + if (GRANULARITY_TEST_4k & len) + granularity = 0; /* use 4K granularity */ + + /* Define the first range and total number of ranges required */ + if (granularity) { + gran_value = 0x00010000; /* 64 KiB */ + range_base = range_base >> 16; + } else { + gran_value = 0x00001000; /* 4 KiB */ + range_base = range_base >> 12; + } + total_ranges = len / gran_value; + range_base &= 0x000000ff; /* Bits 7-0 */ + + /* Create the value (reg32) to be programed and program required ranges */ + reg32 = rom_base & ROM_BASE_MASK; + reg32 |= range_base; + if (granularity) + reg32 |= RANGE_UNIT; + if (type & WRITE_PROTECT) + reg32 |= ROM_RANGE_WP; + if (type & READ_PROTECT) + reg32 |= ROM_RANGE_RP; + + for (range = 0; range < total_ranges; range++) { + ret = protect_a_range(reg32); + if (ret) + return ret; + reg32++; /* next range */ + } + + /* define commands to be blocked if in range */ + reg32 = 0; + if (type & WRITE_PROTECT) { + reg32 |= (ctrl_spi_data.write_enable_cmd << 24); + reg32 |= (ctrl_spi_data.write_cmd << 16); + reg32 |= (ctrl_spi_data.erase_cmd << 8); + } + if (type & READ_PROTECT) + reg32 |= ctrl_spi_data.read_cmd; + + /* Final steps to protect region */ + pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32); + reg32 = pci_read_config32(SOC_LPC_DEV, SPI_CNTRL0); + reg32 &= ~SPI_ACCESS_MAC_ROM_EN; + pci_write_config32(SOC_LPC_DEV, SPI_CNTRL0, reg32); + + return 0; +} + +const struct spi_ctrlr fch_spi_flash_ctrlr = { + .max_xfer_size = SPI_FIFO_DEPTH, + .flash_probe = fch_spi_flash_probe, + .flash_protect = fch_spi_flash_protect, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &fch_spi_flash_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c new file mode 100644 index 0000000..c2ff6ea --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <soc/southbridge.h> +#include <amdblocks/fch_spi.h> +#include <drivers/spi/spi_flash_internal.h> +#include <timer.h> +#include <string.h> + +extern struct spi_data ctrl_spi_data; + +static void spi_flash_addr(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; +} + +int crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + unsigned int ctrlr_max = SPI_FIFO_DEPTH; + + /* + * Assume opcode is always one byte and deduct it from the cmd_len as the hardware has + * a separate register for the opcode. + */ + cmd_len--; + ctrlr_max -= cmd_len; + return min(ctrlr_max, buf_len); +} + +int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) +{ + int ret; + u8 buff[SPI_FIFO_DEPTH + 1]; + memcpy(buff, cmd, cmd_len); + memcpy(buff + cmd_len, data, data_len); + + ret = do_fch_spi_flash_cmd(buff, cmd_len + data_len, NULL, 0); + if (ret) { + printk(BIOS_WARNING, "FCH_SF: Failed to send write command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +static int fch_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + u8 status, cmd = CMD_READ_STATUS; + + ret = do_fch_spi_flash_cmd(&cmd, 1, &status, 1); + if (!ret) + *reg = status; + return ret; +} + +int fch_spi_wait_cmd_ready(unsigned long timeout) +{ + struct mono_time current, end; + int ret; + u8 status; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); + + do { + ret = fch_spi_flash_status(NULL, &status); + if (ret) + return -1; + if ((status & STATUS_WIP) == 0) + return 0; + timer_monotonic_get(&current); + } while (!mono_time_after(&current, &end)); + + printk(BIOS_DEBUG, "FCH_SF: timeout at %ld msec\n", timeout); + return -1; +} + +static int fch_spi_flash_erase(const struct spi_flash *flash, uint32_t offset, size_t len) +{ + u32 start, end, erase_size; + int ret = -1; + u8 cmd[4]; + + erase_size = ctrl_spi_data.sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_WARNING, "%s: Erase offset/length not multiple of erase size\n", + ctrl_spi_data.name); + return -1; + } + if (len == 0) { + printk(BIOS_WARNING, "%s: Erase length cannot be 0\n", ctrl_spi_data.name); + return -1; + } + + cmd[0] = ctrl_spi_data.erase_cmd; + start = offset; + end = start + len; + + while (offset < end) { + spi_flash_addr(offset, cmd); + offset += erase_size; + +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "FCH_SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], offset); +#endif + ret = fch_spi_enable_write(); + if (ret) + goto out; + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), NULL, 0); + if (ret) + goto out; + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PAGE_ERASE_TIMEOUT_MS); + if (ret) + goto out; + } + + printk(BIOS_DEBUG, "%s: Successfully erased %zu bytes @ %#x\n", ctrl_spi_data.name, len, + start); + +out: + return ret; +} + +static int fch_spi_flash_read(const struct spi_flash *flash, uint32_t offset, size_t len, + void *buf) +{ + uint8_t *data = buf; + int ret; + size_t xfer_len; + u8 cmd[5]; + + cmd[0] = ctrl_spi_data.read_cmd; + cmd[4] = 0; + while (len) { + xfer_len = crop_chunk(ctrl_spi_data.read_cmd_len, len); + spi_flash_addr(offset, cmd); + ret = do_fch_spi_flash_cmd(cmd, ctrl_spi_data.read_cmd_len, data, xfer_len); + if (ret) { + printk(BIOS_WARNING, + "FCH_SF: Failed to send read command %#.2x(%#x, %#zx): %d\n", + cmd[0], offset, xfer_len, ret); + return ret; + } + offset += xfer_len; + data += xfer_len; + len -= xfer_len; + } + return 0; +} + +static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, size_t len, + const void *buf) +{ + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret = 0; + u8 cmd[4]; + + if (ctrl_spi_data.special != ESPECIAL_SPI_NONE) + return special_spi_write(offset, len, buf); + page_size = ctrl_spi_data.page_size; + + for (actual = 0; actual < len; actual += chunk_len) { + byte_addr = offset % page_size; + chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = crop_chunk(sizeof(cmd), chunk_len); + + cmd[0] = ctrl_spi_data.write_cmd; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" + "\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = fch_spi_enable_write(); + if (ret < 0) { + printk(BIOS_WARNING, "%s: Enabling Write failed\n", ctrl_spi_data.name); + goto out; + } + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "%s: Page Program failed\n", ctrl_spi_data.name); + goto out; + } + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); + if (ret) + goto out; + + offset += chunk_len; + } + +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "%s: Successfully programmed %zu bytes @ 0x%lx\n", + ctrl_spi_data.name, len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + return ret; +} + +const struct spi_flash_ops fch_spi_flash_ops = { + .read = fch_spi_flash_read, + .write = fch_spi_flash_write, + .erase = fch_spi_flash_erase, + .status = fch_spi_flash_status, +}; diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c new file mode 100644 index 0000000..21d91a0 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <spi-generic.h> +#include <amdblocks/fch_spi.h> +#include <string.h> + +extern struct spi_data ctrl_spi_data; + +static int sst_byte_write(u32 offset, const void *buf) +{ + int ret; + u8 cmd[4] = { + CMD_SST_BP, + offset >> 16, + offset >> 8, + offset, + }; + + ret = fch_spi_enable_write(); + if (ret) + return ret; + + ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf, 1); + if (ret) + return ret; + + return fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); +} + +static int special_sst_write_aai(u32 offset, size_t len, const void *buf) +{ + size_t actual, chunk_len, cmd_len; + unsigned long byte_addr; + unsigned long page_size; + int ret = 0; + u8 cmd[4]; + + page_size = ctrl_spi_data.page_size; + + /* If the data is not word aligned, write out leading single byte */ + actual = offset % 2; + if (actual) { + ret = sst_byte_write(offset, buf); + len--; + if (ret) + goto done; + } + offset += actual; + + ret = fch_spi_enable_write(); + if (ret) + goto done; + + cmd[0] = ctrl_spi_data.write_cmd; + cmd_len = sizeof(cmd); + + for (actual = 0; actual < len; actual += chunk_len) { + byte_addr = offset % page_size; + chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = crop_chunk(cmd_len, chunk_len); +/* + * If page_size is 2 (most SST SPI), this section of code is useful only on the first pass, + * as subsequent passes will send only the AAI command without the offset. However, this + * implementation allows for combining 2 implementations into a single one and does not consume + * too much time compared to the actual physical write within the SPI. + */ + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; + +#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) + printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = fch_spi_enable_write(); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = fch_spi_flash_cmd_write(cmd, cmd_len, buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: SST Page Program failed\n"); + break; + } + + ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS); + if (ret) + break; + + offset += chunk_len; + if (page_size == 2) + cmd_len = 1; + } +done: + return ret; +} + +int special_spi_write(uint32_t offset, size_t len, const void *buf) +{ + int ret = 0; + switch (ctrl_spi_data.special) { + case ESPECIAL_SPI_SST: + ret = special_sst_write_aai(offset, len, buf); + break; + default: + break; + } + return ret; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Gerrit-Change-Number: 35018 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci: fix legacy VGA encoding
by Michael Niewöhner (Code Review) 21 Sep '19

21 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35514 ) Change subject: device/pci: fix legacy VGA encoding ...................................................................... device/pci: fix legacy VGA encoding Enable decoding of 16-bit legacy VGA addresses to prevent resource conflicts with other devices (like SMBus and SATA on X11SS* boards). Tested on X11SSM-F. Change-Id: I29e37ac69d68ef8e0f37ef02660a53101f254992 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/device/cardbus_device.c M src/device/device.c M src/include/device/pci_def.h 3 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35514/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index a440746..4cd9f85 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -156,6 +156,7 @@ PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_VGA16 | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); /* Error check */ diff --git a/src/device/device.c b/src/device/device.c index 44d1f95..d0806ea 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> @@ -748,6 +749,7 @@ /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard; struct bus *bus; + u16 ctrl; bus = 0; vga = 0; @@ -793,11 +795,21 @@ bus = vga->bus; } - /* Now walk up the bridges setting the VGA enable. */ + /* Now walk up the bridges setting the VGA enable if supported. */ while (bus) { - printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", - dev_path(bus->dev)); - bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; + /* try to set VGA16; it will return 1 if it is supported */ + ctrl = pci_read_config16(bus->dev, PCI_CB_BRIDGE_CONTROL); + if (!(ctrl & PCI_BRIDGE_CTL_VGA16)) { // no test needed if already set + pci_or_config16(bus->dev, PCI_CB_BRIDGE_CONTROL, PCI_BRIDGE_CTL_VGA16); + ctrl = pci_read_config16(bus->dev, PCI_CB_BRIDGE_CONTROL); + /* restore */ + pci_write_config16(bus->dev, PCI_CB_BRIDGE_CONTROL, ctrl & ~PCI_BRIDGE_CTL_VGA16); + } + if (ctrl & PCI_BRIDGE_CTL_VGA16) { + printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA(16) for bridge %s\n", dev_path(bus->dev)); + bus->bridge_ctrl |= (PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16); + } + bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..660edcb 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -138,6 +138,7 @@ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_VGA16 0x16 /* Enable VGA16 decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ /* Fast Back2Back enabled on secondary interface */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29e37ac69d68ef8e0f37ef02660a53101f254992 Gerrit-Change-Number: 35514 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 21 Sep '19

21 Sep '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: (3 comments) https://review.coreboot.org/c/coreboot/+/34089/19/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/19/src/soc/intel/common/bloc… PS19, Line 31: alteast > at least Done, Thanks!! for reviewing the CLs https://review.coreboot.org/c/coreboot/+/34089/19/src/soc/intel/common/bloc… PS19, Line 69: printk(BIOS_ERR, "LPSS controller D: 0x%x F: 0x%x uses irq %d" : ", conflicts with gpio mapped to irq %d\n", : irq_entry->slot, irq_entry->func, int_lpss, : int_lpss); > Shouldn't we die() with this? It means there's a fatal configuration error, and I'm assuming that t […] only if GPIO is configured as GPI and irq routing is set via IOAPIC, else we are fine. That would be a fatal configuration. Currently it would just up as a warning in logs? what do you think? https://review.coreboot.org/c/coreboot/+/34089/19/src/soc/intel/common/bloc… PS19, Line 108: create_irq_entry(dev, &irq_entry); : irq_config[index] = irq_entry; > You could just do create_irq_entry(dev, &irq_config[index]) to avoid the extra copy Ok, done. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 21 Sep 2019 14:19:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 21 Sep '19

21 Sep '19

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Arthur Heymans, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34089 to look at the new patch set (#20). Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices Add implementation to fill PCI IRQ table. Each IRQ entry in the table would have information on PCI device number, bus number, irq number and INTx mapping information. This table will be used by FSP as interrupt config to program ITSS PIRx register and also to program interrupt pin for LPSS controllers. Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/irq.h M src/soc/intel/common/block/itss/Kconfig M src/soc/intel/common/block/itss/Makefile.inc A src/soc/intel/common/block/itss/irq.c 4 files changed, 181 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34089/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/wifi/generic.c: Use upper case for ACPI WiFi name
by Andrew McRae (Code Review) 21 Sep '19

21 Sep '19

Andrew McRae has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35466 ) Change subject: drivers/wifi/generic.c: Use upper case for ACPI WiFi name ...................................................................... drivers/wifi/generic.c: Use upper case for ACPI WiFi name The ACPI specification requires upper case letters for the device name. For Intel WiFi names, the name is generated, so ensure that only upper case letters are used. Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc Signed-off-by: Andrew McRae <amcrae(a)chromium.org> --- M src/drivers/wifi/generic.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35466/1 diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index b593ffe..bb225b7 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -239,7 +239,8 @@ { static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; - snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02x", + /* ACPI specification requires uppercase name */ + snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X", (dev_path_encode(dev) & 0xff)); return wifi_acpi_name; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc Gerrit-Change-Number: 35466 Gerrit-PatchSet: 1 Gerrit-Owner: Andrew McRae <amcrae(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: extend BOOT_MODE_PCR to SHA256 bank on TPM2
by Andrey Pronin (Code Review) 21 Sep '19

21 Sep '19

Andrey Pronin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35476 ) Change subject: vboot: extend BOOT_MODE_PCR to SHA256 bank on TPM2 ...................................................................... vboot: extend BOOT_MODE_PCR to SHA256 bank on TPM2 With the support of various algorithms and banks in tlcl_extend(), digest_algo parameter of tpm_extend_pcr() started defining the target PCR bank in TPM2 case. The OS expects coreboot to extend the SHA256 bank of BOOT_MODE_PCR. The value that the OS expects coreboot to extend into BOOT_MODE_PCR is the SHA1 digest of mode bits extended to the length of SHA256 digest by appending zero bytes. Thus the correct value for digest_algo passed into tpm_extend_pcr() for BOOT_MODE_PCR is TPM_ALG_SHA256. This didn't matter until adding the support for multiple digest introduced by patches like https://review.coreboot.org/c/coreboot/+/33252, as tlcl_extend always used SHA256 bank before. Change-Id: I834fec24023cd10344cc359117f00fc80c61b80c Signed-off-by: Andrey Pronin <apronin(a)chromium.org> --- M src/security/vboot/tpm_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35476/1 diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 1db7189..0a211c5 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -46,7 +46,7 @@ switch (which_digest) { /* SHA1 of (devmode|recmode|keyblock) bits */ case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, + return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size, TPM_PCR_BOOT_MODE); /* SHA256 of HWID */ case HWID_DIGEST_PCR: -- To view, visit https://review.coreboot.org/c/coreboot/+/35476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I834fec24023cd10344cc359117f00fc80c61b80c Gerrit-Change-Number: 35476 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Pronin <apronin(a)chromium.org> Gerrit-MessageType: newchange

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