coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/i82870: Drop unused file
by Kyösti Mälkki (Code Review) 22 Sep '19

22 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35520 ) Change subject: sb/intel/i82870: Drop unused file ...................................................................... sb/intel/i82870: Drop unused file Change-Id: I024805769ad05f995a23669a82f5482ce3e7ae70 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82870/Makefile.inc D src/southbridge/intel/i82870/pci_parity.c 2 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35520/1 diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 790bd01..d6ae171 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -2,6 +2,5 @@ ramstage-y += ioapic.c ramstage-y += pcibridge.c -#ramstage-y += pci_parity.c endif diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c deleted file mode 100644 index 3bb05cc..0000000 --- a/src/southbridge/intel/i82870/pci_parity.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <pci.h> -#include <printk.h> -# - -void p64h2_pci_parity_enable(void) -{ - uint8_t reg; - - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); - - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); - - return; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024805769ad05f995a23669a82f5482ce3e7ae70 Gerrit-Change-Number: 35520 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/cardbus: Remove unnecessary bridge_ctrl bitmask
by Kyösti Mälkki (Code Review) 22 Sep '19

22 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35519 ) Change subject: device/cardbus: Remove unnecessary bridge_ctrl bitmask ...................................................................... device/cardbus: Remove unnecessary bridge_ctrl bitmask The bits PARITY and SERR are set unconditionally below. Change-Id: I03f53fe7f436f8feed7b34756439077f02a85565 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/cardbus_device.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35519/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 826d785..48c54bc 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -152,8 +152,6 @@ ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link_list->bridge_ctrl & ( - PCI_BRIDGE_CTL_PARITY | - PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | -- To view, visit https://review.coreboot.org/c/coreboot/+/35519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03f53fe7f436f8feed7b34756439077f02a85565 Gerrit-Change-Number: 35519 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROL
by Kyösti Mälkki (Code Review) 22 Sep '19

22 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35518 ) Change subject: device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROL ...................................................................... device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROL Read-modify-write needs to access the same register. Numerically both used defines are 0x3e, while register implementations are not identical but only similar. Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/cardbus_device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35518/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 4b24c54..826d785 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -161,7 +161,7 @@ /* Error check */ ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl); pci_dev_enable_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0 Gerrit-Change-Number: 35518 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci: Replace add with bitwise-or
by Kyösti Mälkki (Code Review) 22 Sep '19

22 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35517 ) Change subject: device/pci: Replace add with bitwise-or ...................................................................... device/pci: Replace add with bitwise-or Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/cardbus_device.c M src/device/pci_device.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/i82801gx/pci.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35517/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index a440746..4b24c54 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -159,7 +159,7 @@ PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); /* Error check */ - ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); + ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ecb652..c043dd6 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -626,7 +626,7 @@ dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 2186287..6391de4 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -77,7 +77,7 @@ dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 22c5165..1d1f902 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -76,7 +76,7 @@ dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/35517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36 Gerrit-Change-Number: 35517 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 22 Sep '19

22 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34998 ) Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... Patch Set 14: Ping, patrick? -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 14 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 22 Sep 2019 12:17:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: remove unnecessary fsp setting CdClock
by Michael Niewöhner (Code Review) 22 Sep '19

22 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35477 ) Change subject: mb/supermicro/x11ssh: remove unnecessary fsp setting CdClock ...................................................................... mb/supermicro/x11ssh: remove unnecessary fsp setting CdClock CdClock does not need to be set because the board does not use IGD. Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/supermicro/x11ssh/ramstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35477/1 diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11ssh/ramstage.c index 2672f73..a37d2d2 100644 --- a/src/mainboard/supermicro/x11ssh/ramstage.c +++ b/src/mainboard/supermicro/x11ssh/ramstage.c @@ -20,7 +20,6 @@ /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - params->CdClock = 3; /* This must be one, otherwise FSP crashes ... */ params->PchHdaVcType = 0x1; -- To view, visit https://review.coreboot.org/c/coreboot/+/35477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21 Gerrit-Change-Number: 35477 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Nico Huber (Code Review) 22 Sep '19

22 Sep '19

Nico Huber has uploaded a new patch set (#8) to the change originally created by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... lenovo/x230: introduce FHD variant There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a Full HD (FHD) eDP panel instead of the stock LVDS display. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. The VBT has been modified as well, which allows brightness controls to work out of the box. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with panel LP125WF2 SPB4. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/Kconfig.name M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/variants/x230/data.vbt R src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads A src/mainboard/lenovo/x230/variants/x230_fhd/data.vbt A src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads 7 files changed, 45 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28950/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: lock down TCO on pch finalize
by Michael Niewöhner (Code Review) 22 Sep '19

22 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35448 ) Change subject: soc/intel/skylake: lock down TCO on pch finalize ...................................................................... soc/intel/skylake: lock down TCO on pch finalize Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720 Signed-off-by: Michael Niewöhner <michael.niewoehner(a)8com.de> --- M src/soc/intel/skylake/finalize.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35448/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8afaf4d..0d6f737 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -26,6 +26,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <reg_script.h> #include <spi-generic.h> @@ -72,6 +73,8 @@ config_t *config; u8 reg8; + tco_lockdown(); + /* Display me status before we hide it */ intel_me_status(); -- To view, visit https://review.coreboot.org/c/coreboot/+/35448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720 Gerrit-Change-Number: 35448 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/fsp_broadwell_de: Add devhide functionality
by Martin Roth (Code Review) 21 Sep '19

21 Sep '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35321 ) Change subject: soc/fsp_broadwell_de: Add devhide functionality ...................................................................... Patch Set 8: (3 comments) https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 54: Possibly change all the spaces to tabs in a follow on commit? Up to you. https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 113: Coming of from Reword this? https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/ubox.h: https://review.coreboot.org/c/coreboot/+/35321/8/src/soc/intel/fsp_broadwel… PS8, Line 42: : static inline void iio_hide(const uint8_t devno, const uint8_t funcno) Why make this an inline function in a .h file instead of just in the case statement directly? Even just put it in the .c file and let the compiler decide to inline it if it wants to. -- To view, visit https://review.coreboot.org/c/coreboot/+/35321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Gerrit-Change-Number: 35321 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sat, 21 Sep 2019 20:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common file
by Martin Roth (Code Review) 21 Sep '19

21 Sep '19

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35320 ) Change subject: soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common file ...................................................................... soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common file Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h M src/soc/intel/fsp_broadwell_de/include/soc/vtd.h M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 3 files changed, 19 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index 973f559..58591dc 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -32,6 +32,7 @@ #define VTD_FUNC 0 #define VTD_DEVID 0x6f28 #define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) +#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) #define LPC_DEV 31 #define LPC_FUNC 0 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h index 43da267..814cba0 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h @@ -16,6 +16,9 @@ #ifndef _BROADWELL_VTD_H_ #define _BROADWELL_VTD_H_ +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + #define VTD_CPUBUSNO 0x108 #define VTD_CPUBUSNO_BUS0_MASK 0xff #define VTD_CPUBUSNO_BUS0_SHIFT 0 @@ -26,4 +29,14 @@ #define VTD_DFX1 0x804 #define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29) #define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30) + +static inline uint8_t get_busno1(void) +{ + uint32_t reg32; + + /* Figure out what bus number is assigned for CPUBUSNO(1) */ + reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO); + return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK); +} + #endif diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 5c9682a..b0fad3f 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -61,24 +61,18 @@ static void enable_integrated_uart(uint8_t port) { - uint32_t reg32, busno1 = 0, ubox_uart_en = 0, dfx1 = 0; - pci_devfn_t vtd_dev, ubox_dev; - - vtd_dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - - /* Figure out what bus number is assigned for CPUBUSNO(1) */ - reg32 = pci_mmio_read_config32(vtd_dev, VTD_CPUBUSNO); - busno1 = (reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK; + uint32_t ubox_uart_en = 0, dfx1 = 0; + pci_devfn_t ubox_dev; /* UBOX sits on CPUBUSNO(1) */ - ubox_dev = PCI_DEV(busno1, UBOX_DEV, UBOX_FUNC); + ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS); /* In case we are in bypass mode do nothing */ if (reset_sts & UBOX_SC_BYPASS) return; - dfx1 = pci_mmio_read_config32(vtd_dev, VTD_DFX1); + dfx1 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_DFX1); ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE); switch (port) { @@ -96,7 +90,7 @@ } /* Disable decoding and enable the port we want */ - pci_mmio_write_config32(vtd_dev, VTD_DFX1, dfx1); + pci_mmio_write_config32(VTD_PCI_DEV, VTD_DFX1, dfx1); pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Gerrit-Change-Number: 35320 Gerrit-PatchSet: 6 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2019