V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615
Change subject: mb/google/hatch: Disable the eMMC controller for hatch
......................................................................
mb/google/hatch: Disable the eMMC controller for hatch
eMMC controller is not used in hatch hence this patch adds the
Kconfig option to disable the eMMC controller ACPI entries.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/mainboard/google/hatch/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 711d2e9..15fe354 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -15,6 +15,7 @@
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COFFEELAKE
select SYSTEM_TYPE_LAPTOP
+ select EXCLUDE_EMMC_INTERFACE
if BOARD_GOOGLE_BASEBOARD_HATCH
--
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Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35029 )
Change subject: soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align
......................................................................
soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align
This patch makes top_of_ram aligned in order to meet MTRR
alignment requirments.
Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
4 files changed, 27 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35029/1
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 9e2f2f8..d83da7f 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -133,6 +133,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps = pmc_get_power_state();
console_init();
@@ -155,12 +156,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index af65d38..0d8d4c8 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -142,6 +142,7 @@
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
console_init();
@@ -164,10 +165,12 @@
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
+ * This satisfies MTRR alignment requirements as well.
*/
- top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
- MTRR_TYPE_WRBACK);
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 4d0cc17..a083788 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -117,6 +117,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps = pmc_get_power_state();
console_init();
@@ -139,12 +140,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 1d925b3..0977614 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -145,6 +145,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps;
console_init();
@@ -166,12 +167,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
if (CONFIG(HAVE_SMI_HANDLER)) {
/* Cache the TSEG region. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff
Gerrit-Change-Number: 35029
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Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34805 )
Change subject: arch/x86: Add postcar_frame_add_ramcache() API
......................................................................
arch/x86: Add postcar_frame_add_ramcache() API
This patch adds new API for intermediate caching top_of_ram
and setting up required MTRR for next stage.
Change-Id: Iddafb573afb4799de64754a94816d7f3f2f4982f
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/postcar_loader.c
2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34805/1
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 293ca02..7dc4049 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -329,6 +329,13 @@
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
/*
+ * Add variable MTRR covering the Top of RAM with given MTRR type.
+ */
+void postcar_frame_add_ramcache(struct postcar_frame *pcf,
+ uintptr_t addr, size_t size, int type);
+
+
+/*
* Push used MTRR and Max MTRRs on to the stack
* and return pointer to stack top.
*/
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 35e139f..8a1f6cb 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -120,6 +120,29 @@
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
+/*
+ * Make sure we are enabling intermediate caching to speed up next stage
+ * (postcar/romstage) loading and decompression as we are still in romstage
+ * and CAR tear down will be handled by next stage at its entry.
+ */
+static void enable_top_of_ram_cache(uintptr_t base, size_t size)
+{
+ int mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
+}
+
+void postcar_frame_add_ramcache(struct postcar_frame *pcf,
+ uintptr_t addr, size_t size, int type)
+{
+ /* enable intermediate caching for Top of RAM */
+ enable_top_of_ram_cache(addr, size);
+ postcar_frame_add_mtrr(pcf, addr, size, type);
+}
+
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
{
/*
--
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
......................................................................
soc/intel/cannonlake: Speed up postcar loading using intermediate caching
This patch ensures intermediate caching is enabled to speed up
loading and decompression of next stage as we are still in romstage
and car tear down will be handled by next stage at its entry.
TEST=cbmem -t shows ~2-4ms time savings in warm reboot case with this
CL.
Change-Id: I3ba63887acb5c4bdeaf3e21c24fb0e631362962c
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34791/1
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b9899..04a9d53 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -127,6 +127,21 @@
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
+/*
+ * Make sure we are enabling intermediate caching to speed up next stage
+ * (postcar/romstage) loading and decompression as we are still in romstage
+ * and car tear down will be handled by next stage at its entry.
+ */
+static void enable_ramstage_caching(uintptr_t base, size_t size)
+{
+ int mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
+}
+
asmlinkage void car_stage_entry(void)
{
bool s3wake;
@@ -160,6 +175,8 @@
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ /* enabling intermediate caching */
+ enable_ramstage_caching(top_of_ram, 16*MiB);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
--
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