Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30747
Change subject: cpu/amd/microcode: Search all containers
......................................................................
cpu/amd/microcode: Search all containers
Currently, it’s aborted if the first file is not found.
The commit was only tested with all microcode containers present in
CBFS.
If only one microcode update container is present, which is not the
first, it is skipped.
Change the return to continue to traverse all elements.
Fixes: 83e4c5613 (cpu/amd/microcode: Update parser to use stock microcode blobs)
Change-Id: I5195ff0334cf49cadc25de31822a9f2f2cd90490
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/cpu/amd/microcode/microcode.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30747/1
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index e8ab175..622c6db 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -214,7 +214,7 @@
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
- return;
+ continue;
}
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
--
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Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35011 )
Change subject: Doc/mb/asus: Add H110M-E/M.2 Documentation
......................................................................
Doc/mb/asus: Add H110M-E/M.2 Documentation
Followed and adapted from the ASRock H110M-DVS Documentation
Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com>
Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b
---
A Documentation/mainboard/asus/h110m-e_m2.md
1 file changed, 136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35011/1
diff --git a/Documentation/mainboard/asus/h110m-e_m2.md b/Documentation/mainboard/asus/h110m-e_m2.md
new file mode 100644
index 0000000..134dca8
--- /dev/null
+++ b/Documentation/mainboard/asus/h110m-e_m2.md
@@ -0,0 +1,136 @@
+# ASUS H110M-E/M.2
+
+This page describes how to run coreboot on the [ASUS H110M-E/M.2].
+
+## Required proprietary blobs
+
+Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset.
+Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md)
+(intel FSP 2.0) to initialize this generation silicon. Please see this
+[document](../../soc/intel/code_development_model/code_development_model.md).
+
+FSP Information:
+
+```eval_rst
++-----------------------------+-------------------+-------------------+
+| FSP Project Name | Directory | Specification |
++-----------------------------+-------------------+-------------------+
+| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
+| processors and chipsets | | |
+| (formerly Kaby Lake) | | |
++-----------------------------+-------------------+-------------------+
+```
+
+## Building coreboot
+
+The following steps set the default parameters for this board to build a
+fully working image:
+
+```bash
+make distclean
+touch .config
+./util/scripts/config --enable VENDOR_ASUS
+./util/scripts/config --enable BOARD_ASUS_H110M_E_M2
+./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES
+./util/scripts/config --enable CONFIG_FSP_USE_REPO
+./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx"
+make olddefconfig
+```
+
+However, it is strongly advised to use `make menuconfig` afterwards
+(or instead), so that you can see all of the settings.
+
+Use the following command to disable the serial console if debugging
+output is not required:
+
+```bash
+./util/scripts/config --disable CONSOLE_SERIAL
+```
+
+However, a more flexible method is to change the console log level from
+within an OS using `util/nvramtool`, or with the `nvramcui` payload.
+
+Now, run `make` to build the coreboot image.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region, such as the Management Engine or firmware descriptor, then
+an external programmer is required (unless you find a clever way around
+the flash protection). More information about this [here](../../flash_tutorial/index.md).
+
+### External programming
+
+The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a
+GIgaDevice GD25B128CPIG, whose datasheet can be found [here][GD25B128CPIG].
+The chip is located to the bottom right-hand side of the board. For
+a precise location, refer to section 1.3 (Motherboard Layout) of the
+[H110M-E/M.2 manual], where the chip is labelled "128Mb BIOS". Take note of
+the chip's orientation, remove it from its socket, and flash it with
+an external programmer. For reference, the notch in the chip should be
+facing towards the bottom of the board.
+
+## Known issues
+
+- The VGA port doesn't work. Discrete graphic card is used as primary
+ device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not
+ set). Dynamic switching between iGPU and PEG is not yet supported.
+
+- SuperIO GPIO pin is used to reset Realtek chip. However, since the
+ Logical Device 7 (GPIO7, GPIO8) is not initialized, the network
+ chip is in a reset state all the time.
+
+## Untested
+
+- parallel port
+- PS/2 keyboard
+- PS/2 mouse
+- EHCI debug
+- TPM
+- infrared module
+- chassis intrusion header
+- chassis speaker header
+
+## Working
+
+- integrated graphics init with libgfxinit (see [Known issues](#known-issues))
+- PCIe x1
+- PEG x16 Gen3
+- SATA
+- USB
+- serial port
+- onboard audio
+- using `me_cleaner`
+- using `flashrom`
+
+## TODO
+
+- NCT5539D GPIOs
+- onboard network (see [Known issues](#known-issues))
+- S3 suspend/resume
+- Wake-on-LAN
+- hardware monitor
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU | Intel Skylake/Kaby Lake (LGA1151) |
++------------------+--------------------------------------------------+
+| PCH | Intel Sunrise Point H110 |
++------------------+--------------------------------------------------+
+| Super I/O | Nuvoton NCT5539D |
++------------------+--------------------------------------------------+
+| EC | None |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel Management Engine |
++------------------+--------------------------------------------------+
+```
+
+[ASUS H110M-E/M.2]: https://www.asus.com/Motherboards/H110M-E-M-2/overview/
+[GD25B128CPIG]: https://www.gigadevice.com/datasheet/gd25b127d/ [The closest match found]
+[flashrom]: https://flashrom.org/Flashrom
+[ASUS H110M-E/M.2 manual]: https://dlcdnets.asus.com/pub/ASUS/mb/LGA1151/H110M-E_M2/E11622_H110M-E_M2_…
--
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Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34657 )
Change subject: Documentation/soc/intel: Add documentation for MCU update
......................................................................
Documentation/soc/intel: Add documentation for MCU update
Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a
Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com>
---
A Documentation/soc/intel/ucode_update/Flash_Layout.PNG
A Documentation/soc/intel/ucode_update/microcode_update_model.md
2 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34657/1
diff --git a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG
new file mode 100644
index 0000000..ac18977
--- /dev/null
+++ b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG
Binary files differ
diff --git a/Documentation/soc/intel/ucode_update/microcode_update_model.md b/Documentation/soc/intel/ucode_update/microcode_update_model.md
new file mode 100644
index 0000000..e2d7f35
--- /dev/null
+++ b/Documentation/soc/intel/ucode_update/microcode_update_model.md
@@ -0,0 +1,43 @@
+# Microcode update mechanism for devices in field
+
+## Introduction
+
+Processor microcode (MCU) is akin to processor firmware. Processors may need updates to their microcode to operate correctly. These updates fix bugs/errata that can cause anything from incorrect processing, to code and data corruption, and system lockups.
+
+##Problem Statement
+
+As per chrome design, any field updatable FW has to be first verified by vboot (chrome root of trust - CROT) before it is allowed to run on the system. CROT executes on the CPU, hence FW such as MCU loaded before the CPU reset cannot be verified before it actually gets loaded. As a result today Chromebooks are not able to apply MCU in the field. This proposal tries to address the issue
+
+Prior to CPU reset, the CPU HW locates the FIT table from the storage, walks over the FIT table and picks-up the MCU that matches the CPU Family, Model, Stepping and PLATFORM ID with the highest revision ID. CPU verifies that MCU is signed by Intel and once verification is successful, it attempts to load the MCU.
+
+However FIT does not contain any fall back mechanism. If one MCU loading fails for whatever reason, it drops the further loading process and moves on to CPU reset. While it is fairly a remote chance, in case of any failure to load MCU which cause hang like situations before CPU reset, a platform based mechanism can be put in place to enter recovery mode. As detailed below, if we are using BUC register based top swap implementation, then an RTC reset may be required to clear top swap bit.
+
+## Design Proposal
+
+The proposal relies on the following Intel SoC features:
+
+1. Top swap, which enables the BIOS to have 2 bootblocks and bot from either using a RTC backed Top swap control bit in BUC register.
+2. Firmware Interface Table (FIT) based MCU loading.
+
+The idea is to have 2 bootblocks, each having its own FIT table. The FIT in one of them will be configured to point to an MCU in RO firmware, and the FIT in other one will point to a fixed flash region (aka MCU staging area), which will contain an MCU from RW firmware.
+
+Top-swap feature of Intel CPUs, will be used to switch between 2 bootblocks, based on the bootmode i.e., recovery or normal/developer mode.
+
+Coreboot will keep the MCU staging area updated with the MCU from the currently selected RW firmware.
+
+## Implementation Details
+
+1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their own FIT tables. Both bootblocks will be in the RO section.
+ a. bb_ro_ucode contains a FIT which has pointer to MCU (microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario.
+ b. bb_staged_ucode is identical to bb_ro_ucode but contains a FIT which has pointer to a MCU that will reside in a staging area.
+2. Create a MCU staging area
+ a. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for that SoC. This is a RW region just lke the RW_MRC_CACHE.
+ b. MCU from RW-A/RW-B will be copied to this region during boot.
+ c. A Flash Protected Range (FPR) should be configured to write protect this MCU Staging area.
+ d. bb_staged_ucode FIT points to the MCU in this staging area.
+3. The resulting flash layout is shown below,
+**Flash Layout**
+![Flash Layout][flash_layout]
+[flash_layout]: Flash_Layout.PNG
+
+4. The proposed design uses the PCR register based control for top-swap
--
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Hello Marco Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33661
to review the following change.
Change subject: vendorcode/google: load sar config from CBFS first then VPD
......................................................................
vendorcode/google: load sar config from CBFS first then VPD
SAR config provisioned in RO VPD can be done in the factory only. Once
it is wrong, we can override the SAR config by updating FW RW which can
carry new SAR config in CBFS. As a result, we should check CBFS first
then VPD.
Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1
Signed-off-by: Marco Chen <marcochen(a)chromium.org>
---
M src/vendorcode/google/chromeos/sar.c
1 file changed, 23 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33661/1
diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c
index bbcb211..a5a2c3b 100644
--- a/src/vendorcode/google/chromeos/sar.c
+++ b/src/vendorcode/google/chromeos/sar.c
@@ -82,36 +82,37 @@
sizeof(struct wifi_sar_delta_table);
}
- /* Try to read the SAR limit entry from VPD */
- if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str,
- buffer_size, VPD_ANY)) {
- printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n",
- wifi_sar_limit_key);
-
- if (!CONFIG(WIFI_SAR_CBFS))
- return -1;
-
+ if (CONFIG(WIFI_SAR_CBFS)) {
printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n");
sar_cbfs_len = load_sar_file_from_cbfs(
(void *) wifi_sar_limit_str,
sar_expected_len);
- if (sar_cbfs_len != sar_expected_len) {
- printk(BIOS_ERR, "%s has bad len in CBFS\n",
- WIFI_SAR_CBFS_FILENAME);
- return -1;
- }
- } else {
- /* VPD key "wifi_sar" found. strlen is checked with addition of
- * 1 as we have created buffer size 1 char larger for the reason
- * mentioned at start of this function itself */
- if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) {
- printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n");
- return -1;
- }
+ if (sar_cbfs_len == sar_expected_len)
+ goto done;
+
+ printk(BIOS_ERR, "%s has bad len in CBFS\n",
+ WIFI_SAR_CBFS_FILENAME);
}
+ /* Try to read the SAR limit entry from VPD */
+ if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str,
+ buffer_size, VPD_ANY)) {
+ printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n",
+ wifi_sar_limit_key);
+ return -1;
+ }
+
+ /* VPD key "wifi_sar" found. strlen is checked with addition of
+ * 1 as we have created buffer size 1 char larger for the reason
+ * mentioned at start of this function itself */
+ if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) {
+ printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n");
+ return -1;
+ }
+
+done:
/* Decode the heximal encoded string to binary values */
if (hexstrtobin(wifi_sar_limit_str, bin_buffer, bin_buff_adjusted_size)
< bin_buff_adjusted_size) {
--
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Gerrit-Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1
Gerrit-Change-Number: 33661
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Gerrit-Owner: Marco Chen <marcochen(a)google.com>
Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org>
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Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905
Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable
......................................................................
RFC: smbios: allow setting BIOS-version string from VPD variable
As in the title. Such approach allows for convenient setting of the
firmware version and keep it in partition that is easily readable
from both - coreboot binary and already running operating system.
vpd_find is used directly as it returns pointer to vpd value which,
by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This
way we avoid copying string around and coming up with temporary
buffer.
Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458
Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com>
---
M src/arch/x86/smbios.c
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 589f4f0..2ffd2dd 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -30,6 +30,9 @@
#include <memory_info.h>
#include <spd.h>
#include <cbmem.h>
+#if CONFIG(VPD)
+#include <drivers/vpd/vpd.h>
+#endif
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -347,6 +350,15 @@
const char *__weak smbios_mainboard_bios_version(void)
{
+#if CONFIG(VPD)
+ /* size is unused for now */
+ int size;
+ const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO);
+
+ /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */
+ if(coreboot_vpd_version)
+ return coreboot_vpd_version;
+#endif
if (strlen(CONFIG_LOCALVERSION))
return CONFIG_LOCALVERSION;
else
--
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Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458
Gerrit-Change-Number: 32905
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Gerrit-Owner: Łukasz Siudut
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junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798
Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
......................................................................
for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5
Signed-off-by: junaid <junaidimpex(a)gmail.com>
---
M src/mainboard/intel/d945gclf/Kconfig
M src/mainboard/intel/d945gclf/devicetree.cb
2 files changed, 37 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 70fa848..906dd01 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -20,7 +20,8 @@
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
select SOUTHBRIDGE_INTEL_I82801GX
- select SUPERIO_SMSC_LPC47M15X
+## changed as per Advantech SOM 4461
+ select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 90c517f..864775a 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -65,44 +65,42 @@
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 off end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
- device pci 1e.2 off end # AC'97 Audio
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47m15x
- device pnp 2e.0 off # Floppy
- end
- device pnp 2e.3 off # Parport
- end
- device pnp 2e.4 on
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 on
- io 0x60 = 0x2f8
- irq 0x70 = 3
- irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
- end
- device pnp 2e.7 on # Keyboard+Mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- irq 0xf0 = 0x82 # HW accel A20.
- end
- device pnp 2e.8 on # GAME
- # all default
- end
- device pnp 2e.a on # PME
- end
- device pnp 2e.b on # MPU
- end
- end
- end
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # Parallel Port
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard,Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ #device pnp 2e.6 off end # SPI
+ device pnp 2e.307 off end # GPIO6
+ device pnp 2e.8 off end # WDTO, PLED
+ device pnp 2e.009 off end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 off end # GPIO4
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.A off end # ACPI
+ device pnp 2e.B off end # HW Monitor
+ end # w83627dhg
+ end
device pci 1f.1 off end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on end # SMBus
- end
- end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ end
+ end
end
--
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