coreboot-gerrit September 2019

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Change in ...coreboot[master]: mb/*/devicetree.cb: Add more smbios_slot_desc
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32684 Change subject: mb/*/devicetree.cb: Add more smbios_slot_desc ...................................................................... mb/*/devicetree.cb: Add more smbios_slot_desc Add smbios_slot_desc for desktop and serverboards. Fill in PCIe, PCI and Mini PCIe slots. Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/asus/h61m-cs/devicetree.cb M src/mainboard/asus/kcma-d8/devicetree.cb M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 22 files changed, 100 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32684/1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 9eba6fc..18c0c12 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -48,6 +48,7 @@ end device pci 01.0 on subsystemid 0x1849 0x0151 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on subsystemid 0x1849 0x0152 @@ -92,6 +93,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x1849 0x1e10 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -114,6 +116,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x1849 0x244e + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1e49 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..1e4d6bc 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -267,6 +267,7 @@ end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 @@ -295,7 +296,9 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 58a319d..a25a57e 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -38,6 +38,7 @@ device pci 01.0 on # PCIe graphics subsystemid 0x1849 0x0c01 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # VGA controller @@ -101,6 +102,7 @@ end device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" end device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index 9a4c6fe..118e435 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -30,7 +30,9 @@ device domain 0x0 on subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index f8a2d83..49bb8b2 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -17,6 +17,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -211,12 +212,15 @@ device pci 14.4 on # Bridge device pci 1.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot 0" "5" end device pci 2.0 on # Slot # Slot # PCI 1 + smbios_slot_desc "6" "3" "PCI slot 1" "5" end device pci 3.0 on # Slot # Slot # PCI 2 + smbios_slot_desc "6" "3" "PCI slot 2" "5" end device pci 5.0 on end # VGA end diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..5710521 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -18,6 +18,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -35,12 +36,15 @@ end device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci c.0 on # Bridge (GPP2 Port1) # Slot # PCI E 5 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci d.0 on # Bridge (GPP3b Port0) # Slot # PCI E 3 + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 @@ -226,6 +230,7 @@ device pci 2.0 on end # FireWire device pci 3.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot" "5" end end device pci 14.5 on end # USB OHCI2 0x4399 diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f39..915b67a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071f..80cd2e9 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index f853452..d3706d5 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -119,7 +119,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics (PCIEX16_1) device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568a..409314e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -24,7 +24,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end @@ -73,7 +75,9 @@ device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" + end # PCI bridge device pci 1f.0 on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index a00e2ee..faf05a2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -23,7 +23,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index e382cbd..72d064c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -31,7 +31,9 @@ register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics (PCIEX16) device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 95659be..1c97750 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -72,6 +72,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb0" "4" "PCI Express x4" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -81,6 +82,7 @@ end device pci 1c.4 on # PCIe Port #5 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xac" "4" "PCI Express x1" "0x8" end device pci 1c.5 off # PCIe Port #6 end @@ -95,6 +97,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x103c 0x1495 + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge PCI-LPC bridge subsystemid 0x103c 0x1495 @@ -214,6 +217,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x103c 0x1495 diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fad139a..3feb4e7 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -21,7 +21,8 @@ device domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge x16 + device pci 01.0 on + end # PCIe Bridge x16 device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -56,13 +57,19 @@ # Disabling 1c.0 might break IRQ settings as it enables port coalescing # There are two mini PCIe x1 sockets, so one PCIe port is unrouted - device pci 1c.0 on end # PCIe Port #1 mini PCIe x1? - device pci 1c.1 on end # PCIe Port #2 mini PCIe x1? + device pci 1c.0 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #1 mini PCIe x1? + device pci 1c.1 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #2 mini PCIe x1? device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY device pci 1c.5 on end # PCIe Port #6 FireWire - device pci 1c.6 on end # PCIe Port #7 PCIe x1 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 PCIe x1 device pci 1c.7 on end # PCIe Port #8 mini PCIe x1? device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 4db2536..58e6942 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -35,13 +35,17 @@ device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge @@ -111,7 +115,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 off end # Internal graphics end end diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2e8b8f4..4074e82 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -27,7 +27,9 @@ device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 + device pci 7.0 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # PCIE P2P bridge miniPCIe slot 1 device pci 8.0 on end # NB/SB Link P2P bridge end # agesa northbridge @@ -77,7 +79,9 @@ device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 + device pci 15.0 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # PCIe PortA miniPCIe slot 2 device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 6728228..e37dc20 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 0c0c21e..2c2900c 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c93c04f..95a6920 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -32,7 +32,9 @@ device pci 2.2 on end # LAN2 device pci 2.3 on end # LAN3 device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index b6b22cf..dac8c50 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..05dec1b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -157,6 +157,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x8086 0x2010 diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 434fb59..5784fe0 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x15d9 0x0803 inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG 10 + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xb" + end # PEG 10 device pci 01.1 on end # PEG 11 device pci 02.0 off end # IGD device pci 03.0 off end # Mini-HD audio @@ -78,7 +80,9 @@ subsystemid 0x15d9 0x1533 end end - device pci 1c.4 on end # PCIe root port 5 + device pci 1c.4 on + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" + end # PCIe root port 5 device pci 1c.5 off end # PCIe root port 6 device pci 1c.6 off end # PCIe root port 7 device pci 1c.7 off end # PCIe root port 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/32684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Gerrit-Change-Number: 32684 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t520: Add MRC settings in devicetree
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32500 Change subject: mb/lenovo/t520: Add MRC settings in devicetree ...................................................................... mb/lenovo/t520: Add MRC settings in devicetree Add support for MRC raminit using devicetree settings. Tested on Lenovo T520. Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a --- M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 3 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32500/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..d61f651 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -2,7 +2,6 @@ def_bool n select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 96d07fe..8566200 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -20,6 +20,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> @@ -95,3 +96,12 @@ void mainboard_config_superio(void) { } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..22db921 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -36,6 +36,26 @@ register "pci_mmio_size" = "2048" + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "dimm_channel0_disabled" = "2" + register "dimm_channel1_disabled" = "2" + + register "max_mem_clock_mhz" = "666" # DDR3-1333 + + register "usb_port_config" = "{ + { 1, 0, 0x0040 }, /* back, towards HDMI plugs */ + { 1, 0, 0x0040 }, /* back, towards power plug */ + { 1, 1, 0x0040 }, /* half-width miniPCIe */ + { 1, 1, 0x0040 }, /* full-width miniPCIe */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 3, 0x0040 }, /* front connector */ + }" + + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] -- To view, visit https://review.coreboot.org/c/coreboot/+/32500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a Gerrit-Change-Number: 32500 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: Enable acoustic noise mitgation for arcada platform, the slow slew ra...
by Nathan Chen (Code Review) 10 Jun '23

10 Jun '23

Nathan Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32520 Change subject: Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. ...................................................................... Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen(a)wistron.corp-partner.google.com> Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32520/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cf64c4b..77bd82a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -37,10 +37,10 @@ register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C -- To view, visit https://review.coreboot.org/c/coreboot/+/32520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e Gerrit-Change-Number: 32520 Gerrit-PatchSet: 1 Gerrit-Owner: Nathan Chen <nathan_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: sb/intel/lynxpoint: Fix flashconsole after lockdown
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33008 Change subject: sb/intel/lynxpoint: Fix flashconsole after lockdown ...................................................................... sb/intel/lynxpoint: Fix flashconsole after lockdown Same as with sb/intel/bd82x6x: SMM final locks the SPI BAR, which causes flashconsole to hang. Re-init it like SMM does with CONFIG_SPI_FLASH_SMM. Change-Id: Ie35af9610ebbba5c66351e9668e9a55cae3c7520 Signed-off-by: Daniel Maslowski <dan(a)orangecms.org> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/33008/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c1..714c696 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -965,8 +965,16 @@ RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; - if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) { + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); + } + } } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie35af9610ebbba5c66351e9668e9a55cae3c7520 Gerrit-Change-Number: 33008 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: nb/intel/sandybridge: Use understandable values for PWM backlight
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30567 Change subject: nb/intel/sandybridge: Use understandable values for PWM backlight ...................................................................... nb/intel/sandybridge: Use understandable values for PWM backlight This gets rid of setting the register values from the devicetree and makes it possible to use sensible values in the devicetree. TODO update autoport. Untested Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t520/variants/t520/devicetree.cb M src/mainboard/lenovo/t520/variants/w520/devicetree.cb M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/gma.c 31 files changed, 93 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30567/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 226ec04..4a7edc9 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "2" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001312" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,8 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x13121312" + register "pwm_freq" = "200" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index def3d1d..24cfe9a 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 07be8e7..05d7b34 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -15,8 +15,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + register "pwm_freq" = "953" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index eacfe57..d47684c 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -17,6 +17,9 @@ # Set backlight PWM values register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "pwm_freq" = "1041" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 0fdb55e..446c822 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -17,8 +17,8 @@ # For native gfx register "gfx.use_spread_spectrum_clock" = "0" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 753d286..bf3f03f 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000437" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 041b5e8..6bd4885 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 9f9efbb..adacbd9 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 9d6fe3f..c9151fc 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000385" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "26" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 56d90d3..c8fb413 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000d9c" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 2384e71..604d4bc 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000263" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "94" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 3e1f308..af14415 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -13,7 +12,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 35135a9..ddf7baa 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000060" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "600" - register "gpu_pch_backlight" = "0x041e041e" + register "pwm_freq" = "926" + register "duty_cycle" = "10" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index bed406a..0b7722e 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index a090308..809fee2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 5eb92bc..ddd4289 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 56e7f63..69e104a 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e69f727..3abf890 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -10,7 +10,8 @@ register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms - register "gpu_cpu_backlight" = "0x03d2" + register "duty_cycle" = "63" + device domain 0 on device pci 00.0 on diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 97350f3..671b45d 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 33b9368..3df91b9 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 4dcdc9d..20404c0 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 7a72b26..4af6c42 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -18,8 +18,8 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ccdff7c..2a3a30f 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cb88a7f..c60ac62 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001155" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "300" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 969ae38..85f3fbc 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a31be72..9a4866d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 4455fdb..eab2401 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x0000001a" - register "gpu_pch_backlight" = "0x002e0000" + register "pwm_freq" = "21229" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index b51c86e..ffc8b2e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000ac8" - register "gpu_pch_backlight" = "0x13120000" + register "pwm_freq" = "200" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index ed0d997..617e69d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_LGA1155 device lapic 0x0 on diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824..ebead59 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -37,8 +37,8 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + u32 pwm_freq; + u8 duty_cycle; /* * Maximum memory clock. diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9..c5cdd41 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -528,6 +528,17 @@ gtt_write(0xe4f24, 0x0ff803cf); } +static uint32_t get_raw_freq_mhz(void) +{ + uint32_t pp_divisor = (gtt_read(PCH_PP_DIVISOR) >> 8) & 0xffffff; + return (pp_divisor + 1) * 2 / 100; +} + +static uin32_t pwm_freq_to_reg(uint32_t pwm_freq) +{ + return get_raw_freq_mhz * 1000000 / (pwm_freq * 128); +} + static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_sandybridge_config *conf = dev->chip_info; @@ -582,14 +593,25 @@ gtt_write(0xc7210, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { + if (conf->pwm_freq) + { + uint32_t pwm_reg = pwm_freq_to_reg(conf->pwm_freq); + /* Set the pwm frequency */ gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + reg = pwm_reg << 16; + /* PCH PWM freq override */ + uint8_t duty_cycle = conf->duty_cycle; + if (duty_cycle == 0 || duty_cycle > 100) { + printk(BIOS_WARNING, "GMA: Invalid duty cycle, using 100%\n"); + duty_cycle = 100; + } + if (gtt_read(0xc8250) & (1 << 30)) + reg |= pwm_reg * duty_cycle / 100; + /* PCH PWM backlight freq + duty cycle*/ + gtt_write(0xc8254, reg); + /* CPU PWM backlight duty cycle */ + gtt_write(0x48250, (1 << 31)); + gtt_write(0x48254, pwm_reg * duty_cycle / 100); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Gerrit-Change-Number: 30567 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: superio/smsc/smscsuperio: Add SCH5317
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33009 Change subject: superio/smsc/smscsuperio: Add SCH5317 ...................................................................... superio/smsc/smscsuperio: Add SCH5317 According to the Linux kernel docs (Documentation/hwmon/smsc47b397), this EC is compatible with the SMSC LPC47B397-NC. No public datasheet is available. Found on a Gigabyte P34V2 board. Change-Id: Ib3227213f6a0fe4a02c5f53471f67089a8e5b4be Signed-off-by: Daniel Maslowski <dan(a)orangecms.org> --- M src/superio/smsc/smscsuperio/superio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33009/1 diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 4ce006d..523bcc1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -56,6 +56,7 @@ #define SCH3112 0x7c #define SCH3114 0x7d #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ +#define SCH5317 0x85 /* compatible with LPC47B397 */ #define SCH5027D 0x89 #define SCH4304 0x90 /* SCH4304, SCH4307 */ #define SCH5147 0xc1 @@ -136,6 +137,7 @@ {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3114, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, + {SCH5317, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, // TODO: check correctness {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}}, {SCH4304, {0, 3, 4, 5, -1, 7, -1, 11, -1, -1, -1, -1, 10, -1, -1}}, {SCH5147, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, -- To view, visit https://review.coreboot.org/c/coreboot/+/33009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3227213f6a0fe4a02c5f53471f67089a8e5b4be Gerrit-Change-Number: 33009 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/{fsp_baytrail,braswell}: Include microcode updates
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33560 Change subject: soc/intel/{fsp_baytrail,braswell}: Include microcode updates ...................................................................... soc/intel/{fsp_baytrail,braswell}: Include microcode updates Change-Id: Id4a34486ef57be6eb395dee9714cb6c01253404e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33560/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 1017d80..cd8343e 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -65,6 +65,8 @@ verstage-y += pmutil.c verstage-y += tsc_freq.c +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4c-*) + CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index ca2b353..b1f13fa 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += i2c.c ramstage-y += gfx.c +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-37-*) + CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp -- To view, visit https://review.coreboot.org/c/coreboot/+/33560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4a34486ef57be6eb395dee9714cb6c01253404e Gerrit-Change-Number: 33560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Update CBFS
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33664 Change subject: Documentation: Update CBFS ...................................................................... Documentation: Update CBFS Update some parts to match current implementation. Change-Id: I84d07ae1c5c1ded2b9ab5934e2babbbabb749440 --- M Documentation/lib/cbfs.md M Documentation/lib/payloads/selfboot.md 2 files changed, 46 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33664/1 diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md index 83d8b44..ce87b78 100644 --- a/Documentation/lib/cbfs.md +++ b/Documentation/lib/cbfs.md @@ -7,7 +7,7 @@ ## Introduction -This document describes the coreboot CBFS specification (from here +This document describes the coreboot filesystem specification (from here referred to as CBFS). CBFS is a scheme for managing independent chunks of data in a system ROM. Though not a true filesystem, the style and concepts are similar. @@ -15,7 +15,7 @@ ## Architecture -The CBFS architecture looks like the following: +The CBFS on x86 architecture looks like the following: ``` /---------------\ <-- Start of ROM @@ -49,11 +49,11 @@ The CBFS architecture consists of a binary associated with a physical ROM disk referred hereafter as the ROM. A number of independent of -components, each with a header prepended on to data are located within -the ROM. The components are nominally arranged sequentially, though they +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they are aligned along a pre-defined boundary. -The bootblock occupies the last 20k of the ROM. Within +On x86 legacy the bootblock occupies the last 20k of the ROM. Within the bootblock is a master header containing information about the ROM including the size, alignment of the components, and the offset of the start of the first CBFS component within the ROM. @@ -62,14 +62,13 @@ The master header contains essential information about the ROM that is used by both the CBFS implementation within coreboot at runtime as well -as host based utilities to create and manage the ROM. The master header -will be located somewhere within the bootblock (last 20k of the ROM). A -pointer to the location of the header will be located at offset --4 from the end of the ROM. This translates to address 0xFFFFFFFC on a -normal x86 system. The pointer will be to physical memory somewhere -between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot -to locate the header at run time. Build time utilities will -need to read the pointer and do the appropriate math to locate the header. +as host based utilities to create and manage the ROM. The master header +will be located at the start of CBFS. A pointer to the location of the +header will be located at offset -4 from the end of the ROM. +This translates to address 0xFFFFFFFC on a normal x86 system. +This makes it easier for coreboot to locate the header at run time. +Build time utilities will need to read the pointer and do the appropriate +math to locate the header. The following is the structure of the master header: @@ -114,16 +113,16 @@ for. ## Bootblock -The bootblock is a mandatory component in the ROM. It is located in the -last 20k of the ROM space, and contains, among other things, the location of the -master header and the entry point for the loader firmware. The bootblock -does not have a component header attached to it. +The bootblock is a mandatory component in the ROM. On x86 legacy it is located +at the end of the CBFS, and contains, among other things, the location of the +master header and the entry point for the loader firmware. On other +architectures the bootblock might not be part of the CBFS. ## Components CBFS components are placed in the ROM starting at 'offset' specified in -the master header and ending at the bootblock. Thus the total size -available for components in the ROM is (ROM size - 20k - 'offset'). +the master header and ending at the end of the CBFS. Thus the total size +available for components in the ROM is (ROM size - 'offset'). Each CBFS component is to be aligned according to the 'align' value in the header. Thus, if a component of size 1052 is located at offset 0 with an 'align' @@ -208,10 +207,10 @@ #### Stages -Stages are code loaded by coreboot during the boot process. They are -essential to a successful boot. Stages are comprised of a single blob +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob of binary data that is to be loaded into a particular location in memory -and executed. The uncompressed header contains information about how +and executed. The uncompressed header contains information about how large the data is, and where it should be placed, and what additional memory needs to be cleared. @@ -244,8 +243,8 @@ `compression` is an integer defining how the data is compressed. There are three compression types defined by this version of the standard: -none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional -types may be added assuming that coreboot understands how to handle the scheme. +none (0x0), lzma (0x1), and lz4 (0x02), though additional types may be +added assuming that coreboot understands how to handle the scheme. `entry` is a 64 bit value indicating the location where the program counter should jump following the loading of the stage. This should be @@ -271,13 +270,13 @@ #### Payloads Payloads are loaded by coreboot following the boot process. +The default payloads supported by coreboot are [SELF] payloads. -Stages are assigned a component value of 0x20. When coreboot sees this +[SELF] stages are assigned a component value of 0x20. When coreboot sees this component type, it knows that it should pass the data to a sub-function -that will process the payload. Furthermore, other run time applications such -as 'bayou' may easily index all available payloads -on the system by searching for the payload type. - +that will process the payload. Furthermore, other run time applications such +as 'bayou' may easily index all available payloads on the system by searching +for the payload type. The following is the format of a stage component: @@ -338,9 +337,9 @@ `compression` is the compression scheme for the segment. Each segment can be independently compressed. There are three compression types defined by -this version of the standard: none (0x0), lzma (0x1), and nrv2b -(0x02, deprecated), though additional types may be added assuming that -coreboot understands how to handle the scheme. +this version of the standard: none (0x0), lzma (0x1), and lz4 (0x02), though +additional types may be added assuming that coreboot understands how to handle +the scheme. `offset` is the address of the data within the component, starting from the component header. @@ -355,6 +354,13 @@ The data will located immediately following the last segment. +#### FIT payload + +A payload of type [FIT] is supported on some architectures. + +[FIT] stages are assigned a component value of 0x21 and do not support +compressions at all. + #### Option ROMS The third specified component type will be Option ROMs. Option ROMS will @@ -364,8 +370,11 @@ #### NULL -There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is -the "don't care" component type. This can be used when the component +There is a 4th component type, defined as NULL (0xFFFFFFFF, 0x00000000). +This is the "don't care" component type. This can be used when the component type is not necessary (such as when the name of the component is unique. i.e. option_table). It is recommended that all components be assigned a unique type, but NULL can be used when the type does not matter. + +[FIT]: payloads/fit.md +[SELF]: payloads/selfboot.md diff --git a/Documentation/lib/payloads/selfboot.md b/Documentation/lib/payloads/selfboot.md index 62a4393..791d6c0 100644 --- a/Documentation/lib/payloads/selfboot.md +++ b/Documentation/lib/payloads/selfboot.md @@ -18,6 +18,8 @@ address they specify. If it's not possible to load the payload at the specified address, the system won't boot. +Implementations details can be found in the [CBFS] documentation. + ### Calling conventions The SELF payload is called with a pointer to the coreboot tables as first argument. @@ -26,3 +28,4 @@ and a pointer to the *FDT* as arguments. [RISC-V]: ../../arch/riscv/index.md +[CBFS]: ../cbfs.md -- To view, visit https://review.coreboot.org/c/coreboot/+/33664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84d07ae1c5c1ded2b9ab5934e2babbbabb749440 Gerrit-Change-Number: 33664 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload/drivers/i8042: ignore special keys on keyboard
by Matt Delco (Code Review) 10 Jun '23

10 Jun '23

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33303 Change subject: libpayload/drivers/i8042: ignore special keys on keyboard ...................................................................... libpayload/drivers/i8042: ignore special keys on keyboard Some keyboards have a fn-key (and/or fn-mode lock) that can generate 0xe0-prefixed scan codes for certain keys. Previously the 0xe0 prefix state wasn't tracked (it was ignored), so these scan codes could be misinterpreted as non-0xe0 presses (e.g., 'mute' generates 0xe0 0x20 but this would get interpreted as 0x20 and be treated as a 'D' press). Most 0xe0-prefixed codes (besides those for the 10-key) are irrelevant for firmware so we'll ignore them. BUG=none BRANCH=none TEST=local build and flash. Verified that special keys are no longer interpreted as other keystrokes. Change-Id: Ie6a828b6a0a3ab47456d6db2db504aa0d7aefc28 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33303/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 3e5f988..bca916f 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -235,12 +235,30 @@ unsigned char ch; int shift; int ret = 0; - - while (!keyboard_havechar()) ; + static int prior_special = 0; ch = keyboard_get_scancode(); - if (!(ch & 0x80) && ch < 0x59) { + if (prior_special) { + if (ch == 0x5e) + ret = POWER_BUTTON; + /* + * For now 0xe0 with 0x1c, 0x35, or 0x47 - 0x53 is the same as + * non-0xe0. For 10-key scan codes 0x47-0x53 it's probably more + * accurate for the non-0xe0 presses to use the numeric + * interpretation of the key (i.e., when num lock is on) and + * the 0xe0 prefixed versions should use the non-numeric + * interpretation (i.e., num lock off). However, the existing + * tables are using the non-numeric interpretation so for now + * the 0xe0 presses can use what's in the table for non-0xe0 + * presses. The main exception is that shift+'/' on the keypad + * (0xe0 0x35) should still produce a '/' (vs. a '?' like on + * the key that's to the left of the right-shift on English + * keyboards) so we'll ignore the shift status. + */ + else if (ch == 0x1c || ch == 0x35 || (ch >= 0x47 && ch <= 0x53)) + ret = map->map[0][ch]; + } else if (ch < 0x59) { /* implies !(ch & 0x80), i.e., key press */ shift = (modifier & KB_MOD_SHIFT) ^ (modifier & KB_MOD_CAPSLOCK) ? 1 : 0; @@ -265,8 +283,8 @@ } } - if (ch == 0x5e) - ret = POWER_BUTTON; + /* sequence 0xe0 0xe0 should not leave prior_special set. */ + prior_special = !prior_special && ch == 0xe0; return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6a828b6a0a3ab47456d6db2db504aa0d7aefc28 Gerrit-Change-Number: 33303 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST] mb/google/hatch: Update AC/DC loadline values for PnP
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33741 to review the following change. Change subject: [TEST] mb/google/hatch: Update AC/DC loadline values for PnP ...................................................................... [TEST] mb/google/hatch: Update AC/DC loadline values for PnP Update the AC/DC loadline values for all domains for PnP. BUG=None BRANCH=None TEST=Build and Boot hatch EVT for PnP Change-Id: Ie736c401bc41413aacc8f1abd3c3bad2bbf8b713 igned-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33741/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a66c743..70d6772 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,82 @@ # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(85), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms -- To view, visit https://review.coreboot.org/c/coreboot/+/33741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie736c401bc41413aacc8f1abd3c3bad2bbf8b713 Gerrit-Change-Number: 33741 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019