coreboot-gerrit September 2019

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Change in coreboot[master]: src: Remove unneeded 'include <delay.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34230 ) Change subject: src: Remove unneeded 'include <delay.h>' ...................................................................... src: Remove unneeded 'include <delay.h>' Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/ipmi/ipmi_kcs_ops.c M src/mainboard/getac/p470/mainboard.c M src/soc/mediatek/common/rtc.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/gpio.c M src/soc/qualcomm/qcs405/i2c.c M src/soc/qualcomm/sdm845/usb.c 7 files changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34230/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0cc4e0a..8e02b28 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -31,7 +31,7 @@ #include <smbios.h> #endif #include <version.h> -#include <delay.h> + #include "ipmi_kcs.h" #include "chip.h" diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 813b1d6..da90349 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <delay.h> #include <drivers/intel/gma/int15.h> diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fe252b5..080f334 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/pmic_wrap.h> diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 56824a4..8a17e37 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -14,8 +14,6 @@ #include <console/console.h> #include <device/mmio.h> -#include <types.h> -#include <delay.h> #include <timestamp.h> #include <commonlib/helpers.h> #include <string.h> diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 7b2238d..1d18250 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <types.h> -#include <delay.h> #include <timestamp.h> #include <gpio.h> diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 94f8e0d..77c381c 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -31,7 +31,6 @@ #include <assert.h> #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <stdlib.h> #include <string.h> diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index c7d65e6..062cd94 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -17,7 +17,6 @@ #include <lib.h> #include <stdlib.h> #include <console/console.h> -#include <delay.h> #include <soc/usb.h> #include <soc/clock.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Gerrit-Change-Number: 34230 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: src: Remove unused 'include <halt.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35124 ) Change subject: src: Remove unused 'include <halt.h>' ...................................................................... src: Remove unused 'include <halt.h>' Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/sdm845/aop_load_reset.c M src/southbridge/intel/ibexpeak/smihandler.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35124/1 diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9..e89e132 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -16,7 +16,6 @@ #include <string.h> #include <arch/cache.h> #include <cbfs.h> -#include <halt.h> #include <console/console.h> #include <timestamp.h> #include <soc/mmu.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a254bd7..e84b4b95 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <elog.h> -#include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <southbridge/intel/common/finalize.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/35124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Gerrit-Change-Number: 35124 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: src/vendorcode: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33682 Change subject: src/vendorcode: Use 'include <stdlib.h>' when appropriate ...................................................................... src/vendorcode: Use 'include <stdlib.h>' when appropriate Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33682/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index 8e348d0..8616fb6 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index f7d631f..c6017b2 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,7 +37,9 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> + #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" #include "libbdk-hal/if/bdk-if.h" diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..ed003dc 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -36,8 +36,11 @@ * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ + #include <bdk.h> #include <string.h> +#include <stdlib.h> + #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-hal/bdk-ecam.h" diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 385acee..e3fc993 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -40,6 +40,7 @@ #include "dram-internal.h" #include <string.h> +#include <stdlib.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> #include <libbdk-hal/bdk-clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Gerrit-Change-Number: 33682 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: AGESA: Fix discovery of IO APICs number
by Krystian Hebel (Code Review) 18 Dec '19

18 Dec '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34589 ) Change subject: AGESA: Fix discovery of IO APICs number ...................................................................... AGESA: Fix discovery of IO APICs number Number of IO APICs are hardcoded. This fix reads this number from the default values obtained by creating a structure for a parameter block of an AGESA. While it is possible to modify NumberOfIoApics in callouts, every platform currently in the tree goes with the default value. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 --- M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 4 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34589/1 diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..7964f4e 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -297,6 +297,23 @@ return (final < AGESA_FATAL) ? 0 : -1; } +int amd_get_ioapic_num(void) { + AMD_INTERFACE_PARAMS aip; + AMD_EARLY_PARAMS *params; + int ret; + + agesa_locate_image(&aip.StdHeader); + + amd_create_struct(&aip, AMD_INIT_EARLY, NULL, 0); + + params = (AMD_EARLY_PARAMS *)aip.NewStructPtr; + ret = params->PlatformConfig.NumberOfIoApics; + + amd_release_struct(&aip); + + return ret; +} + #if ENV_RAMSTAGE static void amd_bs_ramstage_init(void *arg) diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 17819e9..97eba2f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -39,6 +39,8 @@ void amd_initmmio(void); void amd_initenv(void); +int amd_get_ioapic_num(void); + void *GetHeapBase(void); void EmptyHeap(void); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c6457a3..e9a1e05 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -870,7 +870,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 928d9d2..b3b68f9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -896,7 +896,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; -- To view, visit https://review.coreboot.org/c/coreboot/+/34589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 Gerrit-Change-Number: 34589 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: TEST-ONLY: add support anx7625 driver
by jitao shi (Code Review) 17 Dec '19

17 Dec '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35623 ) Change subject: TEST-ONLY: add support anx7625 driver ...................................................................... TEST-ONLY: add support anx7625 driver Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- A src/drivers/analogix/anx7625/Kconfig A src/drivers/analogix/anx7625/Makefile.inc A src/drivers/analogix/anx7625/anx7625.c A src/drivers/analogix/anx7625/anx7625.h M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_anx7625.c 7 files changed, 1,423 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35623/1 diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig new file mode 100644 index 0000000..afe0338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config DRIVER_ANALOGIX_ANX7625 + bool + default n + help + Analogix anx7625 MIPI DSI to eDP Converter diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc new file mode 100644 index 0000000..9a46338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += anx7625.c diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c new file mode 100644 index 0000000..676872b --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -0,0 +1,948 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Analogix Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <console/console.h> +#include <timer.h> +#include <string.h> + +#include "anx7625.h" + +/* + * there is a sync issue while access I2C register between AP(CPU) and + * internal firmware(OCM), to avoid the race condition, AP should access + * the reserved slave address before slave address occurs changes. + */ +static int i2c_access_workaround(uint8_t bus, uint8_t saddr) +{ + uint8_t offset; + static uint8_t saddr_backup = 0; + int ret = 0; + + if (saddr != saddr_backup) { + saddr_backup = saddr; + + if (saddr == TCPC_INTERFACE_ADDR) + offset = RSVD_00_ADDR; + else if (saddr == TX_P0_ADDR) + offset = RSVD_D1_ADDR; + else if (saddr == TX_P1_ADDR) + offset = RSVD_60_ADDR; + else if (saddr == RX_P0_ADDR) + offset = RSVD_39_ADDR; + else if (saddr == RX_P1_ADDR) + offset = RSVD_7F_ADDR; + else + offset = RSVD_00_ADDR; + + ret = i2c_writeb(bus, saddr, offset, 0x00); + if (ret < 0) + printk(BIOS_INFO, "failed to access i2c %x\n:%x", + saddr, offset); + } + + return ret; +} + +static int anx7625_reg_read(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t *val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_readb(bus, saddr, offset, val); + if (ret < 0) { + printk(BIOS_INFO, "read i2c failed id=%x:%x\n", + saddr, offset); + return ret; + } + + return *val; +} + +static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t len, uint8_t *buf) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); + if (ret < 0) + printk(BIOS_INFO, "read i2c block failed id=%x:%x\n", + saddr, reg_addr); + + return ret; +} + +static int anx7625_reg_write(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t reg_val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_writeb(bus, saddr, reg_addr, reg_val); + + if (ret < 0) + printk(BIOS_INFO, "failed to write i2c id=%x\n:%x", + saddr, reg_addr); + + return ret; +} + +static int anx7625_write_or(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + uint8_t val; + int ret; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val | (mask))); +} + +static int anx7625_write_and(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + int ret; + uint8_t val; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val & (mask))); +} + +static int wait_aux_op_finish(uint8_t bus) +{ + uint8_t val; + int ret; + int loop; + + ret = -1; + for (loop = 0; loop < 150; loop++) { + mdelay(2); + anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); + if (!(val & AP_AUX_CTRL_OP_EN)) { + ret = 0; + break; + } + } + + if (ret != 0) { + printk(BIOS_INFO, "wait aux operation failed.\n"); + } else { + ret = anx7625_reg_read(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, &val); + if ((ret < 0) || (val & 0x0F)) { + printk(BIOS_INFO, "aux status %02x\n", val); + ret = -1; + } + } + + return ret; +} + +static unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long iterations = 0L; + + if (a == 0) + return b; + + while (b != 0) { + if (a > b) + a = a - b; + else + b = b - a; + iterations++; + } + + return a; +} + +/* reduction of fraction a/b */ +static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) +{ + unsigned long gcd_num; + unsigned long tmp_a, tmp_b; + u32 i = 1; + + gcd_num = gcd(*a, *b); + *a /= gcd_num; + *b /= gcd_num; + + tmp_a = *a; + tmp_b = *b; + + while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { + i++; + *a = tmp_a / i; + *b = tmp_b / i; + } + + /* + * in the end, make a, b larger to have higher ODFC PLL + * output frequency accuracy + */ + while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { + *a <<= 1; + *b <<= 1; + } + + *a >>= 1; + *b >>= 1; +} + +static int anx7625_calculate_m_n(u32 pixelclock, + unsigned long *m, unsigned long *n, uint8_t *post_divider) +{ + if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { + /* pixel clock frequency is too high */ + printk(BIOS_INFO, "pixelclock too high, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); + return 1; + } + + if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { + /* pixel clock frequency is too low */ + printk(BIOS_INFO, "pixelclock too low, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); + return 1; + } + + *post_divider = 1; + + for (*post_divider = 1; + pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + for (*post_divider = 1; + (pixelclock < + (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + printk(BIOS_INFO, "cannot find property post_divider(%d)\n", + *post_divider); + return 1; + } + } + + /* patch to improve the accuracy */ + if (*post_divider == 7) { + /* 27,000,000 is not divisible by 7 */ + *post_divider = 8; + } else if (*post_divider == 11) { + /* 27,000,000 is not divisible by 11 */ + *post_divider = 12; + } else if ((*post_divider == 13) || (*post_divider == 14)) { + /*27,000,000 is not divisible by 13 or 14*/ + *post_divider = 15; + } + + if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { + printk(BIOS_INFO, "act clock(%u) large than maximum(%lu)\n", + pixelclock * (*post_divider), + PLL_OUT_FREQ_ABS_MAX); + return 1; + } + + + *m = pixelclock * 599 / 600; + *n = XTAL_FRQ / (*post_divider); + + anx7625_reduction_of_a_fraction(m, n); + + return 0; +} + +static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider) +{ + int ret; + + /* config input reference clock frequency 27MHz/19.2MHz */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + ~(REF_CLK_27000kHz << MIPI_FREF_D_IND)); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + (REF_CLK_27000kHz << MIPI_FREF_D_IND)); + /* post divider */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, 0x0f); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, + post_divider << 4); + + /* add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_VCO_TUNE_REG_VAL); + + /* reset ODFC PLL */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_RESET_N); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + MIPI_PLL_RESET_N); + + if (ret < 0) + printk(BIOS_INFO, "IO error.\n"); + + return ret; +} + +static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) +{ + unsigned long m, n; + u16 htotal; + int ret; + uint8_t post_divider = 0; + + ret = anx7625_calculate_m_n(dt->pixelclock * 1000, + &m, &n, &post_divider); + + if (ret != 0) { + printk(BIOS_INFO, "cannot get property m n value.\n"); + return -1; + } + + printk(BIOS_INFO, "compute M(%lu), N(%lu), divider(%d).\n", + m, n, post_divider); + + /* configure pixel clock */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L, + (dt->pixelclock / 1000) & 0xFF); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_H, + (dt->pixelclock / 1000) >> 8); + /* lane count */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 0xfc); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 3); + + /* Htotal */ + htotal = dt->hactive + dt->hfront_porch + + dt->hback_porch + dt->hsync_len; + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); + /* Hactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_L, dt->hactive & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_H, dt->hactive >> 8); + /* HFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_L, dt->hfront_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_H, + dt->hfront_porch >> 8); + /* HWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_L, dt->hsync_len); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_H, dt->hsync_len >> 8); + /* HBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_L, dt->hback_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_H, dt->hback_porch >> 8); + /* Vactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_L, + dt->vactive); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_H, + dt->vactive >> 8); + /* VFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_FRONT_PORCH, dt->vfront_porch); + /* VWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_SYNC_WIDTH, dt->vsync_len); + /* VBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_BACK_PORCH, dt->vback_porch); + /* M value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_7_0, (m & 0xff)); + /* N value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, + (n & 0xff)); + /* diff */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_DIGITAL_ADJ_1, 0x37); + + ret |= anx7625_odfc_config(bus, post_divider - 1); + + if (ret < 0) + printk(BIOS_INFO, "mipi dsi setup IO error.\n"); + + return ret; +} + +static int anx7625_swap_dsi_lane3(uint8_t bus) +{ + int ret; + uint8_t val; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access MIPI_SWAP.\n"); + return -1; + } + + val |= (1 << MIPI_SWAP_CH3); + return anx7625_reg_write(bus, RX_P1_ADDR, MIPI_SWAP, val); +} + +static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt) + +{ + int val, ret; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_swap_dsi_lane3(bus); + if (ret < 0) { + printk(BIOS_INFO, "IO error : swap dsi lane 3 failed.\n"); + return ret; + } + + /* DSI clock settings */ + val = (0 << MIPI_HS_PWD_CLK) | + (0 << MIPI_HS_RT_CLK) | + (0 << MIPI_PD_CLK) | + (1 << MIPI_CLK_RT_MANUAL_PD_EN) | + (1 << MIPI_CLK_HS_MANUAL_PD_EN) | + (0 << MIPI_CLK_DET_DET_BYPASS) | + (0 << MIPI_CLK_MISS_CTRL) | + (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); + ret = anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PHY_CONTROL_3, val); + + /* + * Decreased HS prepare tg delay from 160ns to 80ns work with + * a) Dragon board 810 series (Qualcomm AP) + * b) Moving Pixel DSI source (PG3A pattern generator + + * P332 D-PHY Probe) default D-PHY tg + * 5ns/step + */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_TIME_HS_PRPR, 0x10); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_18, + SELECT_DSI<<MIPI_DPI_SELECT); /* enable DSI mode*/ + + ret |= anx7625_dsi_video_config(bus, dt); + if (ret < 0) { + printk(BIOS_INFO, "dsi video tg config failed\n"); + return ret; + } + + /* toggle m, n ready */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); + mdelay(1); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + MIPI_M_NUM_READY | MIPI_N_NUM_READY); + + /* configure integer stable register */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_VIDEO_STABLE_CNT, 0x02); + /* power on MIPI RX */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x00); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x80); + + if (ret < 0) + printk(BIOS_INFO, "IO error : mipi dsi enable init failed.\n"); + + return ret; +} + +static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) +{ + int ret; + + printk(BIOS_INFO, "config dsi.\n"); + + /* DSC disable */ + ret = anx7625_write_and(bus, RX_P0_ADDR, + R_DSC_CTRL_0, ~DSC_EN); + + ret |= anx7625_api_dsi_config(bus, dt); + + if (ret < 0) { + printk(BIOS_INFO, "IO error : api dsi config error.\n"); + } else { + /* set MIPI RX EN */ + ret = anx7625_write_or(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_MIPI_RX_EN); + /* clear mute flag */ + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AV_STATUS, ~AP_MIPI_MUTE); + if (ret < 0) + printk(BIOS_INFO, "IO error : enable mipi rx failed.\n"); + else + printk(BIOS_INFO, "success to config DSI\n"); + } + + return ret; +} + +static int sp_tx_rst_aux(uint8_t bus) +{ + int ret; + + ret = anx7625_write_or(bus, TX_P2_ADDR, RST_CTRL2, + AUX_RST); + ret |= anx7625_write_and(bus, TX_P2_ADDR, RST_CTRL2, + ~AUX_RST); + return ret; +} + +static int sp_tx_aux_wr(uint8_t bus, uint8_t offset) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, offset); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_aux_rd(uint8_t bus, uint8_t len_cmd) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, len_cmd); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_get_edid_block(uint8_t bus) +{ + int ret = 0; + uint8_t val = 0; + + sp_tx_aux_wr(bus, 0x7e); + sp_tx_aux_rd(bus, 0x01); + ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_BUFF_START, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access AUX BUFF.\n"); + return -1; + } + + printk(BIOS_INFO, " EDID Block = %d\n", val + 1); + + if (val > 3) + val = 1; + + return val; +} + +static int edid_read(uint8_t bus, + uint8_t offset, uint8_t *pblock_buf) +{ + uint8_t c, cnt = 0; + + c = 0; + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + sp_tx_rst_aux(bus); + printk(BIOS_INFO, "edid read failed, reset!\n"); + cnt++; + } else { + anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, pblock_buf); + return 0; + } + } + + return 1; + +} + +static int segments_edid_read(uint8_t bus, + uint8_t segment, uint8_t *buf, uint8_t offset) +{ + uint8_t c, cnt = 0; + int ret; + + /* write address only */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x30); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, + AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); + + ret |= wait_aux_op_finish(bus); + /* write segment address */ + ret |= sp_tx_aux_wr(bus, segment); + /* data read */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + if (ret < 0) { + printk(BIOS_INFO, "IO error : aux initial failed.\n"); + return ret; + } + + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + ret = sp_tx_rst_aux(bus); + printk(BIOS_INFO, "segment read failed, reset!\n"); + cnt++; + } else { + ret = anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, buf); + return ret; + } + } + + return ret; +} + +static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf) +{ + uint8_t offset, edid_pos; + int count, blocks_num; + uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; + uint8_t i, j; + uint8_t g_edid_break = 0; + int ret; + + /* address initial */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_15_8, 0); + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AUX_ADDR_19_16, 0xf0); + if (ret < 0) { + printk(BIOS_INFO, "access aux channel IO error.\n"); + return -1; + } + + blocks_num = sp_tx_get_edid_block(bus); + if (blocks_num < 0) + return blocks_num; + + count = 0; + + do { + switch (count) { + case 0: + case 1: + for (i = 0; i < 8; i++) { + offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; + g_edid_break = edid_read(bus, offset, + pblock_buf); + + if (g_edid_break == 1) + break; + + memcpy(&pedid_blocks_buf[offset], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + } + + break; + case 2: + offset = 0x00; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + case 3: + offset = 0x80; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + default: + break; + } + + count++; + + } while (blocks_num >= count); + + /* reset aux channel */ + sp_tx_rst_aux(bus); + + return blocks_num; +} + +static void anx7625_power_on(void) +{ +#ifdef ANXGPIO + /* power on pin enable */ + gpio_set_value(gpio_p_on, 1); + mdelay(10); + /* power reset pin enable */ + gpio_set_value(gpio_reset, 1); + mdelay(10); +#endif + printk(BIOS_INFO, "Anx7625 power on !\n"); +} + +static void anx7625_power_standby(void) +{ +#ifdef ANXGPIO + gpio_set_value(gpio_reset, 0); + mdelay(1); + gpio_set_value(gpio_p_on, 0); + mdelay(1); +#endif + printk(BIOS_INFO, "anx7625 power down\n"); +} + +static void anx7625_disable_pd_protocol(uint8_t bus) +{ + int ret; + + /* reset main ocm */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x40); + /* Disable PD */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_DISABLE_PD); + /* release main ocm */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x00); + + if (ret < 0) + printk(BIOS_INFO, "disable PD feature failed.\n"); + else + printk(BIOS_INFO, "disable PD feature succeeded.\n"); +} + +#define FLASH_LOAD_STA 0x05 +#define FLASH_LOAD_STA_CHK (1<<7) +static void anx7625_power_on_init(uint8_t bus) +{ + int retry_count, i; + int ret = 0; + uint8_t val; + + for (retry_count = 0; retry_count < 3; retry_count++) { + anx7625_power_on(); + + anx7625_reg_write(bus, RX_P0_ADDR, XTAL_FRQ_SEL, XTAL_FRQ_27M); + + for (i = 0; i < OCM_LOADING_TIME; i++) { + /* check interface workable */ + ret = anx7625_reg_read(bus, RX_P0_ADDR, + FLASH_LOAD_STA, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access flash load.\n"); + return; + } + if ((val & FLASH_LOAD_STA_CHK) == FLASH_LOAD_STA_CHK) { + printk(BIOS_INFO, "interface initialization\n"); + anx7625_disable_pd_protocol(bus); + + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_VERSION, &val); + + printk(BIOS_INFO, "Firmware ver %02x:", val); + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_REVERSION, &val); + printk(BIOS_INFO, "%02x\n", val); + return; + } + mdelay(1); + } + anx7625_power_standby(); + } +} + +static void anx7625_start_dp_work(uint8_t bus) +{ + int ret; + uint8_t val; + + /* not support HDCP */ + ret = anx7625_write_and(bus, RX_P1_ADDR, 0xee, 0x9f); + + /* try auth flag */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xec, 0x10); + /* interrupt for DRM */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xff, 0x01); + if (ret < 0) + return; + + ret = anx7625_reg_read(bus, RX_P1_ADDR, 0x86, &val); + if (ret < 0) + return; + + printk(BIOS_INFO, "Secure OCM version=%02x\n", val); +} + +static int anx7625_hpd_change_detect(uint8_t bus) +{ + int ret; + uint8_t status; + + ret = anx7625_reg_read(bus, RX_P0_ADDR, + SYSTEM_STSTUS, &status); + if (ret < 0) { + printk(BIOS_INFO, "IO error : clear interrupt status.\n"); + return ret; + } + + if (status & HPD_STATUS) { + anx7625_start_dp_work(bus); + printk(BIOS_INFO, "hpd received 0x7e:0x45=%x\n", status); + return 1; + } + return 0; +} + +static void anx7625_parse_edid(struct edid *edid, struct display_timing *dt) +{ + dt->pixelclock = edid->mode.pixel_clock; + + dt->hactive = edid->mode.ha; + dt->hsync_len = edid->mode.hspw; + dt->hback_porch = edid->mode.hbl - edid->mode.hso - + edid->mode.hborder - edid->mode.hspw; + dt->hfront_porch = edid->mode.hso - edid->mode.hborder; + + dt->vactive = edid->mode.va; + dt->vsync_len = edid->mode.vspw; + dt->vfront_porch = edid->mode.vso - edid->mode.vborder; + dt->vback_porch = edid->mode.vbl - edid->mode.vso - + edid->mode.vspw - edid->mode.vborder; + + printk(BIOS_INFO, "pixelclock(%d).\n", dt->pixelclock); + printk(BIOS_INFO, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", + dt->hactive, + dt->hsync_len, + dt->hfront_porch, + dt->hback_porch); + printk(BIOS_INFO, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", + dt->vactive, + dt->vsync_len, + dt->vfront_porch, + dt->vback_porch); +} + +int anx7625_dp_start(uint8_t bus, struct edid *edid) +{ + int ret; + struct display_timing dt; + + anx7625_parse_edid(edid, &dt); + + ret = anx7625_dsi_config(bus, &dt); + if (ret < 0) + printk(BIOS_INFO, "MIPI phy setup error.\n"); + else + printk(BIOS_INFO, "MIPI phy setup OK.\n"); + + return ret; +} + +int anx7625_dp_get_edid(uint8_t bus, struct edid *out) +{ + int block_num; + int ret; + u8 edid[ONE_BLOCK_SIZE * 4]; + + block_num = sp_tx_edid_read(bus, edid); + if (block_num < 0) { + printk(BIOS_INFO, "Failed to get eDP EDID.\n"); + return -1; + } + + ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); + if (ret != EDID_CONFORMANT) { + printk(BIOS_INFO, "Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int anx7625_init(uint8_t bus) +{ + int cnt; + + anx7625_power_on_init(bus); + + for (cnt = 0; cnt < 50; cnt++) { + mdelay(10); + if (anx7625_hpd_change_detect(bus)) + return 0; + } + + return -1; +} + diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h new file mode 100644 index 0000000..d2391a6 --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. + * + */ + + +#include <edid.h> +#include <types.h> + +#ifndef __ANX7625_H__ +#define __ANX7625_H__ + +#ifndef LOG_TAG +#define LOG_TAG "anx7625dp" +#endif + +#define ANX7625_DRV_VERSION "0.1.04" + +/* Loading OCM re-trying times */ +#define OCM_LOADING_TIME 10 + +/********* ANX7625 Register **********/ +#define ANXI2CSIM +#ifdef ANXI2CSIM +#define TX_P0_ADDR 0x38 +#define TX_P1_ADDR 0x3D +#define TX_P2_ADDR 0x39 +#define RX_P0_ADDR 0x3F +#define RX_P1_ADDR 0x42 +#define RX_P2_ADDR 0x2A +#define TCPC_INTERFACE_ADDR 0x2C +#else +#define TX_P0_ADDR 0x70 +#define TX_P1_ADDR 0x7A +#define TX_P2_ADDR 0x72 +#define RX_P0_ADDR 0x7e +#define RX_P1_ADDR 0x84 +#define RX_P2_ADDR 0x54 +#define TCPC_INTERFACE_ADDR 0x58 +#endif + +#define RSVD_00_ADDR 0x00 +#define RSVD_D1_ADDR 0xD1 +#define RSVD_60_ADDR 0x60 +#define RSVD_39_ADDR 0x39 +#define RSVD_7F_ADDR 0x7F + +/* anx7625 clock frequency in Hz */ +#define XTAL_FRQ (27*1000000) + +#define POST_DIVIDER_MIN 1 +#define POST_DIVIDER_MAX 16 +#define PLL_OUT_FREQ_MIN 520000000UL +#define PLL_OUT_FREQ_MAX 730000000UL +#define PLL_OUT_FREQ_ABS_MIN 300000000UL +#define PLL_OUT_FREQ_ABS_MAX 800000000UL +#define MAX_UNSIGNED_24BIT 16777215UL + +/***************************************************************/ +/* Register definition of device address 0x58 */ + +#define PRODUCT_ID_L 0x02 +#define PRODUCT_ID_H 0x03 + +#define INTR_ALERT_1 0xCC +#define INTR_SOFTWARE_INT (1<<3) +#define INTR_RECEIVED_MSG (1<<5) + +#define SYSTEM_STSTUS 0x45 +#define INTERFACE_CHANGE_INT 0x44 +#define HPD_STATUS_CHANGE 0x80 +#define HPD_STATUS 0x80 + +/******** END of I2C Address 0x58 ********/ + +/***************************************************************/ +/* Register definition of device address 0x70 */ +#define I2C_ADDR_70_DPTX 0x70 + +#define SP_TX_LINK_BW_SET_REG 0xA0 +#define SP_TX_LANE_COUNT_SET_REG 0xA1 + +#define M_VID_0 0xC0 +#define M_VID_1 0xC1 +#define M_VID_2 0xC2 +#define N_VID_0 0xC3 +#define N_VID_1 0xC4 +#define N_VID_2 0xC5 + +/***************************************************************/ +/* Register definition of device address 0x72 */ +#define AUX_RST 0x04 +#define RST_CTRL2 0x07 + +#define SP_TX_TOTAL_LINE_STA_L 0x24 +#define SP_TX_TOTAL_LINE_STA_H 0x25 +#define SP_TX_ACT_LINE_STA_L 0x26 +#define SP_TX_ACT_LINE_STA_H 0x27 +#define SP_TX_V_F_PORCH_STA 0x28 +#define SP_TX_V_SYNC_STA 0x29 +#define SP_TX_V_B_PORCH_STA 0x2A +#define SP_TX_TOTAL_PIXEL_STA_L 0x2B +#define SP_TX_TOTAL_PIXEL_STA_H 0x2C +#define SP_TX_ACT_PIXEL_STA_L 0x2D +#define SP_TX_ACT_PIXEL_STA_H 0x2E +#define SP_TX_H_F_PORCH_STA_L 0x2F +#define SP_TX_H_F_PORCH_STA_H 0x30 +#define SP_TX_H_SYNC_STA_L 0x31 +#define SP_TX_H_SYNC_STA_H 0x32 +#define SP_TX_H_B_PORCH_STA_L 0x33 +#define SP_TX_H_B_PORCH_STA_H 0x34 + +#define SP_TX_VID_CTRL 0x84 +#define SP_TX_BPC_MASK 0xE0 +#define SP_TX_BPC_6 0x00 +#define SP_TX_BPC_8 0x20 +#define SP_TX_BPC_10 0x40 +#define SP_TX_BPC_12 0x60 + +#define VIDEO_BIT_MATRIX_12 0x4c + +#define AUDIO_CHANNEL_STATUS_1 0xd0 +#define AUDIO_CHANNEL_STATUS_2 0xd1 +#define AUDIO_CHANNEL_STATUS_3 0xd2 +#define AUDIO_CHANNEL_STATUS_4 0xd3 +#define AUDIO_CHANNEL_STATUS_5 0xd4 +#define AUDIO_CHANNEL_STATUS_6 0xd5 +#define TDM_SLAVE_MODE 0x10 +#define I2S_SLAVE_MODE 0x08 + +#define AUDIO_CONTROL_REGISTER 0xe6 +#define TDM_TIMING_MODE 0x08 + +#define I2C_ADDR_72_DPTX 0x72 + +#define VIDEO_CONTROL_0 0x08 + +#define ACTIVE_LINES_L 0x14 +#define ACTIVE_LINES_H 0x15 /* note: bit[7:6] are reserved */ +#define VERTICAL_FRONT_PORCH 0x16 +#define VERTICAL_SYNC_WIDTH 0x17 +#define VERTICAL_BACK_PORCH 0x18 + +#define HORIZONTAL_TOTAL_PIXELS_L 0x19 +#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* note: bit[7:6] are reserved */ +#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B +#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* note: bit[7:6] are reserved */ +#define HORIZONTAL_FRONT_PORCH_L 0x1D +#define HORIZONTAL_FRONT_PORCH_H 0x1E /* note: bit[7:4] are reserved */ +#define HORIZONTAL_SYNC_WIDTH_L 0x1F +#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* note: bit[7:4] are reserved */ +#define HORIZONTAL_BACK_PORCH_L 0x21 +#define HORIZONTAL_BACK_PORCH_H 0x22 /* note: bit[7:4] are reserved */ + +/******** END of I2C Address 0x72 *********/ +/***************************************************************/ +/* Register definition of device address 0x7e */ + +#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E + +#define XTAL_FRQ_SEL 0x3F +/* bit field positions */ +#define XTAL_FRQ_SEL_POS 5 +/* bit field values */ +#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) +#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) + +#define R_DSC_CTRL_0 0x40 +#define READ_STATUS_EN 7 +#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ +#define DSC_BIST_DONE 1 /* bit[5:1]: 1=DSC MBIST pass */ +#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ + +#define OCM_FW_VERSION 0x31 +#define OCM_FW_REVERSION 0x32 + +#define AP_AUX_ADDR_7_0 0x11 +#define AP_AUX_ADDR_15_8 0x12 +#define AP_AUX_ADDR_19_16 0x13 + +/* note: bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ +#define AP_AUX_CTRL_STATUS 0x14 +#define AP_AUX_CTRL_OP_EN 0x10 +#define AP_AUX_CTRL_ADDRONLY 0x20 + +#define AP_AUX_BUFF_START 0x15 +#define PIXEL_CLOCK_L 0x25 +#define PIXEL_CLOCK_H 0x26 + +#define AP_AUX_COMMAND 0x27 /* com+len */ +/* bit 0&1: 3D video structure */ +/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ +#define AP_AV_STATUS 0x28 +#define AP_VIDEO_CHG (1<<2) +#define AP_AUDIO_CHG (1<<3) +#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */ +#define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ +#define AP_DISABLE_PD (1<<6) +#define AP_DISABLE_DISPLAY (1<<7) +/***************************************************************/ +/* Register definition of device address 0x84 */ +#define MIPI_PHY_CONTROL_3 0x03 +#define MIPI_HS_PWD_CLK 7 +#define MIPI_HS_RT_CLK 6 +#define MIPI_PD_CLK 5 +#define MIPI_CLK_RT_MANUAL_PD_EN 4 +#define MIPI_CLK_HS_MANUAL_PD_EN 3 +#define MIPI_CLK_DET_DET_BYPASS 2 +#define MIPI_CLK_MISS_CTRL 1 +#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 + +#define MIPI_LANE_CTRL_0 0x05 +#define MIPI_TIME_HS_PRPR 0x08 + +/* After MIPI RX protocol layer received this many video frames, */ +/* protocol layer starts to reconstruct video stream from PHY */ +#define MIPI_VIDEO_STABLE_CNT 0x0A + +#define MIPI_LANE_CTRL_10 0x0F +#define MIPI_DIGITAL_ADJ_1 0x1B + +#define MIPI_PLL_M_NUM_23_16 0x1E +#define MIPI_PLL_M_NUM_15_8 0x1F +#define MIPI_PLL_M_NUM_7_0 0x20 +#define MIPI_PLL_N_NUM_23_16 0x21 +#define MIPI_PLL_N_NUM_15_8 0x22 +#define MIPI_PLL_N_NUM_7_0 0x23 + +#define MIPI_DIGITAL_PLL_6 0x2A +/* bit[7:6]: VCO band control, only effective */ +/* when MIPI_PLL_FORCE_BAND_EN (0x84:0x2B[6]) is 1 */ +#define MIPI_M_NUM_READY 0x10 +#define MIPI_N_NUM_READY 0x08 +#define STABLE_INTEGER_CNT_EN 0x04 +#define MIPI_PLL_TEST_BIT 0 +/* bit[1:0]: test point output select - */ +/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ + +#define MIPI_DIGITAL_PLL_7 0x2B +#define MIPI_PLL_FORCE_N_EN 7 +#define MIPI_PLL_FORCE_BAND_EN 6 + +#define MIPI_PLL_VCO_TUNE_REG 4 +/* bit[5:4]: VCO metal capacitance - */ +/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ +#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 + +#define MIPI_PLL_PLL_LDO_BIT 2 +/* bit[3:2]: vco_v2i power - */ +/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ +#define MIPI_PLL_RESET_N 0x02 +#define MIPI_FRQ_FORCE_NDET 0 + +#define MIPI_ALERT_CLR_0 0x2D +#define HS_link_error_clear 7 +/* This bit itself is S/C, and it clears 0x84:0x31[7] */ + +#define MIPI_ALERT_OUT_0 0x31 +#define check_sum_err_hs_sync 7 +/* This bit is cleared by 0x84:0x2D[7] */ + +#define MIPI_DIGITAL_PLL_8 0x33 +#define MIPI_POST_DIV_VAL 4 +/* n means divided by (n+1), n = 0~15 */ +#define MIPI_EN_LOCK_FRZ 3 +#define MIPI_FRQ_COUNTER_RST 2 +#define MIPI_FRQ_SET_REG_8 1 +/* bit 0 is reserved */ + +#define MIPI_DIGITAL_PLL_9 0x34 + +#define MIPI_DIGITAL_PLL_16 0x3B +#define MIPI_FRQ_FREEZE_NDET 7 +#define MIPI_FRQ_REG_SET_ENABLE 6 +#define MIPI_REG_FORCE_SEL_EN 5 +#define MIPI_REG_SEL_DIV_REG 4 +#define MIPI_REG_FORCE_PRE_DIV_EN 3 +/* bit 2 is reserved */ +#define MIPI_FREF_D_IND 1 +#define REF_CLK_27000kHz 1 +#define REF_CLK_19200kHz 0 +#define MIPI_REG_PLL_PLL_TEST_ENABLE 0 + +#define MIPI_DIGITAL_PLL_18 0x3D +#define FRQ_COUNT_RB_SEL 7 +#define REG_FORCE_POST_DIV_EN 6 +#define MIPI_DPI_SELECT 5 +#define SELECT_DSI 1 +#define SELECT_DPI 0 +#define REG_BAUD_DIV_RATIO 0 + +#define H_BLANK_L 0x3E +/* for DSC only */ +#define H_BLANK_H 0x3F +/* for DSC only; note: bit[7:6] are reserved */ +#define MIPI_SWAP 0x4A +#define MIPI_SWAP_CH0 7 +#define MIPI_SWAP_CH1 6 +#define MIPI_SWAP_CH2 5 +#define MIPI_SWAP_CH3 4 +#define MIPI_SWAP_CLK 3 +/* bit[2:0] are reserved */ + +/******** END of I2C Address 0x84 *********/ + +/* DPCD regs */ +#define DPCD_DPCD_REV 0x00 +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_MAX_LANE_COUNT 0x02 + +/********* ANX7625 Register End **********/ + +/***************** Display *****************/ +enum AudioFs { + AUDIO_FS_441K = 0x00, + AUDIO_FS_48K = 0x02, + AUDIO_FS_32K = 0x03, + AUDIO_FS_882K = 0x08, + AUDIO_FS_96K = 0x0a, + AUDIO_FS_1764K = 0x0c, + AUDIO_FS_192K = 0x0e +}; + +enum AudioWdLen { + AUDIO_W_LEN_16_20MAX = 0x02, + AUDIO_W_LEN_18_20MAX = 0x04, + AUDIO_W_LEN_17_20MAX = 0x0c, + AUDIO_W_LEN_19_20MAX = 0x08, + AUDIO_W_LEN_20_20MAX = 0x0a, + AUDIO_W_LEN_20_24MAX = 0x03, + AUDIO_W_LEN_22_24MAX = 0x05, + AUDIO_W_LEN_21_24MAX = 0x0d, + AUDIO_W_LEN_23_24MAX = 0x09, + AUDIO_W_LEN_24_24MAX = 0x0b +}; + +#define I2S_CH_2 0x01 +#define TDM_CH_4 0x03 +#define TDM_CH_6 0x05 +#define TDM_CH_8 0x07 + +#define MAX_DPCD_BUFFER_SIZE 16 + +#define ONE_BLOCK_SIZE 128 +#define FOUR_BLOCK_SIZE (128*4) + +struct display_timing { + unsigned int pixelclock; + unsigned int hactive; + unsigned int hfront_porch; + unsigned int hback_porch; + unsigned int hsync_len; + unsigned int vactive; + unsigned int vfront_porch; + unsigned int vback_porch; + unsigned int vsync_len; +}; + +int anx7625_dp_start(uint8_t bus, struct edid *edid); +int anx7625_dp_get_edid(uint8_t bus, struct edid *out); +int anx7625_init(uint8_t bus); +#endif /* __ANX7625_H__ */ diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 2828918..bab96ad 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -42,7 +42,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JACUZZI select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 2e8a79a..7839422 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -30,4 +30,6 @@ ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c + ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c new file mode 100644 index 0000000..10cbf5c --- /dev/null +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> +#include <string.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); //1.0 + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); //3.3 + gpio_output(GPIO_PP1800_LCM_EN, 1); //1.8 + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 4; + mtk_i2c_bus_init(i2c_bus); + + anx7625_init(i2c_bus); + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + anx7625_dp_start(i2c_bus, edid); + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Gerrit-Change-Number: 35623 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: security/vboot: Boot to Recovery Mode if no RW slot present
by Bill XIE (Code Review) 17 Dec '19

17 Dec '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34977 ) Change subject: security/vboot: Boot to Recovery Mode if no RW slot present ...................................................................... security/vboot: Boot to Recovery Mode if no RW slot present Currently, even if there is no RW slot present, vboot will still try to find one to boot, result in an infinite boot loop. This change explicitly allows a coreboot build with vboot but without RW slot to make use of vboot only for measured boot, by performing "Recovery mode" boot, with stages and payloads in the RO slot. Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/security/vboot/vboot_logic.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34977/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7f00df5..48fd6db 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -347,7 +347,9 @@ "Initializing measured boot mode failed!"); } - if (get_recovery_mode_switch()) { + /* Boot to Recovery Mode if no RW slot present */ + if (!CONFIG(VBOOT_SLOTS_RW_A) || + get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; -- To view, visit https://review.coreboot.org/c/coreboot/+/34977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Gerrit-Change-Number: 34977 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message...
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35228 to review the following change. Change subject: src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message() defined in common code ...................................................................... src/soc/intel/(cnl,skl,icl): Remove, and call send_heci_reset_message() defined in common code Removed send_heci_reset_message() from socs(cnl/skl/icl), and made changes to call function send_heci_reset_req_message() defined in the common code. Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> --- M src/soc/intel/cannonlake/reset.c M src/soc/intel/icelake/reset.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 3 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35228/1 diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index e92396f3..e01c22c 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -22,65 +22,10 @@ #include <string.h> #include <soc/pci_devs.h> -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 470b5f4..d83b3ee 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -22,65 +22,10 @@ #include <string.h> #include <soc/pci_devs.h> -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b -#define MKHI_STATUS_SUCCESS 0 - -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 - -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 1) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - if (!heci_receive(&reply, &reply_size)) - return -1; - if (reply.result != MKHI_STATUS_SUCCESS) { - printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); - return -1; - } - printk(BIOS_DEBUG, "Heci receive success!\n"); - return 0; -} - void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_message()) + if (!send_heci_reset_req_message(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index fbe5033..bec54d8 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -197,17 +197,8 @@ #define MKHI_GEN_GROUP_ID 0xff -/* Reset Request */ -#define MKHI_GLOBAL_RESET 0x0b - #define MKHI_GET_FW_VERSION 0x02 -#define GR_ORIGIN_BIOS_MEM_INIT 0x01 -#define GR_ORIGIN_BIOS_POST 0x02 -#define GR_ORIGIN_MEBX 0x03 - -#define GLOBAL_RST_TYPE 0x01 - #define BIOS_HOST_ADD 0x00 #define HECI_MKHI_ADD 0x07 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index e8d75e3..fde4b13 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -431,50 +431,6 @@ } } -static int send_heci_reset_message(void) -{ - int status; - struct reset_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - } __packed reply; - struct reset_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u8 req_origin; - u8 reset_type; - } __packed; - struct reset_message msg = { - .cmd = MKHI_GLOBAL_RESET, - .req_origin = GR_ORIGIN_BIOS_POST, - .reset_type = GLOBAL_RST_TYPE - }; - size_t reply_size; - - heci_reset(); - - status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); - if (!status) - return -1; - - reply_size = sizeof(reply); - memset(&reply, 0, reply_size); - status = heci_receive(&reply, &reply_size); - if (!status) - return -1; - /* get reply result from HECI MSG */ - if (reply.result) { - printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); - return -1; - } - printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); - return 0; -} - int send_global_reset(void) { int status = -1; @@ -486,7 +442,7 @@ goto ret; /* ME should be in Normal Mode for this command */ - status = send_heci_reset_message(); + status = send_heci_reset_req_message(GLOBAL_RESET); ret: return status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Gerrit-Change-Number: 35228 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/chip/Kconfig: Fix minor whitespace
by HIMANSHU SAHDEV (Code Review) 16 Dec '19

16 Dec '19

HIMANSHU SAHDEV has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35291 ) Change subject: soc/intel/common/block/chip/Kconfig: Fix minor whitespace ...................................................................... soc/intel/common/block/chip/Kconfig: Fix minor whitespace Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan(a)gmail.com> --- M src/soc/intel/common/block/chip/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35291/1 diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig index 273d088..8021c24 100644 --- a/src/soc/intel/common/block/chip/Kconfig +++ b/src/soc/intel/common/block/chip/Kconfig @@ -1,4 +1,4 @@ config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG bool help - Intel Processor common soc/ chip configuration support + Intel Processor common soc/chip configuration support -- To view, visit https://review.coreboot.org/c/coreboot/+/35291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Gerrit-Change-Number: 35291 Gerrit-PatchSet: 1 Gerrit-Owner: HIMANSHU SAHDEV <sahdev.himan(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33964 Change subject: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx ...................................................................... cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx Change-Id: I8108398071a6ff7bceb90741581522023a786afd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33964/1 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c3..5d23ce5 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -76,7 +76,7 @@ struct pde pdp[512]; } __packed; -void paging_enable_pae_cr3(uintptr_t cr3) +void paging_enable_pae_cr3(CRx_TYPE cr3) { /* Load the page table address */ write_cr3(cr3); @@ -198,7 +198,7 @@ /* Get pointer to PD that's not identity mapped */ pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); do { const size_t len = MIN(length, s2MiB - offset); @@ -279,7 +279,7 @@ | ((i & 0x3ff) << 21) | 0xE3; pd[i].addr_hi = (window >> 1); } - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); } mapped_window[index] = window; } @@ -376,7 +376,7 @@ return -1; } - paging_enable_pae_cr3((uintptr_t)_pdpt); + paging_enable_pae_cr3((CRx_TYPE)_pdpt); return 0; } diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 72bae53..6464503 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -22,7 +22,7 @@ /* Enable paging with cr3 value for page directory pointer table as well as PAE option in cr4. */ -void paging_enable_pae_cr3(uintptr_t cr3); +void paging_enable_pae_cr3(CRx_TYPE cr3); /* Enable paging as well as PAE option in cr4. */ void paging_enable_pae(void); /* Disable paging as well as PAE option in cr4. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8108398071a6ff7bceb90741581522023a786afd Gerrit-Change-Number: 33964 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/sandybridge/raminit_common.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33005 Change subject: nb/sandybridge/raminit_common.c: Remove variable set but not used ...................................................................... nb/sandybridge/raminit_common.c: Remove variable set but not used Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33005/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..b8ad3c0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1824,7 +1824,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane, old; + int channel, slotrank, lane; MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -1898,15 +1898,18 @@ 0x100 * channel + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + 0x100 * channel + 8)) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, - slotrank, lane, old, + printram("Bval+: %d, %d, %d, %x", channel, + slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB); + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + printram(" -> %x\n", + ctrl->timings[channel][slotrank].lanes[lane]. + timB); + } } MCHBAR32(0x3400) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Gerrit-Change-Number: 33005 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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