John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32087
Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept
......................................................................
Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept
Signed-off-by: John Looney <john.looney(a)gmail.com>
Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2
---
A src/mainboard/emulation/qemu-q35/board.fmd
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/32087/1
diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd
new file mode 100644
index 0000000..a97e218
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/board.fmd
@@ -0,0 +1,16 @@
+# layout for firmware residing at top of 4GB address space
+# +-------------+ <-- 4GB - ROM_SIZE / start of flash
+# | unspecified |
+# +-------------+ <-- 4GB - BIOS_SIZE
+# | FMAP |
+# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE
+# | CBFS |
+# +-------------+ <-- 4GB / end of flash
+FLASH@4278190080 0x1000000 {
+ BIOS@0 0x1000000 {
+ FMAP@0 0x200
+ RO_VPD@0x200 0x10000
+ RW_VPD@0x10200 0x1000
+ COREBOOT(CBFS)@0x11200
+ }
+}
--
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Gerrit-Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2
Gerrit-Change-Number: 32087
Gerrit-PatchSet: 1
Gerrit-Owner: John Looney <john.looney(a)gmail.com>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253
Change subject: Documentation: Document PMH known registers
......................................................................
Documentation: Document PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/pmh.md
2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index d94c23e..adfe877 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -54,6 +54,7 @@
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
+- [PMH](lenovo/pmh.md)
### Sandy Bridge series
diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md
new file mode 100644
index 0000000..06c595d
--- /dev/null
+++ b/Documentation/mainboard/lenovo/pmh.md
@@ -0,0 +1,69 @@
+# Lenovo's Power Management Hub
+
+The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC
+to controll power rails and reset lines on the lenovo mainboard.
+Starting with Ivy Bridge series, the CPLD was removed and an EC with higher
+pincount does the same job. The IO space to configure the PMH is still
+the same.
+
+## PMH access
+
+The PMH register can be accessed using the IO region:
+
+ IO region address: 0x15e0
+ IO region size: 16
+
+The IO region has the following layout:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0xc | ADDR_L: Low address into PMH space |
++-------------------+---------------------------------------+
+| 0xd | ADDR_H: High address into PMH space |
++-------------------+---------------------------------------+
+| 0xe | DATA: The data to read/write in PMH |
++-------------------+---------------------------------------+
+```
+
+The PMH register space allows to access 512bytes.
+The following registers are known:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0x50 | BIT3: dGPU power enable |
+| +---------------------------------------+
+| | BIT5: Backlight enable |
+| +---------------------------------------+
+| | BIT7: dGPU !reset |
++-------------------+---------------------------------------+
+| 0x51 | BIT0: Trackpoint enable |
+| +---------------------------------------+
+| | BIT2: Touchpad enable |
++-------------------+---------------------------------------+
+| 0x60 | BIT3: Dock event enable |
++-------------------+---------------------------------------+
+| 0x62 | BIT0: Ultrabay power enable |
++-------------------+---------------------------------------+
+| 0xc2 | ID: ID of PMH |
++-------------------+---------------------------------------+
+| 0xc3 | REV: Revision of PMH |
++-------------------+---------------------------------------+
+```
+
+The revision at 0xc3 seems to increment over time:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Revision | Mainboard generation |
++-------------------+---------------------------------------+
+| 4 | T520 and T420s |
++-------------------+---------------------------------------+
+| 5 | W530 |
++-------------------+---------------------------------------+
+| 6 | T470p |
++-------------------+---------------------------------------+
+```
--
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Gerrit-Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed
Gerrit-Change-Number: 32253
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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Pixie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32372
Change subject: Supplement motherboard name for G41M-GS
......................................................................
Supplement motherboard name for G41M-GS
A few months ago, Arthur Heymans rebased a few patches to add
support for the G41M-GS to aid me in testing my G41M-S. The
two boards are exact duplicates, save for the -GS having a
gigabit LAN chip, and the G41M-S having a 100Mbit one. I did
some scant testing, and it worked, but I had a lot of other
projects ongoing. Now that I remembered thisagain, I'm here
to commit the motherboard name.
Signed-off-by: Cheetah Pixie <mayulithsv(a)gmail.com>
Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311
---
M src/mainboard/asrock/g41c-gs/Kconfig.name
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32372/1
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name
index 86a41aa..1a090ff3 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig.name
+++ b/src/mainboard/asrock/g41c-gs/Kconfig.name
@@ -5,7 +5,7 @@
bool "G41C-GS / G41C-S"
config BOARD_ASROCK_G41M_GS
- bool "G41M-GS"
+ bool "G41M-GS / G41M-S"
config BOARD_ASROCK_G41M_S3
bool "G41M-S3"
--
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Gerrit-Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311
Gerrit-Change-Number: 32372
Gerrit-PatchSet: 1
Gerrit-Owner: Pixie <mayulithsv(a)gmail.com>
Gerrit-MessageType: newchange
Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33367
Change subject: commonlib: reliicense to for > GPL-2
......................................................................
commonlib: reliicense to for > GPL-2
Allow compatibility with > GPL-2 code bases such that the current
implementations of:
- iobuf
- mem_pol
- region
can be utilitized in other projects.
Change-Id: If4d947d87bf04313a956e2bece9399c3dc770f19
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
M src/commonlib/include/commonlib/iobuf.h
M src/commonlib/include/commonlib/mem_pool.h
M src/commonlib/include/commonlib/region.h
M src/commonlib/iobuf.c
M src/commonlib/mem_pool.c
M src/commonlib/region.c
6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33367/1
diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h
index c5a0f4c..fee789e 100644
--- a/src/commonlib/include/commonlib/iobuf.h
+++ b/src/commonlib/include/commonlib/iobuf.h
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
index c21fa0e..0b6f08c 100644
--- a/src/commonlib/include/commonlib/mem_pool.h
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
index 45484dd..efb7931 100644
--- a/src/commonlib/include/commonlib/region.h
+++ b/src/commonlib/include/commonlib/region.h
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/commonlib/iobuf.c b/src/commonlib/iobuf.c
index b73ee19..219d692 100644
--- a/src/commonlib/iobuf.c
+++ b/src/commonlib/iobuf.c
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
index cb3e726..69b1160 100644
--- a/src/commonlib/mem_pool.c
+++ b/src/commonlib/mem_pool.c
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
index 541a125..8840ecd 100644
--- a/src/commonlib/region.c
+++ b/src/commonlib/region.c
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
--
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